1 // SPDX-License-Identifier: GPL-2.0+
2 #include <linux/bitfield.h>
3 #include <linux/module.h>
4 #include <linux/nvmem-consumer.h>
5 #include <linux/of_address.h>
6 #include <linux/of_platform.h>
7 #include <linux/pinctrl/consumer.h>
10 #define MTK_GPHY_ID_MT7981 0x03a29461
11 #define MTK_GPHY_ID_MT7988 0x03a29481
13 #define MTK_EXT_PAGE_ACCESS 0x1f
14 #define MTK_PHY_PAGE_STANDARD 0x0000
15 #define MTK_PHY_PAGE_EXTENDED_3 0x0003
17 #define MTK_PHY_LPI_REG_14 0x14
18 #define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0)
20 #define MTK_PHY_LPI_REG_1c 0x1c
21 #define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8)
23 #define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30
24 #define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
26 #define ANALOG_INTERNAL_OPERATION_MAX_US 20
27 #define TXRESERVE_MIN 0
28 #define TXRESERVE_MAX 7
30 #define MTK_PHY_ANARG_RG 0x10
31 #define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8)
33 /* Registers on MDIO_MMD_VEND1 */
34 #define MTK_PHY_TXVLD_DA_RG 0x12
35 #define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10)
36 #define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0)
38 #define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16
39 #define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10)
40 #define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0)
42 #define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17
43 #define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8)
44 #define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0)
46 #define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18
47 #define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8)
48 #define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0)
50 #define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19
51 #define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8)
52 #define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0)
54 #define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20
55 #define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8)
56 #define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0)
58 #define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21
59 #define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8)
60 #define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0)
62 #define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22
63 #define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8)
64 #define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0)
66 #define MTK_PHY_RXADC_CTRL_RG7 0xc6
67 #define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8)
69 #define MTK_PHY_RXADC_CTRL_RG9 0xc8
70 #define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12)
71 #define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8)
72 #define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4)
73 #define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0)
75 #define MTK_PHY_LDO_OUTPUT_V 0xd7
77 #define MTK_PHY_RG_ANA_CAL_RG0 0xdb
78 #define MTK_PHY_RG_CAL_CKINV BIT(12)
79 #define MTK_PHY_RG_ANA_CALEN BIT(8)
80 #define MTK_PHY_RG_ZCALEN_A BIT(0)
82 #define MTK_PHY_RG_ANA_CAL_RG1 0xdc
83 #define MTK_PHY_RG_ZCALEN_B BIT(12)
84 #define MTK_PHY_RG_ZCALEN_C BIT(8)
85 #define MTK_PHY_RG_ZCALEN_D BIT(4)
86 #define MTK_PHY_RG_TXVOS_CALEN BIT(0)
88 #define MTK_PHY_RG_ANA_CAL_RG5 0xe0
89 #define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8)
91 #define MTK_PHY_RG_TX_FILTER 0xfe
93 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120
94 #define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8)
95 #define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0)
97 #define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122
98 #define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0)
100 #define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144
101 #define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5)
103 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172
104 #define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8)
105 #define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0)
107 #define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173
108 #define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8)
109 #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0)
111 #define MTK_PHY_RG_AD_CAL_COMP 0x17a
112 #define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8)
114 #define MTK_PHY_RG_AD_CAL_CLK 0x17b
115 #define MTK_PHY_DA_CAL_CLK BIT(0)
117 #define MTK_PHY_RG_AD_CALIN 0x17c
118 #define MTK_PHY_DA_CALIN_FLAG BIT(0)
120 #define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d
121 #define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0)
123 #define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e
124 #define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0)
126 #define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f
127 #define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0)
129 #define MTK_PHY_RG_DASN_DAC_IN0_D 0x180
130 #define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0)
132 #define MTK_PHY_RG_DASN_DAC_IN1_A 0x181
133 #define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0)
135 #define MTK_PHY_RG_DASN_DAC_IN1_B 0x182
136 #define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0)
138 #define MTK_PHY_RG_DASN_DAC_IN1_C 0x183
139 #define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0)
141 #define MTK_PHY_RG_DASN_DAC_IN1_D 0x184
142 #define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0)
144 #define MTK_PHY_RG_DEV1E_REG19b 0x19b
145 #define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8)
147 #define MTK_PHY_RG_LP_IIR2_K1_L 0x22a
148 #define MTK_PHY_RG_LP_IIR2_K1_U 0x22b
149 #define MTK_PHY_RG_LP_IIR2_K2_L 0x22c
150 #define MTK_PHY_RG_LP_IIR2_K2_U 0x22d
151 #define MTK_PHY_RG_LP_IIR2_K3_L 0x22e
152 #define MTK_PHY_RG_LP_IIR2_K3_U 0x22f
153 #define MTK_PHY_RG_LP_IIR2_K4_L 0x230
154 #define MTK_PHY_RG_LP_IIR2_K4_U 0x231
155 #define MTK_PHY_RG_LP_IIR2_K5_L 0x232
156 #define MTK_PHY_RG_LP_IIR2_K5_U 0x233
158 #define MTK_PHY_RG_DEV1E_REG234 0x234
159 #define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0)
160 #define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4)
161 #define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12)
163 #define MTK_PHY_RG_LPF_CNT_VAL 0x235
165 #define MTK_PHY_RG_DEV1E_REG238 0x238
166 #define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0)
167 #define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12)
169 #define MTK_PHY_RG_DEV1E_REG239 0x239
170 #define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0)
171 #define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12)
173 #define MTK_PHY_RG_DEV1E_REG27C 0x27c
174 #define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8)
175 #define MTK_PHY_RG_DEV1E_REG27D 0x27d
176 #define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0)
178 #define MTK_PHY_RG_DEV1E_REG2C7 0x2c7
179 #define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0)
180 #define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8)
182 #define MTK_PHY_RG_DEV1E_REG2D1 0x2d1
183 #define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0)
184 #define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8)
185 #define MTK_PHY_LPI_TR_READY BIT(9)
186 #define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10)
188 #define MTK_PHY_RG_DEV1E_REG323 0x323
189 #define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0)
190 #define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4)
192 #define MTK_PHY_RG_DEV1E_REG324 0x324
193 #define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0)
194 #define MTK_PHY_SMI_DET_MAX_EN BIT(8)
196 #define MTK_PHY_RG_DEV1E_REG326 0x326
197 #define MTK_PHY_LPI_MODE_SD_ON BIT(0)
198 #define MTK_PHY_RESET_RANDUPD_CNT BIT(1)
199 #define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2)
200 #define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4)
201 #define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5)
203 #define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502
204 #define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503
206 #define MTK_PHY_DA_TX_R50_PAIR_A 0x53d
207 #define MTK_PHY_DA_TX_R50_PAIR_B 0x53e
208 #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
209 #define MTK_PHY_DA_TX_R50_PAIR_D 0x540
211 /* Registers on MDIO_MMD_VEND2 */
212 #define MTK_PHY_LED0_ON_CTRL 0x24
213 #define MTK_PHY_LED0_ON_MASK GENMASK(6, 0)
214 #define MTK_PHY_LED0_ON_LINK1000 BIT(0)
215 #define MTK_PHY_LED0_ON_LINK100 BIT(1)
216 #define MTK_PHY_LED0_ON_LINK10 BIT(2)
217 #define MTK_PHY_LED0_ON_LINKDOWN BIT(3)
218 #define MTK_PHY_LED0_ON_FDX BIT(4) /* Full duplex */
219 #define MTK_PHY_LED0_ON_HDX BIT(5) /* Half duplex */
220 #define MTK_PHY_LED0_FORCE_ON BIT(6)
221 #define MTK_PHY_LED0_POLARITY BIT(14)
222 #define MTK_PHY_LED0_ENABLE BIT(15)
224 #define MTK_PHY_LED0_BLINK_CTRL 0x25
225 #define MTK_PHY_LED0_1000TX BIT(0)
226 #define MTK_PHY_LED0_1000RX BIT(1)
227 #define MTK_PHY_LED0_100TX BIT(2)
228 #define MTK_PHY_LED0_100RX BIT(3)
229 #define MTK_PHY_LED0_10TX BIT(4)
230 #define MTK_PHY_LED0_10RX BIT(5)
231 #define MTK_PHY_LED0_COLLISION BIT(6)
232 #define MTK_PHY_LED0_RX_CRC_ERR BIT(7)
233 #define MTK_PHY_LED0_RX_IDLE_ERR BIT(8)
234 #define MTK_PHY_LED0_FORCE_BLINK BIT(9)
236 #define MTK_PHY_LED1_ON_CTRL 0x26
237 #define MTK_PHY_LED1_ON_MASK GENMASK(6, 0)
238 #define MTK_PHY_LED1_ON_LINK1000 BIT(0)
239 #define MTK_PHY_LED1_ON_LINK100 BIT(1)
240 #define MTK_PHY_LED1_ON_LINK10 BIT(2)
241 #define MTK_PHY_LED1_ON_LINKDOWN BIT(3)
242 #define MTK_PHY_LED1_ON_FDX BIT(4) /* Full duplex */
243 #define MTK_PHY_LED1_ON_HDX BIT(5) /* Half duplex */
244 #define MTK_PHY_LED1_FORCE_ON BIT(6)
245 #define MTK_PHY_LED1_POLARITY BIT(14)
246 #define MTK_PHY_LED1_ENABLE BIT(15)
248 #define MTK_PHY_LED1_BLINK_CTRL 0x27
249 #define MTK_PHY_LED1_1000TX BIT(0)
250 #define MTK_PHY_LED1_1000RX BIT(1)
251 #define MTK_PHY_LED1_100TX BIT(2)
252 #define MTK_PHY_LED1_100RX BIT(3)
253 #define MTK_PHY_LED1_10TX BIT(4)
254 #define MTK_PHY_LED1_10RX BIT(5)
255 #define MTK_PHY_LED1_COLLISION BIT(6)
256 #define MTK_PHY_LED1_RX_CRC_ERR BIT(7)
257 #define MTK_PHY_LED1_RX_IDLE_ERR BIT(8)
258 #define MTK_PHY_LED1_FORCE_BLINK BIT(9)
260 #define MTK_PHY_RG_BG_RASEL 0x115
261 #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
263 /* These macro privides efuse parsing for internal phy. */
264 #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
265 #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
266 #define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0))
267 #define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0))
268 #define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0))
270 #define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0))
271 #define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0))
272 #define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0))
273 #define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0))
274 #define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0))
276 #define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0))
277 #define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0))
279 #define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0))
280 #define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0))
297 enum calibration_mode
{
315 struct mtk_socphy_shared_priv
{
319 static int mtk_socphy_read_page(struct phy_device
*phydev
)
321 return __phy_read(phydev
, MTK_EXT_PAGE_ACCESS
);
324 static int mtk_socphy_write_page(struct phy_device
*phydev
, int page
)
326 return __phy_write(phydev
, MTK_EXT_PAGE_ACCESS
, page
);
329 /* One calibration cycle consists of:
330 * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high
331 * until AD_CAL_COMP is ready to output calibration result.
332 * 2.Wait until DA_CAL_CLK is available.
333 * 3.Fetch AD_CAL_COMP_OUT.
335 static int cal_cycle(struct phy_device
*phydev
, int devad
,
336 u32 regnum
, u16 mask
, u16 cal_val
)
341 phy_modify_mmd(phydev
, devad
, regnum
,
343 phy_set_bits_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_AD_CALIN
,
344 MTK_PHY_DA_CALIN_FLAG
);
346 ret
= phy_read_mmd_poll_timeout(phydev
, MDIO_MMD_VEND1
,
347 MTK_PHY_RG_AD_CAL_CLK
, reg_val
,
348 reg_val
& MTK_PHY_DA_CAL_CLK
, 500,
349 ANALOG_INTERNAL_OPERATION_MAX_US
, false);
351 phydev_err(phydev
, "Calibration cycle timeout\n");
355 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_AD_CALIN
,
356 MTK_PHY_DA_CALIN_FLAG
);
357 ret
= phy_read_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_AD_CAL_COMP
) >>
358 MTK_PHY_AD_CAL_COMP_OUT_SHIFT
;
359 phydev_dbg(phydev
, "cal_val: 0x%x, ret: %d\n", cal_val
, ret
);
364 static int rext_fill_result(struct phy_device
*phydev
, u16
*buf
)
366 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_ANA_CAL_RG5
,
367 MTK_PHY_RG_REXT_TRIM_MASK
, buf
[0] << 8);
368 phy_modify_mmd(phydev
, MDIO_MMD_VEND2
, MTK_PHY_RG_BG_RASEL
,
369 MTK_PHY_RG_BG_RASEL_MASK
, buf
[1]);
374 static int rext_cal_efuse(struct phy_device
*phydev
, u32
*buf
)
378 rext_cal_val
[0] = EFS_RG_REXT_TRIM(buf
[3]);
379 rext_cal_val
[1] = EFS_RG_BG_RASEL(buf
[3]);
380 rext_fill_result(phydev
, rext_cal_val
);
385 static int tx_offset_fill_result(struct phy_device
*phydev
, u16
*buf
)
387 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B
,
388 MTK_PHY_CR_TX_AMP_OFFSET_A_MASK
, buf
[0] << 8);
389 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B
,
390 MTK_PHY_CR_TX_AMP_OFFSET_B_MASK
, buf
[1]);
391 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D
,
392 MTK_PHY_CR_TX_AMP_OFFSET_C_MASK
, buf
[2] << 8);
393 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D
,
394 MTK_PHY_CR_TX_AMP_OFFSET_D_MASK
, buf
[3]);
399 static int tx_offset_cal_efuse(struct phy_device
*phydev
, u32
*buf
)
401 u16 tx_offset_cal_val
[4];
403 tx_offset_cal_val
[0] = EFS_DA_TX_AMP_OFFSET_A(buf
[0]);
404 tx_offset_cal_val
[1] = EFS_DA_TX_AMP_OFFSET_B(buf
[1]);
405 tx_offset_cal_val
[2] = EFS_DA_TX_AMP_OFFSET_C(buf
[1]);
406 tx_offset_cal_val
[3] = EFS_DA_TX_AMP_OFFSET_D(buf
[1]);
408 tx_offset_fill_result(phydev
, tx_offset_cal_val
);
413 static int tx_amp_fill_result(struct phy_device
*phydev
, u16
*buf
)
417 const int vals_9461
[16] = { 7, 1, 4, 7,
421 const int vals_9481
[16] = { 10, 6, 6, 10,
425 switch (phydev
->drv
->phy_id
) {
426 case MTK_GPHY_ID_MT7981
:
427 /* We add some calibration to efuse values
428 * due to board level influence.
429 * GBE: +7, TBT: +1, HBT: +4, TST: +7
431 memcpy(bias
, (const void *)vals_9461
, sizeof(bias
));
433 case MTK_GPHY_ID_MT7988
:
434 memcpy(bias
, (const void *)vals_9481
, sizeof(bias
));
438 /* Prevent overflow */
439 for (i
= 0; i
< 12; i
++) {
440 if (buf
[i
>> 2] + bias
[i
] > 63) {
446 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TXVLD_DA_RG
,
447 MTK_PHY_DA_TX_I2MPB_A_GBE_MASK
, (buf
[0] + bias
[0]) << 10);
448 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TXVLD_DA_RG
,
449 MTK_PHY_DA_TX_I2MPB_A_TBT_MASK
, buf
[0] + bias
[1]);
450 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TX_I2MPB_TEST_MODE_A2
,
451 MTK_PHY_DA_TX_I2MPB_A_HBT_MASK
, (buf
[0] + bias
[2]) << 10);
452 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TX_I2MPB_TEST_MODE_A2
,
453 MTK_PHY_DA_TX_I2MPB_A_TST_MASK
, buf
[0] + bias
[3]);
455 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TX_I2MPB_TEST_MODE_B1
,
456 MTK_PHY_DA_TX_I2MPB_B_GBE_MASK
, (buf
[1] + bias
[4]) << 8);
457 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TX_I2MPB_TEST_MODE_B1
,
458 MTK_PHY_DA_TX_I2MPB_B_TBT_MASK
, buf
[1] + bias
[5]);
459 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TX_I2MPB_TEST_MODE_B2
,
460 MTK_PHY_DA_TX_I2MPB_B_HBT_MASK
, (buf
[1] + bias
[6]) << 8);
461 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TX_I2MPB_TEST_MODE_B2
,
462 MTK_PHY_DA_TX_I2MPB_B_TST_MASK
, buf
[1] + bias
[7]);
464 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TX_I2MPB_TEST_MODE_C1
,
465 MTK_PHY_DA_TX_I2MPB_C_GBE_MASK
, (buf
[2] + bias
[8]) << 8);
466 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TX_I2MPB_TEST_MODE_C1
,
467 MTK_PHY_DA_TX_I2MPB_C_TBT_MASK
, buf
[2] + bias
[9]);
468 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TX_I2MPB_TEST_MODE_C2
,
469 MTK_PHY_DA_TX_I2MPB_C_HBT_MASK
, (buf
[2] + bias
[10]) << 8);
470 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TX_I2MPB_TEST_MODE_C2
,
471 MTK_PHY_DA_TX_I2MPB_C_TST_MASK
, buf
[2] + bias
[11]);
473 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TX_I2MPB_TEST_MODE_D1
,
474 MTK_PHY_DA_TX_I2MPB_D_GBE_MASK
, (buf
[3] + bias
[12]) << 8);
475 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TX_I2MPB_TEST_MODE_D1
,
476 MTK_PHY_DA_TX_I2MPB_D_TBT_MASK
, buf
[3] + bias
[13]);
477 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TX_I2MPB_TEST_MODE_D2
,
478 MTK_PHY_DA_TX_I2MPB_D_HBT_MASK
, (buf
[3] + bias
[14]) << 8);
479 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_TX_I2MPB_TEST_MODE_D2
,
480 MTK_PHY_DA_TX_I2MPB_D_TST_MASK
, buf
[3] + bias
[15]);
485 static int tx_amp_cal_efuse(struct phy_device
*phydev
, u32
*buf
)
487 u16 tx_amp_cal_val
[4];
489 tx_amp_cal_val
[0] = EFS_DA_TX_I2MPB_A(buf
[0]);
490 tx_amp_cal_val
[1] = EFS_DA_TX_I2MPB_B(buf
[0]);
491 tx_amp_cal_val
[2] = EFS_DA_TX_I2MPB_C(buf
[0]);
492 tx_amp_cal_val
[3] = EFS_DA_TX_I2MPB_D(buf
[0]);
493 tx_amp_fill_result(phydev
, tx_amp_cal_val
);
498 static int tx_r50_fill_result(struct phy_device
*phydev
, u16 tx_r50_cal_val
,
504 if (phydev
->drv
->phy_id
== MTK_GPHY_ID_MT7988
)
507 val
= clamp_val(bias
+ tx_r50_cal_val
, 0, 63);
509 switch (txg_calen_x
) {
511 reg
= MTK_PHY_DA_TX_R50_PAIR_A
;
514 reg
= MTK_PHY_DA_TX_R50_PAIR_B
;
517 reg
= MTK_PHY_DA_TX_R50_PAIR_C
;
520 reg
= MTK_PHY_DA_TX_R50_PAIR_D
;
526 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, reg
, val
| val
<< 8);
531 static int tx_r50_cal_efuse(struct phy_device
*phydev
, u32
*buf
,
536 switch (txg_calen_x
) {
538 tx_r50_cal_val
= EFS_DA_TX_R50_A(buf
[1]);
541 tx_r50_cal_val
= EFS_DA_TX_R50_B(buf
[1]);
544 tx_r50_cal_val
= EFS_DA_TX_R50_C(buf
[2]);
547 tx_r50_cal_val
= EFS_DA_TX_R50_D(buf
[2]);
552 tx_r50_fill_result(phydev
, tx_r50_cal_val
, txg_calen_x
);
557 static int tx_vcm_cal_sw(struct phy_device
*phydev
, u8 rg_txreserve_x
)
559 u8 lower_idx
, upper_idx
, txreserve_val
;
560 u8 lower_ret
, upper_ret
;
563 phy_set_bits_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_ANA_CAL_RG0
,
564 MTK_PHY_RG_ANA_CALEN
);
565 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_ANA_CAL_RG0
,
566 MTK_PHY_RG_CAL_CKINV
);
567 phy_set_bits_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_ANA_CAL_RG1
,
568 MTK_PHY_RG_TXVOS_CALEN
);
570 switch (rg_txreserve_x
) {
572 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
,
573 MTK_PHY_RG_DASN_DAC_IN0_A
,
574 MTK_PHY_DASN_DAC_IN0_A_MASK
);
575 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
,
576 MTK_PHY_RG_DASN_DAC_IN1_A
,
577 MTK_PHY_DASN_DAC_IN1_A_MASK
);
578 phy_set_bits_mmd(phydev
, MDIO_MMD_VEND1
,
579 MTK_PHY_RG_ANA_CAL_RG0
,
580 MTK_PHY_RG_ZCALEN_A
);
583 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
,
584 MTK_PHY_RG_DASN_DAC_IN0_B
,
585 MTK_PHY_DASN_DAC_IN0_B_MASK
);
586 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
,
587 MTK_PHY_RG_DASN_DAC_IN1_B
,
588 MTK_PHY_DASN_DAC_IN1_B_MASK
);
589 phy_set_bits_mmd(phydev
, MDIO_MMD_VEND1
,
590 MTK_PHY_RG_ANA_CAL_RG1
,
591 MTK_PHY_RG_ZCALEN_B
);
594 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
,
595 MTK_PHY_RG_DASN_DAC_IN0_C
,
596 MTK_PHY_DASN_DAC_IN0_C_MASK
);
597 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
,
598 MTK_PHY_RG_DASN_DAC_IN1_C
,
599 MTK_PHY_DASN_DAC_IN1_C_MASK
);
600 phy_set_bits_mmd(phydev
, MDIO_MMD_VEND1
,
601 MTK_PHY_RG_ANA_CAL_RG1
,
602 MTK_PHY_RG_ZCALEN_C
);
605 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
,
606 MTK_PHY_RG_DASN_DAC_IN0_D
,
607 MTK_PHY_DASN_DAC_IN0_D_MASK
);
608 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
,
609 MTK_PHY_RG_DASN_DAC_IN1_D
,
610 MTK_PHY_DASN_DAC_IN1_D_MASK
);
611 phy_set_bits_mmd(phydev
, MDIO_MMD_VEND1
,
612 MTK_PHY_RG_ANA_CAL_RG1
,
613 MTK_PHY_RG_ZCALEN_D
);
620 lower_idx
= TXRESERVE_MIN
;
621 upper_idx
= TXRESERVE_MAX
;
623 phydev_dbg(phydev
, "Start TX-VCM SW cal.\n");
624 while ((upper_idx
- lower_idx
) > 1) {
625 txreserve_val
= DIV_ROUND_CLOSEST(lower_idx
+ upper_idx
, 2);
626 ret
= cal_cycle(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RXADC_CTRL_RG9
,
627 MTK_PHY_DA_RX_PSBN_TBT_MASK
|
628 MTK_PHY_DA_RX_PSBN_HBT_MASK
|
629 MTK_PHY_DA_RX_PSBN_GBE_MASK
|
630 MTK_PHY_DA_RX_PSBN_LP_MASK
,
631 txreserve_val
<< 12 | txreserve_val
<< 8 |
632 txreserve_val
<< 4 | txreserve_val
);
634 upper_idx
= txreserve_val
;
636 } else if (ret
== 0) {
637 lower_idx
= txreserve_val
;
644 if (lower_idx
== TXRESERVE_MIN
) {
645 lower_ret
= cal_cycle(phydev
, MDIO_MMD_VEND1
,
646 MTK_PHY_RXADC_CTRL_RG9
,
647 MTK_PHY_DA_RX_PSBN_TBT_MASK
|
648 MTK_PHY_DA_RX_PSBN_HBT_MASK
|
649 MTK_PHY_DA_RX_PSBN_GBE_MASK
|
650 MTK_PHY_DA_RX_PSBN_LP_MASK
,
651 lower_idx
<< 12 | lower_idx
<< 8 |
652 lower_idx
<< 4 | lower_idx
);
654 } else if (upper_idx
== TXRESERVE_MAX
) {
655 upper_ret
= cal_cycle(phydev
, MDIO_MMD_VEND1
,
656 MTK_PHY_RXADC_CTRL_RG9
,
657 MTK_PHY_DA_RX_PSBN_TBT_MASK
|
658 MTK_PHY_DA_RX_PSBN_HBT_MASK
|
659 MTK_PHY_DA_RX_PSBN_GBE_MASK
|
660 MTK_PHY_DA_RX_PSBN_LP_MASK
,
661 upper_idx
<< 12 | upper_idx
<< 8 |
662 upper_idx
<< 4 | upper_idx
);
668 /* We calibrate TX-VCM in different logic. Check upper index and then
669 * lower index. If this calibration is valid, apply lower index's result.
671 ret
= upper_ret
- lower_ret
;
674 /* Make sure we use upper_idx in our calibration system */
675 cal_cycle(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RXADC_CTRL_RG9
,
676 MTK_PHY_DA_RX_PSBN_TBT_MASK
|
677 MTK_PHY_DA_RX_PSBN_HBT_MASK
|
678 MTK_PHY_DA_RX_PSBN_GBE_MASK
|
679 MTK_PHY_DA_RX_PSBN_LP_MASK
,
680 upper_idx
<< 12 | upper_idx
<< 8 |
681 upper_idx
<< 4 | upper_idx
);
682 phydev_dbg(phydev
, "TX-VCM SW cal result: 0x%x\n", upper_idx
);
683 } else if (lower_idx
== TXRESERVE_MIN
&& upper_ret
== 1 &&
686 cal_cycle(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RXADC_CTRL_RG9
,
687 MTK_PHY_DA_RX_PSBN_TBT_MASK
|
688 MTK_PHY_DA_RX_PSBN_HBT_MASK
|
689 MTK_PHY_DA_RX_PSBN_GBE_MASK
|
690 MTK_PHY_DA_RX_PSBN_LP_MASK
,
691 lower_idx
<< 12 | lower_idx
<< 8 |
692 lower_idx
<< 4 | lower_idx
);
693 phydev_warn(phydev
, "TX-VCM SW cal result at low margin 0x%x\n",
695 } else if (upper_idx
== TXRESERVE_MAX
&& upper_ret
== 0 &&
698 phydev_warn(phydev
, "TX-VCM SW cal result at high margin 0x%x\n",
705 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_ANA_CAL_RG0
,
706 MTK_PHY_RG_ANA_CALEN
);
707 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_ANA_CAL_RG1
,
708 MTK_PHY_RG_TXVOS_CALEN
);
709 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_ANA_CAL_RG0
,
710 MTK_PHY_RG_ZCALEN_A
);
711 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_ANA_CAL_RG1
,
712 MTK_PHY_RG_ZCALEN_B
| MTK_PHY_RG_ZCALEN_C
|
713 MTK_PHY_RG_ZCALEN_D
);
718 static void mt798x_phy_common_finetune(struct phy_device
*phydev
)
720 phy_select_page(phydev
, MTK_PHY_PAGE_EXTENDED_52B5
);
721 /* EnabRandUpdTrig = 1 */
722 __phy_write(phydev
, 0x11, 0x2f00);
723 __phy_write(phydev
, 0x12, 0xe);
724 __phy_write(phydev
, 0x10, 0x8fb0);
726 /* NormMseLoThresh = 85 */
727 __phy_write(phydev
, 0x11, 0x55a0);
728 __phy_write(phydev
, 0x12, 0x0);
729 __phy_write(phydev
, 0x10, 0x83aa);
732 __phy_write(phydev
, 0x11, 0x0);
733 __phy_write(phydev
, 0x12, 0x0);
734 __phy_write(phydev
, 0x10, 0x9686);
736 /* SSTrKp1000Slv = 5 */
737 __phy_write(phydev
, 0x11, 0xbaef);
738 __phy_write(phydev
, 0x12, 0x2e);
739 __phy_write(phydev
, 0x10, 0x968c);
741 /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
742 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
744 __phy_write(phydev
, 0x11, 0xd10a);
745 __phy_write(phydev
, 0x12, 0x34);
746 __phy_write(phydev
, 0x10, 0x8f82);
748 /* VcoSlicerThreshBitsHigh */
749 __phy_write(phydev
, 0x11, 0x5555);
750 __phy_write(phydev
, 0x12, 0x55);
751 __phy_write(phydev
, 0x10, 0x8ec0);
752 phy_restore_page(phydev
, MTK_PHY_PAGE_STANDARD
, 0);
754 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
755 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_DEV1E_REG234
,
756 MTK_PHY_TR_OPEN_LOOP_EN_MASK
| MTK_PHY_LPF_X_AVERAGE_MASK
,
757 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK
, 0x9));
759 /* rg_tr_lpf_cnt_val = 512 */
760 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_LPF_CNT_VAL
, 0x200);
763 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_LP_IIR2_K1_L
, 0x82);
764 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_LP_IIR2_K1_U
, 0x0);
765 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_LP_IIR2_K2_L
, 0x103);
766 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_LP_IIR2_K2_U
, 0x0);
767 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_LP_IIR2_K3_L
, 0x82);
768 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_LP_IIR2_K3_U
, 0x0);
769 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_LP_IIR2_K4_L
, 0xd177);
770 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_LP_IIR2_K4_U
, 0x3);
771 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_LP_IIR2_K5_L
, 0x2c82);
772 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_LP_IIR2_K5_U
, 0xe);
775 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_DEV1E_REG27C
,
776 MTK_PHY_VGASTATE_FFE_THR_ST1_MASK
, 0x1b << 8);
777 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_DEV1E_REG27D
,
778 MTK_PHY_VGASTATE_FFE_THR_ST2_MASK
, 0x1e);
780 /* Disable LDO pump */
781 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_LDO_PUMP_EN_PAIRAB
, 0x0);
782 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_LDO_PUMP_EN_PAIRCD
, 0x0);
783 /* Adjust LDO output voltage */
784 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_LDO_OUTPUT_V
, 0x2222);
787 static void mt7981_phy_finetune(struct phy_device
*phydev
)
789 u16 val
[8] = { 0x01ce, 0x01c1,
795 /* 100M eye finetune:
796 * Keep middle level of TX MLT3 shapper as default.
797 * Only change TX MLT3 overshoot level here.
799 for (k
= 0, i
= 1; i
< 12; i
++) {
802 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, i
, val
[k
++]);
805 phy_select_page(phydev
, MTK_PHY_PAGE_EXTENDED_52B5
);
806 /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
807 __phy_write(phydev
, 0x11, 0xc71);
808 __phy_write(phydev
, 0x12, 0xc);
809 __phy_write(phydev
, 0x10, 0x8fae);
811 /* ResetSyncOffset = 6 */
812 __phy_write(phydev
, 0x11, 0x600);
813 __phy_write(phydev
, 0x12, 0x0);
814 __phy_write(phydev
, 0x10, 0x8fc0);
817 __phy_write(phydev
, 0x11, 0x4c2a);
818 __phy_write(phydev
, 0x12, 0x3e);
819 __phy_write(phydev
, 0x10, 0x8fa4);
821 /* FfeUpdGainForce = 4 */
822 __phy_write(phydev
, 0x11, 0x240);
823 __phy_write(phydev
, 0x12, 0x0);
824 __phy_write(phydev
, 0x10, 0x9680);
826 phy_restore_page(phydev
, MTK_PHY_PAGE_STANDARD
, 0);
829 static void mt7988_phy_finetune(struct phy_device
*phydev
)
831 u16 val
[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
832 0x020d, 0x0206, 0x0384, 0x03d0,
833 0x03c6, 0x030a, 0x0011, 0x0005 };
836 /* Set default MLT3 shaper first */
837 for (i
= 0; i
< 12; i
++)
838 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, i
, val
[i
]);
841 phy_write_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_TX_FILTER
, 0x5);
843 /* Disable TX power saving */
844 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RXADC_CTRL_RG7
,
845 MTK_PHY_DA_AD_BUF_BIAS_LP_MASK
, 0x3 << 8);
847 phy_select_page(phydev
, MTK_PHY_PAGE_EXTENDED_52B5
);
849 /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
850 __phy_write(phydev
, 0x11, 0x671);
851 __phy_write(phydev
, 0x12, 0xc);
852 __phy_write(phydev
, 0x10, 0x8fae);
854 /* ResetSyncOffset = 5 */
855 __phy_write(phydev
, 0x11, 0x500);
856 __phy_write(phydev
, 0x12, 0x0);
857 __phy_write(phydev
, 0x10, 0x8fc0);
859 /* VgaDecRate is 1 at default on mt7988 */
861 phy_restore_page(phydev
, MTK_PHY_PAGE_STANDARD
, 0);
863 phy_select_page(phydev
, MTK_PHY_PAGE_EXTENDED_2A30
);
864 /* TxClkOffset = 2 */
865 __phy_modify(phydev
, MTK_PHY_ANARG_RG
, MTK_PHY_TCLKOFFSET_MASK
,
866 FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK
, 0x2));
867 phy_restore_page(phydev
, MTK_PHY_PAGE_STANDARD
, 0);
870 static void mt798x_phy_eee(struct phy_device
*phydev
)
872 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
,
873 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120
,
874 MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK
|
875 MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK
,
876 FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK
, 0x0) |
877 FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK
, 0x14));
879 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
,
880 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122
,
881 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK
,
882 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK
,
885 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
,
886 MTK_PHY_RG_TESTMUX_ADC_CTRL
,
887 MTK_PHY_RG_TXEN_DIG_MASK
);
889 phy_set_bits_mmd(phydev
, MDIO_MMD_VEND1
,
890 MTK_PHY_RG_DEV1E_REG19b
, MTK_PHY_BYPASS_DSP_LPI_READY
);
892 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND1
,
893 MTK_PHY_RG_DEV1E_REG234
, MTK_PHY_TR_LP_IIR_EEE_EN
);
895 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_DEV1E_REG238
,
896 MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK
|
897 MTK_PHY_LPI_SLV_SEND_TX_EN
,
898 FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK
, 0x120));
900 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_DEV1E_REG239
,
901 MTK_PHY_LPI_SEND_LOC_TIMER_MASK
|
902 MTK_PHY_LPI_TXPCS_LOC_RCV
,
903 FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK
, 0x117));
905 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_DEV1E_REG2C7
,
906 MTK_PHY_MAX_GAIN_MASK
| MTK_PHY_MIN_GAIN_MASK
,
907 FIELD_PREP(MTK_PHY_MAX_GAIN_MASK
, 0x8) |
908 FIELD_PREP(MTK_PHY_MIN_GAIN_MASK
, 0x13));
910 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_DEV1E_REG2D1
,
911 MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK
,
912 FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK
,
914 MTK_PHY_LPI_SKIP_SD_SLV_TR
| MTK_PHY_LPI_TR_READY
|
915 MTK_PHY_LPI_VCO_EEE_STG0_EN
);
917 phy_set_bits_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_DEV1E_REG323
,
918 MTK_PHY_EEE_WAKE_MAS_INT_DC
|
919 MTK_PHY_EEE_WAKE_SLV_INT_DC
);
921 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_DEV1E_REG324
,
922 MTK_PHY_SMI_DETCNT_MAX_MASK
,
923 FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK
, 0x3f) |
924 MTK_PHY_SMI_DET_MAX_EN
);
926 phy_set_bits_mmd(phydev
, MDIO_MMD_VEND1
, MTK_PHY_RG_DEV1E_REG326
,
927 MTK_PHY_LPI_MODE_SD_ON
| MTK_PHY_RESET_RANDUPD_CNT
|
928 MTK_PHY_TREC_UPDATE_ENAB_CLR
|
929 MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF
|
930 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP
);
932 phy_select_page(phydev
, MTK_PHY_PAGE_EXTENDED_52B5
);
933 /* Regsigdet_sel_1000 = 0 */
934 __phy_write(phydev
, 0x11, 0xb);
935 __phy_write(phydev
, 0x12, 0x0);
936 __phy_write(phydev
, 0x10, 0x9690);
938 /* REG_EEE_st2TrKf1000 = 3 */
939 __phy_write(phydev
, 0x11, 0x114f);
940 __phy_write(phydev
, 0x12, 0x2);
941 __phy_write(phydev
, 0x10, 0x969a);
943 /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */
944 __phy_write(phydev
, 0x11, 0x3028);
945 __phy_write(phydev
, 0x12, 0x0);
946 __phy_write(phydev
, 0x10, 0x969e);
948 /* RegEEE_slv_wake_int_timer_tar = 8 */
949 __phy_write(phydev
, 0x11, 0x5010);
950 __phy_write(phydev
, 0x12, 0x0);
951 __phy_write(phydev
, 0x10, 0x96a0);
953 /* RegEEE_trfreeze_timer2 = 586 */
954 __phy_write(phydev
, 0x11, 0x24a);
955 __phy_write(phydev
, 0x12, 0x0);
956 __phy_write(phydev
, 0x10, 0x96a8);
958 /* RegEEE100Stg1_tar = 16 */
959 __phy_write(phydev
, 0x11, 0x3210);
960 __phy_write(phydev
, 0x12, 0x0);
961 __phy_write(phydev
, 0x10, 0x96b8);
963 /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
964 __phy_write(phydev
, 0x11, 0x1463);
965 __phy_write(phydev
, 0x12, 0x0);
966 __phy_write(phydev
, 0x10, 0x96ca);
968 /* DfeTailEnableVgaThresh1000 = 27 */
969 __phy_write(phydev
, 0x11, 0x36);
970 __phy_write(phydev
, 0x12, 0x0);
971 __phy_write(phydev
, 0x10, 0x8f80);
972 phy_restore_page(phydev
, MTK_PHY_PAGE_STANDARD
, 0);
974 phy_select_page(phydev
, MTK_PHY_PAGE_EXTENDED_3
);
975 __phy_modify(phydev
, MTK_PHY_LPI_REG_14
, MTK_PHY_LPI_WAKE_TIMER_1000_MASK
,
976 FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK
, 0x19c));
978 __phy_modify(phydev
, MTK_PHY_LPI_REG_1c
, MTK_PHY_SMI_DET_ON_THRESH_MASK
,
979 FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK
, 0xc));
980 phy_restore_page(phydev
, MTK_PHY_PAGE_STANDARD
, 0);
982 phy_modify_mmd(phydev
, MDIO_MMD_VEND1
,
983 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122
,
984 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK
,
985 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK
, 0xff));
988 static int cal_sw(struct phy_device
*phydev
, enum CAL_ITEM cal_item
,
989 u8 start_pair
, u8 end_pair
)
994 for (pair_n
= start_pair
; pair_n
<= end_pair
; pair_n
++) {
995 /* TX_OFFSET & TX_AMP have no SW calibration. */
998 ret
= tx_vcm_cal_sw(phydev
, pair_n
);
1009 static int cal_efuse(struct phy_device
*phydev
, enum CAL_ITEM cal_item
,
1010 u8 start_pair
, u8 end_pair
, u32
*buf
)
1015 for (pair_n
= start_pair
; pair_n
<= end_pair
; pair_n
++) {
1016 /* TX_VCM has no efuse calibration. */
1019 ret
= rext_cal_efuse(phydev
, buf
);
1022 ret
= tx_offset_cal_efuse(phydev
, buf
);
1025 ret
= tx_amp_cal_efuse(phydev
, buf
);
1028 ret
= tx_r50_cal_efuse(phydev
, buf
, pair_n
);
1040 static int start_cal(struct phy_device
*phydev
, enum CAL_ITEM cal_item
,
1041 enum CAL_MODE cal_mode
, u8 start_pair
,
1042 u8 end_pair
, u32
*buf
)
1048 ret
= cal_efuse(phydev
, cal_item
, start_pair
,
1052 ret
= cal_sw(phydev
, cal_item
, start_pair
, end_pair
);
1059 phydev_err(phydev
, "cal %d failed\n", cal_item
);
1066 static int mt798x_phy_calibration(struct phy_device
*phydev
)
1071 struct nvmem_cell
*cell
;
1073 cell
= nvmem_cell_get(&phydev
->mdio
.dev
, "phy-cal-data");
1075 if (PTR_ERR(cell
) == -EPROBE_DEFER
)
1076 return PTR_ERR(cell
);
1080 buf
= (u32
*)nvmem_cell_read(cell
, &len
);
1082 return PTR_ERR(buf
);
1083 nvmem_cell_put(cell
);
1085 if (!buf
[0] || !buf
[1] || !buf
[2] || !buf
[3] || len
< 4 * sizeof(u32
)) {
1086 phydev_err(phydev
, "invalid efuse data\n");
1091 ret
= start_cal(phydev
, REXT
, EFUSE_M
, NO_PAIR
, NO_PAIR
, buf
);
1094 ret
= start_cal(phydev
, TX_OFFSET
, EFUSE_M
, NO_PAIR
, NO_PAIR
, buf
);
1097 ret
= start_cal(phydev
, TX_AMP
, EFUSE_M
, NO_PAIR
, NO_PAIR
, buf
);
1100 ret
= start_cal(phydev
, TX_R50
, EFUSE_M
, PAIR_A
, PAIR_D
, buf
);
1103 ret
= start_cal(phydev
, TX_VCM
, SW_M
, PAIR_A
, PAIR_A
, buf
);
1112 static int mt798x_phy_config_init(struct phy_device
*phydev
)
1114 switch (phydev
->drv
->phy_id
) {
1115 case MTK_GPHY_ID_MT7981
:
1116 mt7981_phy_finetune(phydev
);
1118 case MTK_GPHY_ID_MT7988
:
1119 mt7988_phy_finetune(phydev
);
1123 mt798x_phy_common_finetune(phydev
);
1124 mt798x_phy_eee(phydev
);
1126 return mt798x_phy_calibration(phydev
);
1129 static int mt7988_phy_setup_led(struct phy_device
*phydev
)
1131 struct mtk_socphy_shared_priv
*priv
= phydev
->shared
->priv
;
1132 int port
= phydev
->mdio
.addr
;
1133 u32 reg
= priv
->boottrap
;
1134 struct pinctrl
*pinctrl
;
1136 phy_write_mmd(phydev
, MDIO_MMD_VEND2
, MTK_PHY_LED0_ON_CTRL
,
1137 MTK_PHY_LED0_ENABLE
| MTK_PHY_LED0_POLARITY
|
1138 MTK_PHY_LED0_ON_LINK10
|
1139 MTK_PHY_LED0_ON_LINK100
|
1140 MTK_PHY_LED0_ON_LINK1000
);
1141 phy_write_mmd(phydev
, MDIO_MMD_VEND2
, MTK_PHY_LED1_ON_CTRL
,
1142 MTK_PHY_LED1_ENABLE
| MTK_PHY_LED1_POLARITY
|
1143 MTK_PHY_LED1_ON_LINK10
|
1144 MTK_PHY_LED1_ON_LINK100
|
1145 MTK_PHY_LED1_ON_LINK1000
);
1147 if ((port
== GPHY_PORT0
&& reg
& BIT(8)) ||
1148 (port
== GPHY_PORT1
&& reg
& BIT(9)) ||
1149 (port
== GPHY_PORT2
&& reg
& BIT(10)) ||
1150 (port
== GPHY_PORT3
&& reg
& BIT(11))) {
1151 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND2
, MTK_PHY_LED0_ON_CTRL
,
1152 MTK_PHY_LED0_POLARITY
);
1153 phy_clear_bits_mmd(phydev
, MDIO_MMD_VEND2
, MTK_PHY_LED1_ON_CTRL
,
1154 MTK_PHY_LED1_POLARITY
);
1157 phy_write_mmd(phydev
, MDIO_MMD_VEND2
, MTK_PHY_LED0_BLINK_CTRL
,
1158 MTK_PHY_LED0_1000TX
| MTK_PHY_LED0_1000RX
|
1159 MTK_PHY_LED0_100TX
| MTK_PHY_LED0_100RX
|
1160 MTK_PHY_LED0_10TX
| MTK_PHY_LED0_10RX
);
1161 phy_write_mmd(phydev
, MDIO_MMD_VEND2
, MTK_PHY_LED1_BLINK_CTRL
,
1162 MTK_PHY_LED1_1000TX
| MTK_PHY_LED1_1000RX
|
1163 MTK_PHY_LED1_100TX
| MTK_PHY_LED1_100RX
|
1164 MTK_PHY_LED1_10TX
| MTK_PHY_LED1_10RX
);
1166 pinctrl
= devm_pinctrl_get_select(&phydev
->mdio
.dev
, "gbe-led");
1167 if (IS_ERR(pinctrl
)) {
1168 dev_err(&phydev
->mdio
.bus
->dev
, "Failed to setup LED pins\n");
1169 return PTR_ERR(pinctrl
);
1175 static int mt7988_phy_probe_shared(struct phy_device
*phydev
)
1177 struct mtk_socphy_shared_priv
*priv
= phydev
->shared
->priv
;
1178 void __iomem
*boottrap
;
1179 struct device_node
*np
;
1182 np
= of_find_compatible_node(NULL
, NULL
, "mediatek,boottrap");
1186 boottrap
= of_iomap(np
, 0);
1190 reg
= readl(boottrap
);
1193 priv
->boottrap
= reg
;
1198 static int mt7981_phy_probe(struct phy_device
*phydev
)
1200 return mt798x_phy_calibration(phydev
);
1203 static int mt7988_phy_probe(struct phy_device
*phydev
)
1207 err
= devm_phy_package_join(&phydev
->mdio
.dev
, phydev
, 0,
1208 sizeof(struct mtk_socphy_shared_priv
));
1212 if (phy_package_probe_once(phydev
)) {
1213 err
= mt7988_phy_probe_shared(phydev
);
1218 mt7988_phy_setup_led(phydev
);
1220 return mt798x_phy_calibration(phydev
);
1223 static struct phy_driver mtk_socphy_driver
[] = {
1225 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981
),
1226 .name
= "MediaTek MT7981 PHY",
1227 .config_init
= mt798x_phy_config_init
,
1228 .config_intr
= genphy_no_config_intr
,
1229 .handle_interrupt
= genphy_handle_interrupt_no_ack
,
1230 .probe
= mt7981_phy_probe
,
1231 .suspend
= genphy_suspend
,
1232 .resume
= genphy_resume
,
1233 .read_page
= mtk_socphy_read_page
,
1234 .write_page
= mtk_socphy_write_page
,
1237 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988
),
1238 .name
= "MediaTek MT7988 PHY",
1239 .config_init
= mt798x_phy_config_init
,
1240 .config_intr
= genphy_no_config_intr
,
1241 .handle_interrupt
= genphy_handle_interrupt_no_ack
,
1242 .probe
= mt7988_phy_probe
,
1243 .suspend
= genphy_suspend
,
1244 .resume
= genphy_resume
,
1245 .read_page
= mtk_socphy_read_page
,
1246 .write_page
= mtk_socphy_write_page
,
1250 module_phy_driver(mtk_socphy_driver
);
1252 static struct mdio_device_id __maybe_unused mtk_socphy_tbl
[] = {
1253 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981
) },
1254 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988
) },
1258 MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver");
1259 MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
1260 MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
1261 MODULE_LICENSE("GPL");
1263 MODULE_DEVICE_TABLE(mdio
, mtk_socphy_tbl
);