target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2021 MediaTek Inc.
   4  * Author: Sam.Shih <sam.shih@mediatek.com>
   5  */
   6
   7 #include <dt-bindings/clock/mt7986-clk.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/phy/phy.h>
  11 #include <dt-bindings/reset/mt7986-resets.h>
  12
  13 / {
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         clk40m: oscillator@0 {
  19                 compatible = "fixed-clock";
  20                 clock-frequency = <40000000>;
  21                 #clock-cells = <0>;
  22                 clock-output-names = "clkxtal";
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28                 cpu0: cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a53";
  31                         enable-method = "psci";
  32                         reg = <0x0>;
  33                         #cooling-cells = <2>;
  34                 };
  35
  36                 cpu1: cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a53";
  39                         enable-method = "psci";
  40                         reg = <0x1>;
  41                         #cooling-cells = <2>;
  42                 };
  43
  44                 cpu2: cpu@2 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a53";
  47                         enable-method = "psci";
  48                         reg = <0x2>;
  49                         #cooling-cells = <2>;
  50                 };
  51
  52                 cpu3: cpu@3 {
  53                         device_type = "cpu";
  54                         enable-method = "psci";
  55                         compatible = "arm,cortex-a53";
  56                         reg = <0x3>;
  57                         #cooling-cells = <2>;
  58                 };
  59         };
  60
  61         psci {
  62                 compatible  = "arm,psci-0.2";
  63                 method      = "smc";
  64         };
  65
  66         reserved-memory {
  67                 #address-cells = <2>;
  68                 #size-cells = <2>;
  69                 ranges;
  70
  71                 /* 64 KiB reserved for ramoops/pstore */
  72                 ramoops@42ff0000 {
  73                         compatible = "ramoops";
  74                         reg = <0 0x42ff0000 0 0x10000>;
  75                         record-size = <0x1000>;
  76                 };
  77
  78                 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
  79                 secmon_reserved: secmon@43000000 {
  80                         reg = <0 0x43000000 0 0x30000>;
  81                         no-map;
  82                 };
  83
  84                 wmcpu_emi: wmcpu-reserved@4fc00000 {
  85                         no-map;
  86                         reg = <0 0x4fc00000 0 0x00100000>;
  87                 };
  88         };
  89
  90         timer {
  91                 compatible = "arm,armv8-timer";
  92                 interrupt-parent = <&gic>;
  93                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
  94                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
  95                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
  96                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
  97         };
  98
  99         soc {
 100                 #address-cells = <2>;
 101                 #size-cells = <2>;
 102                 compatible = "simple-bus";
 103                 ranges;
 104
 105                 gic: interrupt-controller@c000000 {
 106                         compatible = "arm,gic-v3";
 107                         #interrupt-cells = <3>;
 108                         interrupt-parent = <&gic>;
 109                         interrupt-controller;
 110                         reg = <0 0x0c000000 0 0x10000>,  /* GICD */
 111                               <0 0x0c080000 0 0x80000>,  /* GICR */
 112                               <0 0x0c400000 0 0x2000>,   /* GICC */
 113                               <0 0x0c410000 0 0x1000>,   /* GICH */
 114                               <0 0x0c420000 0 0x2000>;   /* GICV */
 115                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 116                 };
 117
 118                 infracfg: infracfg@10001000 {
 119                         compatible = "mediatek,mt7986-infracfg", "syscon";
 120                         reg = <0 0x10001000 0 0x1000>;
 121                         #clock-cells = <1>;
 122                 };
 123
 124                 topckgen: topckgen@1001b000 {
 125                         compatible = "mediatek,mt7986-topckgen", "syscon";
 126                         reg = <0 0x1001B000 0 0x1000>;
 127                         #clock-cells = <1>;
 128                 };
 129
 130                 watchdog: watchdog@1001c000 {
 131                         compatible = "mediatek,mt7986-wdt",
 132                                      "mediatek,mt6589-wdt";
 133                         reg = <0 0x1001c000 0 0x1000>;
 134                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 135                         #reset-cells = <1>;
 136                 };
 137
 138                 pio: pinctrl@1001f000 {
 139                         compatible = "mediatek,mt7986a-pinctrl";
 140                         reg = <0 0x1001f000 0 0x1000>,
 141                               <0 0x11c30000 0 0x1000>,
 142                               <0 0x11c40000 0 0x1000>,
 143                               <0 0x11e20000 0 0x1000>,
 144                               <0 0x11e30000 0 0x1000>,
 145                               <0 0x11f00000 0 0x1000>,
 146                               <0 0x11f10000 0 0x1000>,
 147                               <0 0x1000b000 0 0x1000>;
 148                         reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
 149                                     "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
 150                         gpio-controller;
 151                         #gpio-cells = <2>;
 152                         gpio-ranges = <&pio 0 0 100>;
 153                         interrupt-controller;
 154                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 155                         interrupt-parent = <&gic>;
 156                         #interrupt-cells = <2>;
 157                 };
 158
 159                 apmixedsys: apmixedsys@1001e000 {
 160                         compatible = "mediatek,mt7986-apmixedsys";
 161                         reg = <0 0x1001E000 0 0x1000>;
 162                         #clock-cells = <1>;
 163                 };
 164
 165                 sgmiisys0: syscon@10060000 {
 166                         compatible = "mediatek,mt7986-sgmiisys_0",
 167                                      "syscon";
 168                         reg = <0 0x10060000 0 0x1000>;
 169                         #clock-cells = <1>;
 170                 };
 171
 172                 sgmiisys1: syscon@10070000 {
 173                         compatible = "mediatek,mt7986-sgmiisys_1",
 174                                      "syscon";
 175                         reg = <0 0x10070000 0 0x1000>;
 176                         #clock-cells = <1>;
 177                 };
 178
 179                 trng: trng@1020f000 {
 180                         compatible = "mediatek,mt7986-rng";
 181                         reg = <0 0x1020f000 0 0x100>;
 182                         clocks = <&infracfg CLK_INFRA_TRNG_CK>;
 183                         clock-names = "rng";
 184                         status = "okay";
 185                 };
 186
 187                 crypto: crypto@10320000 {
 188                         compatible = "inside-secure,safexcel-eip97";
 189                         reg = <0 0x10320000 0 0x40000>;
 190                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 191                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 192                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 193                                      <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 194                         interrupt-names = "ring0", "ring1", "ring2", "ring3";
 195                         clocks = <&infracfg CLK_INFRA_EIP97_CK>;
 196                         clock-names = "infra_eip97_ck";
 197                         assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
 198                         assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
 199                         status = "okay";
 200                 };
 201
 202                 uart0: serial@11002000 {
 203                         compatible = "mediatek,mt7986-uart",
 204                                      "mediatek,mt6577-uart";
 205                         reg = <0 0x11002000 0 0x400>;
 206                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 207                         clocks = <&infracfg CLK_INFRA_UART0_SEL>,
 208                                  <&infracfg CLK_INFRA_UART0_CK>;
 209                         clock-names = "baud", "bus";
 210                         assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 211                                           <&infracfg CLK_INFRA_UART0_SEL>;
 212                         assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
 213                                                  <&topckgen CLK_TOP_UART_SEL>;
 214                         status = "disabled";
 215                 };
 216
 217                 uart1: serial@11003000 {
 218                         compatible = "mediatek,mt7986-uart",
 219                                      "mediatek,mt6577-uart";
 220                         reg = <0 0x11003000 0 0x400>;
 221                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 222                         clocks = <&infracfg CLK_INFRA_UART1_SEL>,
 223                                  <&infracfg CLK_INFRA_UART1_CK>;
 224                         clock-names = "baud", "bus";
 225                         assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
 226                         assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
 227                         status = "disabled";
 228                 };
 229
 230                 uart2: serial@11004000 {
 231                         compatible = "mediatek,mt7986-uart",
 232                                      "mediatek,mt6577-uart";
 233                         reg = <0 0x11004000 0 0x400>;
 234                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 235                         clocks = <&infracfg CLK_INFRA_UART2_SEL>,
 236                                  <&infracfg CLK_INFRA_UART2_CK>;
 237                         clock-names = "baud", "bus";
 238                         assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
 239                         assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
 240                         status = "disabled";
 241                 };
 242
 243                 spi0: spi@1100a000 {
 244                         compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 245                         reg = <0 0x1100a000 0 0x100>;
 246                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 247                         clocks = <&topckgen CLK_TOP_MPLL_D2>,
 248                                  <&topckgen CLK_TOP_SPI_SEL>,
 249                                  <&infracfg CLK_INFRA_SPI0_CK>,
 250                                  <&infracfg CLK_INFRA_SPI0_HCK_CK>;
 251                         clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 252                         status = "disabled";
 253                 };
 254
 255                 spi1: spi@1100b000 {
 256                         compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
 257                         reg = <0 0x1100b000 0 0x100>;
 258                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 259                         clocks = <&topckgen CLK_TOP_MPLL_D2>,
 260                                  <&topckgen CLK_TOP_SPIM_MST_SEL>,
 261                                  <&infracfg CLK_INFRA_SPI1_CK>,
 262                                  <&infracfg CLK_INFRA_SPI1_HCK_CK>;
 263                         clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
 264                         status = "disabled";
 265                 };
 266
 267                 ssusb: usb@11200000 {
 268                         compatible = "mediatek,mt7986-xhci",
 269                                      "mediatek,mtk-xhci";
 270                         reg = <0 0x11200000 0 0x2e00>,
 271                               <0 0x11203e00 0 0x0100>;
 272                         reg-names = "mac", "ippc";
 273                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 274                         clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
 275                                  <&topckgen CLK_TOP_U2U3_XHCI_SEL>,
 276                                  <&infracfg CLK_INFRA_IUSB_CK>,
 277                                  <&infracfg CLK_INFRA_IUSB_133_CK>,
 278                                  <&infracfg CLK_INFRA_IUSB_66M_CK>;
 279                         clock-names = "sys_ck",
 280                                       "xhci_ck",
 281                                       "ref_ck",
 282                                       "mcu_ck",
 283                                       "dma_ck";
 284                         phys = <&u2port0 PHY_TYPE_USB2>,
 285                                <&u3port0 PHY_TYPE_USB3>,
 286                                <&u2port1 PHY_TYPE_USB2>;
 287                         status = "disabled";
 288                 };
 289
 290                 mmc0: mmc@11230000 {
 291                         compatible = "mediatek,mt7986-mmc";
 292                         reg = <0 0x11230000 0 0x1000>,
 293                               <0 0x11c20000 0 0x1000>;
 294                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 295                         clocks = <&infracfg CLK_INFRA_MSDC_CK>,
 296                                  <&infracfg CLK_INFRA_MSDC_HCK_CK>,
 297                                  <&infracfg CLK_INFRA_MSDC_66M_CK>,
 298                                  <&infracfg CLK_INFRA_MSDC_133M_CK>;
 299                         clock-names = "source", "hclk", "axi_cg", "ahb_cg";
 300                         assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
 301                                           <&topckgen CLK_TOP_EMMC_250M_SEL>;
 302                         assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
 303                                                  <&topckgen CLK_TOP_NET1PLL_D5_D2>;
 304                         status = "disabled";
 305                 };
 306
 307                 pcie: pcie@11280000 {
 308                         compatible = "mediatek,mt7986-pcie",
 309                                      "mediatek,mt8192-pcie";
 310                         device_type = "pci";
 311                         #address-cells = <3>;
 312                         #size-cells = <2>;
 313                         reg = <0x00 0x11280000 0x00 0x4000>;
 314                         reg-names = "pcie-mac";
 315                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 316                         bus-range = <0x00 0xff>;
 317                         ranges = <0x82000000 0x00 0x20000000 0x00
 318                                   0x20000000 0x00 0x10000000>;
 319                         clocks = <&infracfg CLK_INFRA_PCIE_SEL>,
 320                                  <&infracfg CLK_INFRA_IPCIE_CK>,
 321                                  <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
 322                                  <&infracfg CLK_INFRA_IPCIER_CK>,
 323                                  <&infracfg CLK_INFRA_IPCIEB_CK>;
 324                         status = "disabled";
 325
 326                         phys = <&pcie_port PHY_TYPE_PCIE>;
 327                         phy-names = "pcie-phy";
 328
 329                         #interrupt-cells = <1>;
 330                         interrupt-map-mask = <0 0 0 0x7>;
 331                         interrupt-map = <0 0 0 1 &pcie_intc 0>,
 332                                         <0 0 0 2 &pcie_intc 1>,
 333                                         <0 0 0 3 &pcie_intc 2>,
 334                                         <0 0 0 4 &pcie_intc 3>;
 335                         pcie_intc: interrupt-controller {
 336                                 #address-cells = <0>;
 337                                 #interrupt-cells = <1>;
 338                                 interrupt-controller;
 339                         };
 340                 };
 341
 342                 pcie_phy: t-phy@11c00000 {
 343                         compatible = "mediatek,mt7986-tphy",
 344                                      "mediatek,generic-tphy-v2";
 345                         #address-cells = <2>;
 346                         #size-cells = <2>;
 347                         ranges;
 348                         status = "disabled";
 349
 350                         pcie_port: pcie-phy@11c00000 {
 351                                 reg = <0 0x11c00000 0 0x20000>;
 352                                 clocks = <&clk40m>;
 353                                 clock-names = "ref";
 354                                 #phy-cells = <1>;
 355                         };
 356                 };
 357
 358                 usb_phy: t-phy@11e10000 {
 359                         compatible = "mediatek,mt7986-tphy",
 360                                      "mediatek,generic-tphy-v2";
 361                         #address-cells = <2>;
 362                         #size-cells = <2>;
 363                         ranges;
 364                         status = "disabled";
 365
 366                         u2port0: usb-phy@11e10000 {
 367                                 reg = <0 0x11e10000 0 0x700>;
 368                                 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
 369                                          <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
 370                                 clock-names = "ref", "da_ref";
 371                                 #phy-cells = <1>;
 372                         };
 373
 374                         u3port0: usb-phy@11e10700 {
 375                                 reg = <0 0x11e10700 0 0x900>;
 376                                 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
 377                                 clock-names = "ref";
 378                                 #phy-cells = <1>;
 379                         };
 380
 381                         u2port1: usb-phy@11e11000 {
 382                                 reg = <0 0x11e11000 0 0x700>;
 383                                 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
 384                                          <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
 385                                 clock-names = "ref", "da_ref";
 386                                 #phy-cells = <1>;
 387                         };
 388                 };
 389
 390                 ethsys: syscon@15000000 {
 391                          #address-cells = <1>;
 392                          #size-cells = <1>;
 393                          compatible = "mediatek,mt7986-ethsys_ck",
 394                                       "syscon";
 395                          reg = <0 0x15000000 0 0x1000>;
 396                          #clock-cells = <1>;
 397                          #reset-cells = <1>;
 398                 };
 399
 400                 eth: ethernet@15100000 {
 401                         compatible = "mediatek,mt7986-eth";
 402                         reg = <0 0x15100000 0 0x80000>;
 403                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 404                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 405                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 406                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 407                         clocks = <&ethsys CLK_ETH_FE_EN>,
 408                                  <&ethsys CLK_ETH_GP2_EN>,
 409                                  <&ethsys CLK_ETH_GP1_EN>,
 410                                  <&ethsys CLK_ETH_WOCPU1_EN>,
 411                                  <&ethsys CLK_ETH_WOCPU0_EN>,
 412                                  <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
 413                                  <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
 414                                  <&sgmiisys0 CLK_SGMII0_CDR_REF>,
 415                                  <&sgmiisys0 CLK_SGMII0_CDR_FB>,
 416                                  <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
 417                                  <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
 418                                  <&sgmiisys1 CLK_SGMII1_CDR_REF>,
 419                                  <&sgmiisys1 CLK_SGMII1_CDR_FB>,
 420                                  <&topckgen CLK_TOP_NETSYS_SEL>,
 421                                  <&topckgen CLK_TOP_NETSYS_500M_SEL>;
 422                         clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
 423                                       "sgmii_tx250m", "sgmii_rx250m",
 424                                       "sgmii_cdr_ref", "sgmii_cdr_fb",
 425                                       "sgmii2_tx250m", "sgmii2_rx250m",
 426                                       "sgmii2_cdr_ref", "sgmii2_cdr_fb",
 427                                       "netsys0", "netsys1";
 428                         assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
 429                                           <&topckgen CLK_TOP_SGM_325M_SEL>;
 430                         assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
 431                                                  <&apmixedsys CLK_APMIXED_SGMPLL>;
 432                         mediatek,ethsys = <&ethsys>;
 433                         mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
 434                         #reset-cells = <1>;
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         status = "disabled";
 438                 };
 439
 440                 consys: consys@10000000 {
 441                         compatible = "mediatek,mt7986-consys";
 442                         reg = <0 0x10000000 0 0x8600000>;
 443                         memory-region = <&wmcpu_emi>;
 444                 };
 445
 446                 wmac: wmac@18000000 {
 447                         compatible = "mediatek,mt7986-wmac", "mediatek,wbsys";
 448                         resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>;
 449                         reset-names = "consys";
 450                         reg = <0 0x18000000 0 0x1000000>,
 451                               <0 0x10003000 0 0x1000>,
 452                               <0 0x11d10000 0 0x1000>;
 453                         interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 454                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 455                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 456                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
 457                         clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
 458                                  <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
 459                         clock-names = "mcu", "ap2conn";
 460                         memory-region = <&wmcpu_emi>;
 461                         status = "disabled";
 462                 };
 463         };
 464
 465 };