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mediatek: filogic: consolidate adc '32k' clock
[openwrt/staging/noltari.git] / target / linux / mediatek / files-5.15 / arch / arm64 / boot / dts / mediatek / mt7986a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 #include <dt-bindings/clock/mt7986-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/reset/mt7986-resets.h>
12 #include <dt-bindings/thermal/thermal.h>
13
14 / {
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 clk40m: oscillator@0 {
20 compatible = "fixed-clock";
21 clock-frequency = <40000000>;
22 #clock-cells = <0>;
23 clock-output-names = "clkxtal";
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29 cpu0: cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a53";
32 enable-method = "psci";
33 reg = <0x0>;
34 #cooling-cells = <2>;
35 };
36
37 cpu1: cpu@1 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 reg = <0x1>;
42 #cooling-cells = <2>;
43 };
44
45 cpu2: cpu@2 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a53";
48 enable-method = "psci";
49 reg = <0x2>;
50 #cooling-cells = <2>;
51 };
52
53 cpu3: cpu@3 {
54 device_type = "cpu";
55 enable-method = "psci";
56 compatible = "arm,cortex-a53";
57 reg = <0x3>;
58 #cooling-cells = <2>;
59 };
60 };
61
62 psci {
63 compatible = "arm,psci-0.2";
64 method = "smc";
65 };
66
67 reserved-memory {
68 #address-cells = <2>;
69 #size-cells = <2>;
70 ranges;
71
72 /* 64 KiB reserved for ramoops/pstore */
73 ramoops@42ff0000 {
74 compatible = "ramoops";
75 reg = <0 0x42ff0000 0 0x10000>;
76 record-size = <0x1000>;
77 };
78
79 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
80 secmon_reserved: secmon@43000000 {
81 reg = <0 0x43000000 0 0x30000>;
82 no-map;
83 };
84
85 wmcpu_emi: wmcpu-reserved@4fc00000 {
86 no-map;
87 reg = <0 0x4fc00000 0 0x00100000>;
88 };
89 };
90
91 timer {
92 compatible = "arm,armv8-timer";
93 interrupt-parent = <&gic>;
94 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
95 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
96 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
97 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
98 };
99
100 soc {
101 #address-cells = <2>;
102 #size-cells = <2>;
103 compatible = "simple-bus";
104 ranges;
105
106 gic: interrupt-controller@c000000 {
107 compatible = "arm,gic-v3";
108 #interrupt-cells = <3>;
109 interrupt-parent = <&gic>;
110 interrupt-controller;
111 reg = <0 0x0c000000 0 0x10000>, /* GICD */
112 <0 0x0c080000 0 0x80000>, /* GICR */
113 <0 0x0c400000 0 0x2000>, /* GICC */
114 <0 0x0c410000 0 0x1000>, /* GICH */
115 <0 0x0c420000 0 0x2000>; /* GICV */
116 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
117 };
118
119 infracfg: infracfg@10001000 {
120 compatible = "mediatek,mt7986-infracfg", "syscon";
121 reg = <0 0x10001000 0 0x1000>;
122 #clock-cells = <1>;
123 };
124
125 topckgen: topckgen@1001b000 {
126 compatible = "mediatek,mt7986-topckgen", "syscon";
127 reg = <0 0x1001B000 0 0x1000>;
128 #clock-cells = <1>;
129 };
130
131 watchdog: watchdog@1001c000 {
132 compatible = "mediatek,mt7986-wdt",
133 "mediatek,mt6589-wdt";
134 reg = <0 0x1001c000 0 0x1000>;
135 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
136 #reset-cells = <1>;
137 };
138
139 pio: pinctrl@1001f000 {
140 compatible = "mediatek,mt7986a-pinctrl";
141 reg = <0 0x1001f000 0 0x1000>,
142 <0 0x11c30000 0 0x1000>,
143 <0 0x11c40000 0 0x1000>,
144 <0 0x11e20000 0 0x1000>,
145 <0 0x11e30000 0 0x1000>,
146 <0 0x11f00000 0 0x1000>,
147 <0 0x11f10000 0 0x1000>,
148 <0 0x1000b000 0 0x1000>;
149 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
150 "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
151 gpio-controller;
152 #gpio-cells = <2>;
153 gpio-ranges = <&pio 0 0 100>;
154 interrupt-controller;
155 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
156 interrupt-parent = <&gic>;
157 #interrupt-cells = <2>;
158 };
159
160 apmixedsys: apmixedsys@1001e000 {
161 compatible = "mediatek,mt7986-apmixedsys";
162 reg = <0 0x1001E000 0 0x1000>;
163 #clock-cells = <1>;
164 };
165
166 sgmiisys0: syscon@10060000 {
167 compatible = "mediatek,mt7986-sgmiisys_0",
168 "syscon";
169 reg = <0 0x10060000 0 0x1000>;
170 #clock-cells = <1>;
171 };
172
173 sgmiisys1: syscon@10070000 {
174 compatible = "mediatek,mt7986-sgmiisys_1",
175 "syscon";
176 reg = <0 0x10070000 0 0x1000>;
177 #clock-cells = <1>;
178 };
179
180 trng: trng@1020f000 {
181 compatible = "mediatek,mt7986-rng";
182 reg = <0 0x1020f000 0 0x100>;
183 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
184 clock-names = "rng";
185 status = "okay";
186 };
187
188 crypto: crypto@10320000 {
189 compatible = "inside-secure,safexcel-eip97";
190 reg = <0 0x10320000 0 0x40000>;
191 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
195 interrupt-names = "ring0", "ring1", "ring2", "ring3";
196 clocks = <&infracfg CLK_INFRA_EIP97_CK>;
197 clock-names = "infra_eip97_ck";
198 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
199 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
200 status = "okay";
201 };
202
203 pwm: pwm@10048000 {
204 compatible = "mediatek,mt7986-pwm";
205 reg = <0 0x10048000 0 0x1000>;
206 #clock-cells = <1>;
207 #pwm-cells = <2>;
208 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&infracfg CLK_INFRA_PWM_HCK>,
210 <&infracfg CLK_INFRA_PWM_STA>,
211 <&infracfg CLK_INFRA_PWM1_CK>,
212 <&infracfg CLK_INFRA_PWM2_CK>;
213 clock-names = "top", "main", "pwm1", "pwm2";
214 status = "disabled";
215 };
216
217 uart0: serial@11002000 {
218 compatible = "mediatek,mt7986-uart",
219 "mediatek,mt6577-uart";
220 reg = <0 0x11002000 0 0x400>;
221 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
223 <&infracfg CLK_INFRA_UART0_CK>;
224 clock-names = "baud", "bus";
225 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
226 <&infracfg CLK_INFRA_UART0_SEL>;
227 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
228 <&topckgen CLK_TOP_UART_SEL>;
229 status = "disabled";
230 };
231
232 uart1: serial@11003000 {
233 compatible = "mediatek,mt7986-uart",
234 "mediatek,mt6577-uart";
235 reg = <0 0x11003000 0 0x400>;
236 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&infracfg CLK_INFRA_UART1_SEL>,
238 <&infracfg CLK_INFRA_UART1_CK>;
239 clock-names = "baud", "bus";
240 assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
241 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
242 status = "disabled";
243 };
244
245 uart2: serial@11004000 {
246 compatible = "mediatek,mt7986-uart",
247 "mediatek,mt6577-uart";
248 reg = <0 0x11004000 0 0x400>;
249 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&infracfg CLK_INFRA_UART2_SEL>,
251 <&infracfg CLK_INFRA_UART2_CK>;
252 clock-names = "baud", "bus";
253 assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
254 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
255 status = "disabled";
256 };
257
258 i2c0: i2c@11008000 {
259 compatible = "mediatek,mt7986-i2c";
260 reg = <0 0x11008000 0 0x90>,
261 <0 0x10217080 0 0x80>;
262 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
263 clock-div = <5>;
264 clocks = <&infracfg CLK_INFRA_I2C0_CK>,
265 <&infracfg CLK_INFRA_AP_DMA_CK>;
266 clock-names = "main", "dma";
267 #address-cells = <1>;
268 #size-cells = <0>;
269 status = "disabled";
270 };
271
272 spi0: spi@1100a000 {
273 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
274 reg = <0 0x1100a000 0 0x100>;
275 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&topckgen CLK_TOP_MPLL_D2>,
277 <&topckgen CLK_TOP_SPI_SEL>,
278 <&infracfg CLK_INFRA_SPI0_CK>,
279 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
280 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
281 status = "disabled";
282 };
283
284 spi1: spi@1100b000 {
285 compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
286 reg = <0 0x1100b000 0 0x100>;
287 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&topckgen CLK_TOP_MPLL_D2>,
289 <&topckgen CLK_TOP_SPIM_MST_SEL>,
290 <&infracfg CLK_INFRA_SPI1_CK>,
291 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
292 clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
293 status = "disabled";
294 };
295
296 auxadc: adc@1100d000 {
297 compatible = "mediatek,mt7986-auxadc",
298 "mediatek,mt7622-auxadc";
299 reg = <0 0x1100d000 0 0x1000>;
300 clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
301 clock-names = "main";
302 #io-channel-cells = <1>;
303 };
304
305 ssusb: usb@11200000 {
306 compatible = "mediatek,mt7986-xhci",
307 "mediatek,mtk-xhci";
308 reg = <0 0x11200000 0 0x2e00>,
309 <0 0x11203e00 0 0x0100>;
310 reg-names = "mac", "ippc";
311 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
313 <&topckgen CLK_TOP_U2U3_XHCI_SEL>,
314 <&infracfg CLK_INFRA_IUSB_CK>,
315 <&infracfg CLK_INFRA_IUSB_133_CK>,
316 <&infracfg CLK_INFRA_IUSB_66M_CK>;
317 clock-names = "sys_ck",
318 "xhci_ck",
319 "ref_ck",
320 "mcu_ck",
321 "dma_ck";
322 phys = <&u2port0 PHY_TYPE_USB2>,
323 <&u3port0 PHY_TYPE_USB3>,
324 <&u2port1 PHY_TYPE_USB2>;
325 status = "disabled";
326 };
327
328 mmc0: mmc@11230000 {
329 compatible = "mediatek,mt7986-mmc";
330 reg = <0 0x11230000 0 0x1000>,
331 <0 0x11c20000 0 0x1000>;
332 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&infracfg CLK_INFRA_MSDC_CK>,
334 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
335 <&infracfg CLK_INFRA_MSDC_66M_CK>,
336 <&infracfg CLK_INFRA_MSDC_133M_CK>;
337 clock-names = "source", "hclk", "axi_cg", "ahb_cg";
338 assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
339 <&topckgen CLK_TOP_EMMC_250M_SEL>;
340 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
341 <&topckgen CLK_TOP_NET1PLL_D5_D2>;
342 status = "disabled";
343 };
344
345 thermal: thermal@1100c800 {
346 #thermal-sensor-cells = <1>;
347 compatible = "mediatek,mt7986-thermal";
348 reg = <0 0x1100c800 0 0x800>;
349 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&infracfg CLK_INFRA_THERM_CK>,
351 <&infracfg CLK_INFRA_ADC_26M_CK>;
352 clock-names = "therm", "auxadc";
353 mediatek,auxadc = <&auxadc>;
354 mediatek,apmixedsys = <&apmixedsys>;
355 nvmem-cells = <&thermal_calibration>;
356 nvmem-cell-names = "calibration-data";
357 };
358
359 pcie: pcie@11280000 {
360 compatible = "mediatek,mt7986-pcie",
361 "mediatek,mt8192-pcie";
362 device_type = "pci";
363 #address-cells = <3>;
364 #size-cells = <2>;
365 reg = <0x00 0x11280000 0x00 0x4000>;
366 reg-names = "pcie-mac";
367 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
368 bus-range = <0x00 0xff>;
369 ranges = <0x82000000 0x00 0x20000000 0x00
370 0x20000000 0x00 0x10000000>;
371 clocks = <&infracfg CLK_INFRA_PCIE_SEL>,
372 <&infracfg CLK_INFRA_IPCIE_CK>,
373 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
374 <&infracfg CLK_INFRA_IPCIER_CK>,
375 <&infracfg CLK_INFRA_IPCIEB_CK>;
376 status = "disabled";
377
378 phys = <&pcie_port PHY_TYPE_PCIE>;
379 phy-names = "pcie-phy";
380
381 #interrupt-cells = <1>;
382 interrupt-map-mask = <0 0 0 0x7>;
383 interrupt-map = <0 0 0 1 &pcie_intc 0>,
384 <0 0 0 2 &pcie_intc 1>,
385 <0 0 0 3 &pcie_intc 2>,
386 <0 0 0 4 &pcie_intc 3>;
387 pcie_intc: interrupt-controller {
388 #address-cells = <0>;
389 #interrupt-cells = <1>;
390 interrupt-controller;
391 };
392 };
393
394 pcie_phy: t-phy@11c00000 {
395 compatible = "mediatek,mt7986-tphy",
396 "mediatek,generic-tphy-v4";
397 #address-cells = <2>;
398 #size-cells = <2>;
399 ranges;
400 status = "disabled";
401
402 pcie_port: pcie-phy@11c00000 {
403 reg = <0 0x11c00000 0 0x20000>;
404 clocks = <&clk40m>;
405 clock-names = "ref";
406 #phy-cells = <1>;
407 auto_load_valid;
408 auto_load_valid_ln1;
409 nvmem-cells = <&pcie_intr_ln0>,
410 <&pcie_rx_imp_ln0>,
411 <&pcie_tx_imp_ln0>,
412 <&pcie_auto_load_valid_ln0>,
413 <&pcie_intr_ln1>,
414 <&pcie_rx_imp_ln1>,
415 <&pcie_tx_imp_ln1>,
416 <&pcie_auto_load_valid_ln1>;
417 nvmem-cell-names = "intr",
418 "rx_imp",
419 "tx_imp",
420 "auto_load_valid",
421 "intr_ln1",
422 "rx_imp_ln1",
423 "tx_imp_ln1",
424 "auto_load_valid_ln1";
425 };
426 };
427
428 efuse: efuse@11d00000 {
429 compatible = "mediatek,mt7986-efuse",
430 "mediatek,efuse";
431 reg = <0 0x11d00000 0 0x1000>;
432 #address-cells = <1>;
433 #size-cells = <1>;
434
435 thermal_calibration: calib@274 {
436 reg = <0x274 0xc>;
437 };
438
439 comb_auto_load_valid: usb3-alv-imp@8da {
440 reg = <0x8da 1>;
441 bits = <0 1>;
442 };
443
444 comb_rx_imp_p0: usb3-rx-imp@8d8 {
445 reg = <0x8d8 1>;
446 bits = <0 5>;
447 };
448
449 comb_tx_imp_p0: usb3-tx-imp@8d8 {
450 reg = <0x8d8 2>;
451 bits = <5 5>;
452 };
453
454 comb_intr_p0: usb3-intr@8d9 {
455 reg = <0x8d9 1>;
456 bits = <2 6>;
457 };
458
459 u2_auto_load_valid_p0: usb2-alv-p0@8e0 {
460 reg = <0x8e0 1>;
461 bits = <0 1>;
462 };
463
464 u2_intr_p0: usb2-intr-p0@8e0 {
465 reg = <0x8e0 1>;
466 bits = <1 5>;
467 };
468
469 u2_auto_load_valid_p1: usb2-alv-p1@8e0 {
470 reg = <0x8e0 2>;
471 bits = <6 1>;
472 };
473
474 u2_intr_p1: usb2-intr-p1@8e0 {
475 reg = <0x8e0 2>;
476 bits = <7 5>;
477 };
478
479 pcie_rx_imp_ln0: pcie-rx-imp@8d0 {
480 reg = <0x8d0 1>;
481 bits = <0 5>;
482 };
483
484 pcie_tx_imp_ln0: pcie-tx-imp@8d0 {
485 reg = <0x8d0 2>;
486 bits = <5 5>;
487 };
488
489 pcie_intr_ln0: pcie-intr@8d1 {
490 reg = <0x8d1 1>;
491 bits = <2 6>;
492 };
493
494 pcie_auto_load_valid_ln0: pcie-ln0-alv@8d4 {
495 reg = <0x8d4 1>;
496 bits = <0 1>;
497 };
498
499 pcie_rx_imp_ln1: pcie-rx-imp@8d2 {
500 reg = <0x8d2 1>;
501 bits = <0 5>;
502 };
503
504 pcie_tx_imp_ln1: pcie-tx-imp@8d2 {
505 reg = <0x8d2 2>;
506 bits = <5 5>;
507 };
508
509 pcie_intr_ln1: pcie-intr@8d3 {
510 reg = <0x8d3 1>;
511 bits = <2 6>;
512 };
513
514 pcie_auto_load_valid_ln1: pcie-ln1-alv@8d4 {
515 reg = <0x8d4 1>;
516 bits = <1 1>;
517 };
518 };
519
520 usb_phy: t-phy@11e10000 {
521 compatible = "mediatek,mt7986-tphy",
522 "mediatek,generic-tphy-v2";
523 #address-cells = <2>;
524 #size-cells = <2>;
525 ranges;
526 status = "disabled";
527
528 u2port0: usb-phy@11e10000 {
529 reg = <0 0x11e10000 0 0x700>;
530 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
531 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
532 clock-names = "ref", "da_ref";
533 #phy-cells = <1>;
534 auto_load_valid;
535 nvmem-cells = <&u2_intr_p0>, <&u2_auto_load_valid_p0>;
536 nvmem-cell-names = "intr", "auto_load_valid";
537 };
538
539 u3port0: usb-phy@11e10700 {
540 reg = <0 0x11e10700 0 0x900>;
541 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
542 clock-names = "ref";
543 #phy-cells = <1>;
544 auto_load_valid;
545 nvmem-cells = <&comb_intr_p0>,
546 <&comb_rx_imp_p0>,
547 <&comb_tx_imp_p0>,
548 <&comb_auto_load_valid>;
549 nvmem-cell-names = "intr", "rx_imp", "tx_imp", "auto_load_valid";
550 };
551
552 u2port1: usb-phy@11e11000 {
553 reg = <0 0x11e11000 0 0x700>;
554 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
555 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
556 clock-names = "ref", "da_ref";
557 #phy-cells = <1>;
558 auto_load_valid;
559 nvmem-cells = <&u2_intr_p1>, <&u2_auto_load_valid_p1>;
560 nvmem-cell-names = "intr", "auto_load_valid";
561 };
562 };
563
564 ethsys: syscon@15000000 {
565 #address-cells = <1>;
566 #size-cells = <1>;
567 compatible = "mediatek,mt7986-ethsys_ck",
568 "syscon";
569 reg = <0 0x15000000 0 0x1000>;
570 #clock-cells = <1>;
571 #reset-cells = <1>;
572 };
573
574 wed_pcie: wed-pcie@10003000 {
575 compatible = "mediatek,mt7986-wed-pcie",
576 "syscon";
577 reg = <0 0x10003000 0 0x10>;
578 };
579
580 wed0: wed@15010000 {
581 compatible = "mediatek,mt7986-wed",
582 "syscon";
583 reg = <0 0x15010000 0 0x1000>;
584 interrupt-parent = <&gic>;
585 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
586 };
587
588 wed1: wed@15011000 {
589 compatible = "mediatek,mt7986-wed",
590 "syscon";
591 reg = <0 0x15011000 0 0x1000>;
592 interrupt-parent = <&gic>;
593 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
594 };
595
596 eth: ethernet@15100000 {
597 compatible = "mediatek,mt7986-eth";
598 reg = <0 0x15100000 0 0x80000>;
599 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&ethsys CLK_ETH_FE_EN>,
604 <&ethsys CLK_ETH_GP2_EN>,
605 <&ethsys CLK_ETH_GP1_EN>,
606 <&ethsys CLK_ETH_WOCPU1_EN>,
607 <&ethsys CLK_ETH_WOCPU0_EN>,
608 <&sgmiisys0 CLK_SGMII0_TX250M_EN>,
609 <&sgmiisys0 CLK_SGMII0_RX250M_EN>,
610 <&sgmiisys0 CLK_SGMII0_CDR_REF>,
611 <&sgmiisys0 CLK_SGMII0_CDR_FB>,
612 <&sgmiisys1 CLK_SGMII1_TX250M_EN>,
613 <&sgmiisys1 CLK_SGMII1_RX250M_EN>,
614 <&sgmiisys1 CLK_SGMII1_CDR_REF>,
615 <&sgmiisys1 CLK_SGMII1_CDR_FB>,
616 <&topckgen CLK_TOP_NETSYS_SEL>,
617 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
618 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
619 "sgmii_tx250m", "sgmii_rx250m",
620 "sgmii_cdr_ref", "sgmii_cdr_fb",
621 "sgmii2_tx250m", "sgmii2_rx250m",
622 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
623 "netsys0", "netsys1";
624 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
625 <&topckgen CLK_TOP_SGM_325M_SEL>;
626 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
627 <&apmixedsys CLK_APMIXED_SGMPLL>;
628 mediatek,ethsys = <&ethsys>;
629 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
630 mediatek,wed-pcie = <&wed_pcie>;
631 mediatek,wed = <&wed0>, <&wed1>;
632 #reset-cells = <1>;
633 #address-cells = <1>;
634 #size-cells = <0>;
635 status = "disabled";
636 };
637
638 consys: consys@10000000 {
639 compatible = "mediatek,mt7986-consys";
640 reg = <0 0x10000000 0 0x8600000>;
641 memory-region = <&wmcpu_emi>;
642 };
643
644 wmac: wmac@18000000 {
645 compatible = "mediatek,mt7986-wmac", "mediatek,wbsys";
646 resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>;
647 reset-names = "consys";
648 reg = <0 0x18000000 0 0x1000000>,
649 <0 0x10003000 0 0x1000>,
650 <0 0x11d10000 0 0x1000>;
651 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
656 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
657 clock-names = "mcu", "ap2conn";
658 memory-region = <&wmcpu_emi>;
659 status = "disabled";
660 };
661 };
662
663 fan: pwm-fan {
664 compatible = "pwm-fan";
665 /* cooling level (0, 1, 2, 3) : (0% duty, 33% duty, 66% duty, 100% duty) */
666 cooling-levels = <0 86 172 255>;
667 #cooling-cells = <2>;
668 status = "disabled";
669 };
670
671 thermal-zones {
672 cpu_thermal: cpu-thermal {
673 polling-delay-passive = <1000>;
674 polling-delay = <1000>;
675 thermal-sensors = <&thermal 0>;
676 trips {
677 cpu_trip_crit: crit {
678 temperature = <125000>;
679 hysteresis = <2000>;
680 type = "critical";
681 };
682
683 cpu_trip_hot: hot {
684 temperature = <120000>;
685 hysteresis = <2000>;
686 type = "hot";
687 };
688
689 cpu_trip_active_high: active-high {
690 temperature = <115000>;
691 hysteresis = <2000>;
692 type = "active";
693 };
694
695 cpu_trip_active_med: active-med {
696 temperature = <85000>;
697 hysteresis = <2000>;
698 type = "active";
699 };
700
701 cpu_trip_active_low: active-low {
702 temperature = <60000>;
703 hysteresis = <2000>;
704 type = "passive";
705 };
706 };
707
708 cooling-maps {
709 cpu-active-high {
710 /* active: set fan to cooling level 3 */
711 cooling-device = <&fan 3 3>;
712 trip = <&cpu_trip_active_high>;
713 };
714
715 cpu-active-med {
716 /* active: set fan to cooling level 2 */
717 cooling-device = <&fan 2 2>;
718 trip = <&cpu_trip_active_med>;
719 };
720
721 cpu-active-low {
722 /* passive: set fan to cooling level 1 */
723 cooling-device = <&fan 1 1>;
724 trip = <&cpu_trip_active_low>;
725 };
726 };
727 };
728 };
729 };
Staging tree of Alvaro Fernandez Rojas