target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Ryder Lee <ryder.lee@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/input/input.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10
  11 #include "mt7622.dtsi"
  12 #include "mt6380.dtsi"
  13
  14 / {
  15         model = "Bananapi BPI-R64";
  16         compatible = "bananapi,bpi-r64", "mediatek,mt7622";
  17
  18         chosen {
  19                 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
  20         };
  21
  22         cpus {
  23                 cpu@0 {
  24                         proc-supply = <&mt6380_vcpu_reg>;
  25                         sram-supply = <&mt6380_vm_reg>;
  26                 };
  27
  28                 cpu@1 {
  29                         proc-supply = <&mt6380_vcpu_reg>;
  30                         sram-supply = <&mt6380_vm_reg>;
  31                 };
  32         };
  33
  34         gpio-keys {
  35                 compatible = "gpio-keys";
  36
  37                 factory {
  38                         label = "factory";
  39                         linux,code = <BTN_0>;
  40                         gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  41                 };
  42
  43                 wps {
  44                         label = "wps";
  45                         linux,code = <KEY_WPS_BUTTON>;
  46                         gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
  47                 };
  48         };
  49
  50         gsw: gsw@0 {
  51                 compatible = "mediatek,mt753x";
  52                 mediatek,ethsys = <&ethsys>;
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55         };
  56
  57         leds {
  58                 compatible = "gpio-leds";
  59
  60                 green {
  61                         label = "bpi-r64:pio:green";
  62                         gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
  63                         default-state = "off";
  64                 };
  65
  66                 red {
  67                         label = "bpi-r64:pio:red";
  68                         gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
  69                         default-state = "off";
  70                 };
  71         };
  72
  73         memory {
  74                 reg = <0 0x40000000 0 0x40000000>;
  75         };
  76
  77         reg_1p8v: regulator-1p8v {
  78                 compatible = "regulator-fixed";
  79                 regulator-name = "fixed-1.8V";
  80                 regulator-min-microvolt = <1800000>;
  81                 regulator-max-microvolt = <1800000>;
  82                 regulator-always-on;
  83         };
  84
  85         reg_3p3v: regulator-3p3v {
  86                 compatible = "regulator-fixed";
  87                 regulator-name = "fixed-3.3V";
  88                 regulator-min-microvolt = <3300000>;
  89                 regulator-max-microvolt = <3300000>;
  90                 regulator-boot-on;
  91                 regulator-always-on;
  92         };
  93
  94         reg_5v: regulator-5v {
  95                 compatible = "regulator-fixed";
  96                 regulator-name = "fixed-5V";
  97                 regulator-min-microvolt = <5000000>;
  98                 regulator-max-microvolt = <5000000>;
  99                 regulator-boot-on;
 100                 regulator-always-on;
 101         };
 102
 103 };
 104
 105 &bch {
 106         status = "disabled";
 107 };
 108
 109 &btif {
 110         status = "okay";
 111 };
 112
 113 &cir {
 114         pinctrl-names = "default";
 115         pinctrl-0 = <&irrx_pins>;
 116         status = "okay";
 117 };
 118
 119 &eth {
 120         status = "okay";
 121         gmac0: mac@0 {
 122                 compatible = "mediatek,eth-mac";
 123                 reg = <0>;
 124                 phy-mode = "sgmii";
 125                 fixed-link {
 126                         speed = <1000>;
 127                         full-duplex;
 128                         pause;
 129                 };
 130         };
 131         gmac1: mac@1 {
 132                 compatible = "mediatek,eth-mac";
 133                 reg = <1>;
 134                 phy-mode = "rgmii";
 135                 fixed-link {
 136                         speed = <1000>;
 137                         full-duplex;
 138                         pause;
 139                 };
 140         };
 141         mdio: mdio-bus {
 142                 #address-cells = <1>;
 143                 #size-cells = <0>;
 144         };
 145 };
 146
 147 &gsw {
 148         mediatek,mdio = <&mdio>;
 149         mediatek,portmap = "wllll";
 150         mediatek,mdio_master_pinmux = <0>;
 151         reset-gpios = <&pio 54 0>;
 152         interrupt-parent = <&pio>;
 153         interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
 154         status = "okay";
 155
 156         port5: port@5 {
 157                 compatible = "mediatek,mt753x-port";
 158                 reg = <5>;
 159                 phy-mode = "rgmii";
 160                 fixed-link {
 161                         speed = <1000>;
 162                         full-duplex;
 163                 };
 164         };
 165
 166         port6: port@6 {
 167                 compatible = "mediatek,mt753x-port";
 168                 reg = <6>;
 169                 phy-mode = "sgmii";
 170                 fixed-link {
 171                         speed = <2500>;
 172                         full-duplex;
 173                 };
 174         };
 175 };
 176
 177 &i2c1 {
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&i2c1_pins>;
 180         status = "okay";
 181 };
 182
 183 &i2c2 {
 184         pinctrl-names = "default";
 185         pinctrl-0 = <&i2c2_pins>;
 186         status = "okay";
 187 };
 188
 189 &mmc0 {
 190         pinctrl-names = "default", "state_uhs";
 191         pinctrl-0 = <&emmc_pins_default>;
 192         pinctrl-1 = <&emmc_pins_uhs>;
 193         status = "okay";
 194         bus-width = <8>;
 195         max-frequency = <50000000>;
 196         cap-mmc-highspeed;
 197         mmc-hs200-1_8v;
 198         vmmc-supply = <&reg_3p3v>;
 199         vqmmc-supply = <&reg_1p8v>;
 200         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 201         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 202         non-removable;
 203 };
 204
 205 &mmc1 {
 206         pinctrl-names = "default", "state_uhs";
 207         pinctrl-0 = <&sd0_pins_default>;
 208         pinctrl-1 = <&sd0_pins_uhs>;
 209         status = "okay";
 210         bus-width = <4>;
 211         max-frequency = <50000000>;
 212         cap-sd-highspeed;
 213         r_smpl = <1>;
 214         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 215         vmmc-supply = <&reg_3p3v>;
 216         vqmmc-supply = <&reg_3p3v>;
 217         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 218         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 219 };
 220
 221 &nandc {
 222         pinctrl-names = "default";
 223         pinctrl-0 = <&parallel_nand_pins>;
 224         status = "disabled";
 225 };
 226
 227 &nor_flash {
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&spi_nor_pins>;
 230         status = "disabled";
 231
 232         flash@0 {
 233                 compatible = "jedec,spi-nor";
 234                 reg = <0>;
 235         };
 236 };
 237
 238 &pcie {
 239         pinctrl-names = "default";
 240         pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
 241         status = "okay";
 242
 243         pcie@0,0 {
 244                 status = "okay";
 245         };
 246
 247         pcie@1,0 {
 248                 status = "okay";
 249         };
 250 };
 251
 252 &pio {
 253         /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 254          * SATA functions. i.e. output-high: PCIe, output-low: SATA
 255          */
 256         asm_sel {
 257                 gpio-hog;
 258                 gpios = <90 GPIO_ACTIVE_HIGH>;
 259                 output-high;
 260         };
 261
 262         /* eMMC is shared pin with parallel NAND */
 263         emmc_pins_default: emmc-pins-default {
 264                 mux {
 265                         function = "emmc", "emmc_rst";
 266                         groups = "emmc";
 267                 };
 268
 269                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 270                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 271                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 272                  */
 273                 conf-cmd-dat {
 274                         pins = "NDL0", "NDL1", "NDL2",
 275                                "NDL3", "NDL4", "NDL5",
 276                                "NDL6", "NDL7", "NRB";
 277                         input-enable;
 278                         bias-pull-up;
 279                 };
 280
 281                 conf-clk {
 282                         pins = "NCLE";
 283                         bias-pull-down;
 284                 };
 285         };
 286
 287         emmc_pins_uhs: emmc-pins-uhs {
 288                 mux {
 289                         function = "emmc";
 290                         groups = "emmc";
 291                 };
 292
 293                 conf-cmd-dat {
 294                         pins = "NDL0", "NDL1", "NDL2",
 295                                "NDL3", "NDL4", "NDL5",
 296                                "NDL6", "NDL7", "NRB";
 297                         input-enable;
 298                         drive-strength = <4>;
 299                         bias-pull-up;
 300                 };
 301
 302                 conf-clk {
 303                         pins = "NCLE";
 304                         drive-strength = <4>;
 305                         bias-pull-down;
 306                 };
 307         };
 308
 309         eth_pins: eth-pins {
 310                 mux {
 311                         function = "eth";
 312                         groups = "mdc_mdio", "rgmii_via_gmac2";
 313                 };
 314         };
 315
 316         i2c1_pins: i2c1-pins {
 317                 mux {
 318                         function = "i2c";
 319                         groups =  "i2c1_0";
 320                 };
 321         };
 322
 323         i2c2_pins: i2c2-pins {
 324                 mux {
 325                         function = "i2c";
 326                         groups =  "i2c2_0";
 327                 };
 328         };
 329
 330         i2s1_pins: i2s1-pins {
 331                 mux {
 332                         function = "i2s";
 333                         groups =  "i2s_out_mclk_bclk_ws",
 334                                   "i2s1_in_data",
 335                                   "i2s1_out_data";
 336                 };
 337
 338                 conf {
 339                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 340                                "I2S_WS", "I2S_MCLK";
 341                         drive-strength = <12>;
 342                         bias-pull-down;
 343                 };
 344         };
 345
 346         irrx_pins: irrx-pins {
 347                 mux {
 348                         function = "ir";
 349                         groups =  "ir_1_rx";
 350                 };
 351         };
 352
 353         irtx_pins: irtx-pins {
 354                 mux {
 355                         function = "ir";
 356                         groups =  "ir_1_tx";
 357                 };
 358         };
 359
 360         /* Parallel nand is shared pin with eMMC */
 361         parallel_nand_pins: parallel-nand-pins {
 362                 mux {
 363                         function = "flash";
 364                         groups = "par_nand";
 365                 };
 366         };
 367
 368         pcie0_pins: pcie0-pins {
 369                 mux {
 370                         function = "pcie";
 371                         groups = "pcie0_pad_perst",
 372                                  "pcie0_1_waken",
 373                                  "pcie0_1_clkreq";
 374                 };
 375         };
 376
 377         pcie1_pins: pcie1-pins {
 378                 mux {
 379                         function = "pcie";
 380                         groups = "pcie1_pad_perst",
 381                                  "pcie1_0_waken",
 382                                  "pcie1_0_clkreq";
 383                 };
 384         };
 385
 386         pmic_bus_pins: pmic-bus-pins {
 387                 mux {
 388                         function = "pmic";
 389                         groups = "pmic_bus";
 390                 };
 391         };
 392
 393         pwm7_pins: pwm1-2-pins {
 394                 mux {
 395                         function = "pwm";
 396                         groups = "pwm_ch7_2";
 397                 };
 398         };
 399
 400         wled_pins: wled-pins {
 401                 mux {
 402                         function = "led";
 403                         groups = "wled";
 404                 };
 405         };
 406
 407         sd0_pins_default: sd0-pins-default {
 408                 mux {
 409                         function = "sd";
 410                         groups = "sd_0";
 411                 };
 412
 413                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 414                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 415                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 416                  */
 417                 conf-cmd-data {
 418                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 419                                "I2S2_IN","I2S4_OUT";
 420                         input-enable;
 421                         drive-strength = <8>;
 422                         bias-pull-up;
 423                 };
 424                 conf-clk {
 425                         pins = "I2S3_OUT";
 426                         drive-strength = <12>;
 427                         bias-pull-down;
 428                 };
 429                 conf-cd {
 430                         pins = "TXD3";
 431                         bias-pull-up;
 432                 };
 433         };
 434
 435         sd0_pins_uhs: sd0-pins-uhs {
 436                 mux {
 437                         function = "sd";
 438                         groups = "sd_0";
 439                 };
 440
 441                 conf-cmd-data {
 442                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 443                                "I2S2_IN","I2S4_OUT";
 444                         input-enable;
 445                         bias-pull-up;
 446                 };
 447
 448                 conf-clk {
 449                         pins = "I2S3_OUT";
 450                         bias-pull-down;
 451                 };
 452         };
 453
 454         /* Serial NAND is shared pin with SPI-NOR */
 455         serial_nand_pins: serial-nand-pins {
 456                 mux {
 457                         function = "flash";
 458                         groups = "snfi";
 459                 };
 460         };
 461
 462         spic0_pins: spic0-pins {
 463                 mux {
 464                         function = "spi";
 465                         groups = "spic0_0";
 466                 };
 467         };
 468
 469         spic1_pins: spic1-pins {
 470                 mux {
 471                         function = "spi";
 472                         groups = "spic1_0";
 473                 };
 474         };
 475
 476         /* SPI-NOR is shared pin with serial NAND */
 477         spi_nor_pins: spi-nor-pins {
 478                 mux {
 479                         function = "flash";
 480                         groups = "spi_nor";
 481                 };
 482         };
 483
 484         /* serial NAND is shared pin with SPI-NOR */
 485         serial_nand_pins: serial-nand-pins {
 486                 mux {
 487                         function = "flash";
 488                         groups = "snfi";
 489                 };
 490         };
 491
 492         uart0_pins: uart0-pins {
 493                 mux {
 494                         function = "uart";
 495                         groups = "uart0_0_tx_rx" ;
 496                 };
 497         };
 498
 499         uart2_pins: uart2-pins {
 500                 mux {
 501                         function = "uart";
 502                         groups = "uart2_1_tx_rx" ;
 503                 };
 504         };
 505
 506         watchdog_pins: watchdog-pins {
 507                 mux {
 508                         function = "watchdog";
 509                         groups = "watchdog";
 510                 };
 511         };
 512 };
 513
 514 &pwm {
 515         pinctrl-names = "default";
 516         pinctrl-0 = <&pwm7_pins>;
 517         status = "okay";
 518 };
 519
 520 &pwrap {
 521         pinctrl-names = "default";
 522         pinctrl-0 = <&pmic_bus_pins>;
 523
 524         status = "okay";
 525 };
 526
 527 &sata {
 528         status = "disable";
 529 };
 530
 531 &sata_phy {
 532         status = "disable";
 533 };
 534
 535 &spi0 {
 536         pinctrl-names = "default";
 537         pinctrl-0 = <&spic0_pins>;
 538         status = "okay";
 539 };
 540
 541 &spi1 {
 542         pinctrl-names = "default";
 543         pinctrl-0 = <&spic1_pins>;
 544         status = "okay";
 545 };
 546
 547 &ssusb {
 548         vusb33-supply = <&reg_3p3v>;
 549         vbus-supply = <&reg_5v>;
 550         status = "okay";
 551 };
 552
 553 &u3phy {
 554         status = "okay";
 555 };
 556
 557 &uart0 {
 558         pinctrl-names = "default";
 559         pinctrl-0 = <&uart0_pins>;
 560         status = "okay";
 561 };
 562
 563 &uart2 {
 564         pinctrl-names = "default";
 565         pinctrl-0 = <&uart2_pins>;
 566         status = "okay";
 567 };
 568
 569 &watchdog {
 570         pinctrl-names = "default";
 571         pinctrl-0 = <&watchdog_pins>;
 572         status = "okay";
 573 };