target/linux/mediatek/dts/mt7986a-zyxel-ex5700-telenor.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6
   7 #include "mt7986a.dtsi"
   8
   9 / {
  10         model = "ZyXEL EX5700 (Telenor)";
  11         compatible = "zyxel,ex5700-telenor", "mediatek,mt7986a";
  12
  13         aliases {
  14                 serial0 = &uart0;
  15                 ethernet0 = &gmac0;
  16                 led-boot = &led_status_green;
  17                 led-failsafe = &led_status_green;
  18                 led-running = &led_status_green;
  19                 led-upgrade = &led_status_amber;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24
  25                 // Stock U-Boot crashes unless /chosen/bootargs exists
  26                 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8";
  27         };
  28
  29         memory {
  30                 reg = <0 0x40000000 0 0x40000000>;
  31         };
  32
  33         reg_3p3v: regulator-3p3v {
  34                 compatible = "regulator-fixed";
  35                 regulator-name = "fixed-3.3V";
  36                 regulator-min-microvolt = <3300000>;
  37                 regulator-max-microvolt = <3300000>;
  38                 regulator-boot-on;
  39                 regulator-always-on;
  40         };
  41
  42         reg_5v: regulator-5v {
  43                 compatible = "regulator-fixed";
  44                 regulator-name = "fixed-5V";
  45                 regulator-min-microvolt = <5000000>;
  46                 regulator-max-microvolt = <5000000>;
  47                 regulator-boot-on;
  48                 regulator-always-on;
  49         };
  50
  51
  52         keys {
  53                 compatible = "gpio-keys";
  54                 poll-interval = <20>;
  55
  56                 reset-button {
  57                         label = "reset";
  58                         gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  59                         linux,code = <KEY_RESTART>;
  60                 };
  61
  62                 wps-button {
  63                         label = "wps";
  64                         gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  65                         linux,code = <KEY_WPS_BUTTON>;
  66                 };
  67         };
  68
  69         leds {
  70                 compatible = "gpio-leds";
  71
  72                 red1 {
  73                         label = "red:net";
  74                         gpios = <&pio 23 GPIO_ACTIVE_HIGH>;
  75                         default-state = "off";
  76                 };
  77
  78                 green1 {
  79                         label = "green:net";
  80                         gpios = <&pio 25 GPIO_ACTIVE_HIGH>;
  81                         default-state = "off";
  82                 };
  83
  84                 amber1 {
  85                         label = "amber:net";
  86                         gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
  87                         default-state = "off";
  88                 };
  89
  90                 white2 {
  91                         label = "white:status";
  92                         gpios = <&pio 16 GPIO_ACTIVE_HIGH>;
  93                         default-state = "off";
  94                 };
  95
  96                 red2 {
  97                         label = "red:status";
  98                         gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
  99                         default-state = "off";
 100                 };
 101
 102                 led_status_green: green2 {
 103                         label = "green:status";
 104                         gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
 105                         default-state = "off";
 106                 };
 107
 108                 led_status_amber: amber2 {
 109                         label = "amber:status";
 110                         gpios = <&pio 18 GPIO_ACTIVE_HIGH>;
 111                         default-state = "off";
 112                 };
 113         };
 114
 115 };
 116
 117 &eth {
 118         status = "okay";
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&eth_pins>;
 121
 122         gmac0: mac@0 {
 123                 compatible = "mediatek,eth-mac";
 124                 reg = <0>;
 125                 phy-mode = "2500base-x";
 126
 127                 fixed-link {
 128                         speed = <2500>;
 129                         full-duplex;
 130                         pause;
 131                 };
 132         };
 133
 134         mac@1 {
 135                 compatible = "mediatek,eth-mac";
 136                 reg = <1>;
 137                 label = "wan";
 138                 phy-mode = "2500base-x";
 139                 phy-handle = <&phy6>;
 140         };
 141
 142         mdio: mdio-bus {
 143                 #address-cells = <1>;
 144                 #size-cells = <0>;
 145         };
 146 };
 147
 148 &mdio {
 149         reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
 150         reset-delay-us = <50000>;
 151         reset-post-delay-us = <20000>;
 152
 153         phy5: phy@5 {
 154                 compatible = "ethernet-phy-ieee802.3-c45";
 155                 reg = <5>;
 156         };
 157
 158         phy6: phy@6 {
 159                 compatible = "ethernet-phy-ieee802.3-c45";
 160                 reg = <6>;
 161         };
 162
 163         switch: switch@1f {
 164                 compatible = "mediatek,mt7531";
 165                 reg = <31>;
 166                 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
 167                 interrupt-controller;
 168                 #interrupt-cells = <1>;
 169                 interrupt-parent = <&pio>;
 170                 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
 171         };
 172 };
 173
 174 &switch {
 175         ports {
 176                 #address-cells = <1>;
 177                 #size-cells = <0>;
 178
 179                 port@0 {
 180                         reg = <0>;
 181                         label = "lan3";
 182                 };
 183
 184                 port@1 {
 185                         reg = <1>;
 186                         label = "lan2";
 187                 };
 188
 189                 port@2 {
 190                         reg = <2>;
 191                         label = "lan1";
 192                 };
 193
 194                 port@5 {
 195                         reg = <5>;
 196                         label = "lan4";
 197                         phy-mode = "2500base-x";
 198                         phy-handle = <&phy5>;
 199                 };
 200
 201                 port@6 {
 202                         reg = <6>;
 203                         ethernet = <&gmac0>;
 204                         phy-mode = "2500base-x";
 205
 206                         fixed-link {
 207                                 speed = <2500>;
 208                                 full-duplex;
 209                                 pause;
 210                         };
 211                 };
 212         };
 213 };
 214
 215 &crypto {
 216         status = "okay";
 217 };
 218
 219 &pcie {
 220         pinctrl-names = "default";
 221         pinctrl-0 = <&pcie_pins>;
 222         status = "okay";
 223
 224         pcie@0,0 {
 225                 reg = <0x0000 0 0 0 0>;
 226
 227                 wifi@0,0 {
 228                         compatible = "mediatek,mt76";
 229                         reg = <0x0000 0 0 0 0>;
 230                         mediatek,mtd-eeprom = <&factory 0xa0000>;
 231                 };
 232         };
 233 };
 234
 235 &pcie_phy {
 236         status = "okay";
 237 };
 238
 239 &watchdog {
 240         status = "okay";
 241 };
 242
 243 &wifi {
 244         status = "okay";
 245         pinctrl-names = "default";
 246         pinctrl-0 = <&wf_5g_pins>;
 247
 248         mediatek,mtd-eeprom = <&factory 0x0>;
 249 };
 250
 251 &pio {
 252         eth_pins: eth-pins {
 253                 mux {
 254                         function = "eth";
 255                         groups = "switch_int", "mdc_mdio";
 256                 };
 257         };
 258
 259         pcie_pins: pcie-pins {
 260                 mux {
 261                         function = "pcie";
 262                         groups = "pcie_pereset"; // "pcie_clk" and "pcie_wake" is unused?
 263                 };
 264         };
 265
 266         spi_flash_pins: spi-flash-pins-33-to-38 {
 267                 mux {
 268                         function = "spi";
 269                         groups = "spi0", "spi0_wp_hold";
 270                 };
 271                 conf-pu {
 272                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 273                         drive-strength = <8>;
 274                         mediatek,pull-up-adv = <0>; /* bias-disable */
 275                 };
 276                 conf-pd {
 277                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 278                         drive-strength = <8>;
 279                         mediatek,pull-down-adv = <0>; /* bias-disable */
 280                 };
 281         };
 282
 283         wf_5g_pins: wf_5g-pins {
 284                 mux {
 285                         function = "wifi";
 286                         groups = "wf_5g";
 287                 };
 288                 conf {
 289                         pins = "WF1_HB1", "WF1_HB2", "WF1_HB3", "WF1_HB4",
 290                                "WF1_HB0", "WF1_HB5", "WF1_HB6", "WF1_HB7",
 291                                "WF1_HB8", "WF1_TOP_CLK", "WF1_TOP_DATA";
 292                         drive-strength = <4>;
 293                 };
 294         };
 295
 296 };
 297
 298 &spi0 {
 299         pinctrl-names = "default";
 300         pinctrl-0 = <&spi_flash_pins>;
 301         cs-gpios = <0>, <0>;
 302         status = "okay";
 303
 304         flash@0 {
 305                 compatible = "jedec,spi-nor";
 306                 reg = <0>;
 307                 spi-max-frequency = <20000000>;
 308         };
 309
 310         flash@1 {
 311                 compatible = "spi-nand";
 312                 reg = <1>;
 313
 314                 mediatek,nmbm;
 315                 mediatek,bmt-max-ratio = <1>;
 316                 mediatek,bmt-max-reserved-blocks = <64>;
 317
 318                 spi-max-frequency = <20000000>;
 319                 spi-tx-bus-width = <4>;
 320                 spi-rx-bus-width = <4>;
 321
 322                 partitions {
 323                         compatible = "fixed-partitions";
 324                         #address-cells = <1>;
 325                         #size-cells = <1>;
 326
 327                         partition@0 {
 328                                 label = "BL2";
 329                                 reg = <0x000000 0x100000>;
 330                                 read-only;
 331                         };
 332                         partition@100000 {
 333                                 label = "u-boot-env";
 334                                 reg = <0x100000 0x80000>;
 335                         };
 336                         factory: partition@180000 {
 337                                 label = "Factory";
 338                                 reg = <0x180000 0x200000>;
 339                                 read-only;
 340                         };
 341                         partition@380000 {
 342                                 label = "FIP";
 343                                 reg = <0x380000 0x200000>;
 344                                 read-only;
 345                         };
 346                         partition@580000 {
 347                                 label = "ubi";
 348                                 reg = <0x580000 0x1da80000>;
 349                         };
 350                 };
 351         };
 352 };
 353
 354 &ssusb {
 355         vusb33-supply = <&reg_3p3v>;
 356         vbus-supply = <&reg_5v>;
 357         status = "okay";
 358 };
 359
 360 &trng {
 361         status = "okay";
 362 };
 363
 364 &uart0 {
 365         status = "okay";
 366 };
 367
 368 &usb_phy {
 369         status = "okay";
 370 };