target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6
   7 #include "mt7986a.dtsi"
   8
   9 / {
  10         model = "Xiaomi Redmi Router AX6000";
  11         compatible = "xiaomi,redmi-router-ax6000", "mediatek,mt7986a";
  12
  13         aliases {
  14                 serial0 = &uart0;
  15         };
  16
  17         chosen {
  18                 stdout-path = "serial0:115200n8";
  19         };
  20
  21         memory {
  22                 reg = <0 0x40000000 0 0x20000000>;
  23         };
  24
  25         keys {
  26                 compatible = "gpio-keys";
  27
  28                 reset {
  29                         label = "reset";
  30                         gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  31                         linux,code = <KEY_RESTART>;
  32                 };
  33
  34                 mesh {
  35                         label = "mesh";
  36                         gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  37                         linux,code = <BTN_9>;
  38                         linux,input-type = <EV_SW>;
  39                 };
  40         };
  41 };
  42
  43 &eth {
  44         status = "okay";
  45
  46         gmac0: mac@0 {
  47                 compatible = "mediatek,eth-mac";
  48                 reg = <0>;
  49                 phy-mode = "2500base-x";
  50
  51                 nvmem-cells = <&macaddr_factory_4>;
  52                 nvmem-cell-names = "mac-address";
  53                 mac-address-increment = <(-1)>;
  54
  55                 fixed-link {
  56                         speed = <2500>;
  57                         full-duplex;
  58                         pause;
  59                 };
  60         };
  61
  62         mdio: mdio-bus {
  63                 #address-cells = <1>;
  64                 #size-cells = <0>;
  65         };
  66 };
  67
  68 &mdio {
  69         switch: switch@0 {
  70                 compatible = "mediatek,mt7531";
  71                 reg = <31>;
  72                 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
  73                 interrupt-controller;
  74                 #interrupt-cells = <1>;
  75                 interrupt-parent = <&pio>;
  76                 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
  77         };
  78 };
  79
  80 &pio {
  81         spi_flash_pins: spi-flash-pins-33-to-38 {
  82                 mux {
  83                         function = "spi";
  84                         groups = "spi0", "spi0_wp_hold";
  85                 };
  86                 conf-pu {
  87                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
  88                         drive-strength = <8>;
  89                         mediatek,pull-up-adv = <0>; /* bias-disable */
  90                 };
  91                 conf-pd {
  92                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
  93                         drive-strength = <8>;
  94                         mediatek,pull-down-adv = <0>; /* bias-disable */
  95                 };
  96         };
  97
  98         wf_2g_5g_pins: wf_2g_5g-pins {
  99                 mux {
 100                         function = "wifi";
 101                         groups = "wf_2g", "wf_5g";
 102                 };
 103                 conf {
 104                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 105                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 106                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 107                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 108                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 109                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 110                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 111                         drive-strength = <4>;
 112                 };
 113         };
 114 };
 115
 116 &spi0 {
 117         pinctrl-names = "default";
 118         pinctrl-0 = <&spi_flash_pins>;
 119         cs-gpios = <0>, <0>;
 120         status = "okay";
 121
 122         flash@0 {
 123                 compatible = "spi-nand";
 124                 #address-cells = <1>;
 125                 #size-cells = <1>;
 126                 reg = <0>;
 127
 128                 mediatek,nmbm;
 129                 mediatek,bmt-max-ratio = <1>;
 130                 mediatek,bmt-max-reserved-blocks = <64>;
 131
 132                 spi-max-frequency = <20000000>;
 133                 spi-tx-buswidth = <4>;
 134                 spi-rx-buswidth = <4>;
 135
 136                 partitions {
 137                         compatible = "fixed-partitions";
 138                         #address-cells = <1>;
 139                         #size-cells = <1>;
 140
 141                         partition@0 {
 142                                 label = "BL2";
 143                                 reg = <0x0 0x100000>;
 144                                 read-only;
 145                         };
 146
 147                         partition@100000 {
 148                                 label = "Nvram";
 149                                 reg = <0x100000 0x40000>;
 150                         };
 151
 152                         partition@140000 {
 153                                 label = "Bdata";
 154                                 reg = <0x140000 0x40000>;
 155                         };
 156
 157                         factory: partition@180000 {
 158                                 label = "Factory";
 159                                 reg = <0x180000 0x200000>;
 160                                 read-only;
 161
 162                                 compatible = "nvmem-cells";
 163                                 #address-cells = <1>;
 164                                 #size-cells = <1>;
 165
 166                                 macaddr_factory_4: macaddr@4 {
 167                                         reg = <0x4 0x6>;
 168                                 };
 169                         };
 170
 171                         partition@380000 {
 172                                 label = "FIP";
 173                                 reg = <0x380000 0x200000>;
 174                                 read-only;
 175                         };
 176
 177                         partition@580000 {
 178                                 label = "crash";
 179                                 reg = <0x580000 0x40000>;
 180                                 read-only;
 181                         };
 182
 183                         partition@5c0000 {
 184                                 label = "crash_log";
 185                                 reg = <0x5c0000 0x40000>;
 186                                 read-only;
 187                         };
 188
 189                         /* ubi partition is the result of squashing
 190                          * consecutive stock partitions:
 191                          * - ubi
 192                          * - ubi1
 193                          * - overlay
 194                          */
 195                         partition@600000 {
 196                                 label = "ubi";
 197                                 reg = <0x600000 0x6e00000>;
 198                         };
 199
 200                         /* last 12 MiB is reserved for NMBM bad block table */
 201                 };
 202         };
 203 };
 204
 205 &switch {
 206         ports {
 207                 #address-cells = <1>;
 208                 #size-cells = <0>;
 209
 210                 port@1 {
 211                         reg = <1>;
 212                         label = "lan4";
 213                 };
 214
 215                 port@2 {
 216                         reg = <2>;
 217                         label = "lan3";
 218                 };
 219
 220                 port@3 {
 221                         reg = <3>;
 222                         label = "lan2";
 223                 };
 224
 225                 port@4 {
 226                         reg = <4>;
 227                         label = "wan";
 228                 };
 229
 230                 port@6 {
 231                         reg = <6>;
 232                         label = "cpu";
 233                         ethernet = <&gmac0>;
 234                         phy-mode = "2500base-x";
 235
 236                         fixed-link {
 237                                 speed = <2500>;
 238                                 full-duplex;
 239                                 pause;
 240                         };
 241                 };
 242         };
 243 };
 244
 245 &wmac {
 246         status = "okay";
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&wf_2g_5g_pins>;
 249
 250         mediatek,mtd-eeprom = <&factory 0x0>;
 251 };
 252
 253 &uart0 {
 254         status = "okay";
 255 };