target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 /dts-v1/;
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6
   7 #include "mt7981.dtsi"
   8
   9 / {
  10         model = "Cetron CT3003";
  11         compatible = "cetron,ct3003", "mediatek,mt7981";
  12
  13         aliases {
  14                 serial0 = &uart0;
  15                 led-boot = &led_status_red;
  16                 led-failsafe = &led_status_red;
  17                 led-running = &led_status_green;
  18                 led-upgrade = &led_status_green;
  19         };
  20
  21         chosen {
  22                 stdout-path = "serial0:115200n8";
  23         };
  24
  25         memory {
  26                 reg = <0 0x40000000 0 0x10000000>;
  27         };
  28
  29         gpio-keys {
  30                 compatible = "gpio-keys";
  31
  32                 reset {
  33                         label = "reset";
  34                         linux,code = <KEY_RESTART>;
  35                         gpios = <&pio 1 GPIO_ACTIVE_LOW>;
  36                 };
  37
  38                 wps {
  39                         label = "wps";
  40                         linux,code = <KEY_WPS_BUTTON>;
  41                         gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  42                 };
  43         };
  44
  45         leds {
  46                 compatible = "gpio-leds";
  47
  48                 led_status_red: led_status_red {
  49                         label = "red:status";
  50                         gpios = <&pio 3 GPIO_ACTIVE_LOW>;
  51                 };
  52
  53                 led_status_green: led_status_green {
  54                         label = "green:status";
  55                         gpios = <&pio 7 GPIO_ACTIVE_LOW>;
  56                 };
  57         };
  58 };
  59
  60 &eth {
  61         status = "okay";
  62
  63         gmac0: mac@0 {
  64                 compatible = "mediatek,eth-mac";
  65                 reg = <0>;
  66                 phy-mode = "2500base-x";
  67
  68                 nvmem-cells = <&macaddr_art_0>;
  69                 nvmem-cell-names = "mac-address";
  70
  71                 fixed-link {
  72                         speed = <2500>;
  73                         full-duplex;
  74                         pause;
  75                 };
  76         };
  77 };
  78
  79 &mdio_bus {
  80         switch: switch@1f {
  81                 compatible = "mediatek,mt7531";
  82                 reg = <31>;
  83                 reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
  84                 interrupt-controller;
  85                 #interrupt-cells = <1>;
  86                 interrupt-parent = <&pio>;
  87                 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
  88         };
  89 };
  90
  91 &spi0 {
  92         pinctrl-names = "default";
  93         pinctrl-0 = <&spi0_flash_pins>;
  94         status = "okay";
  95
  96         spi_nand@0 {
  97                 compatible = "spi-nand";
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100                 reg = <0>;
 101
 102                 spi-max-frequency = <52000000>;
 103                 spi-tx-bus-width = <4>;
 104                 spi-rx-bus-width = <4>;
 105
 106                 mediatek,nmbm;
 107                 mediatek,bmt-max-ratio = <1>;
 108                 mediatek,bmt-max-reserved-blocks = <64>;
 109
 110                 partitions {
 111                         compatible = "fixed-partitions";
 112                         #address-cells = <1>;
 113                         #size-cells = <1>;
 114
 115                         partition@0 {
 116                                 label = "BL2";
 117                                 reg = <0x0000000 0x0100000>;
 118                                 read-only;
 119                         };
 120
 121                         partition@100000 {
 122                                 label = "u-boot-env";
 123                                 reg = <0x0100000 0x0080000>;
 124                         };
 125
 126                         partition@180000 {
 127                                 label = "art";
 128                                 reg = <0x0180000 0x0100000>;
 129                                 read-only;
 130
 131                                 compatible = "nvmem-cells";
 132                                 #address-cells = <1>;
 133                                 #size-cells = <1>;
 134
 135                                 macaddr_art_0: macaddr@0 {
 136                                         reg = <0x0 0x6>;
 137                                 };
 138                         };
 139
 140                         factory: partition@280000 {
 141                                 label = "Factory";
 142                                 reg = <0x0280000 0x0100000>;
 143                                 read-only;
 144                         };
 145
 146                         partition@380000 {
 147                                 label = "FIP";
 148                                 reg = <0x0380000 0x0200000>;
 149                                 read-only;
 150                         };
 151
 152                         partition@580000 {
 153                                 label = "ubi";
 154                                 reg = <0x0580000 0x2000000>;
 155                         };
 156
 157                         partition@2580000 {
 158                                 label = "ubi_backup";
 159                                 reg = <0x2580000 0x2000000>;
 160                         };
 161
 162                         partition@4580000 {
 163                                 label = "Config_backup";
 164                                 reg = <0x4580000 0x0400000>;
 165                         };
 166                 };
 167         };
 168 };
 169
 170 &switch {
 171         ports {
 172                 #address-cells = <1>;
 173                 #size-cells = <0>;
 174
 175                 port@0 {
 176                         reg = <0>;
 177                         label = "lan1";
 178                 };
 179
 180                 port@1 {
 181                         reg = <1>;
 182                         label = "lan2";
 183                 };
 184
 185                 port@2 {
 186                         reg = <2>;
 187                         label = "lan3";
 188                 };
 189
 190                 port@3 {
 191                         reg = <3>;
 192                         label = "wan";
 193                 };
 194
 195                 port@6 {
 196                         reg = <6>;
 197                         ethernet = <&gmac0>;
 198                         phy-mode = "2500base-x";
 199
 200                         fixed-link {
 201                                 speed = <2500>;
 202                                 full-duplex;
 203                                 pause;
 204                         };
 205                 };
 206         };
 207 };
 208
 209 &pio {
 210         spi0_flash_pins: spi0-pins {
 211                 mux {
 212                         function = "spi";
 213                         groups = "spi0", "spi0_wp_hold";
 214                 };
 215
 216                 conf-pu {
 217                         pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
 218                         drive-strength = <MTK_DRIVE_8mA>;
 219                         bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
 220                 };
 221
 222                 conf-pd {
 223                         pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
 224                         drive-strength = <MTK_DRIVE_8mA>;
 225                         bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
 226                 };
 227         };
 228 };
 229
 230 &uart0 {
 231         status = "okay";
 232 };
 233
 234 &watchdog {
 235         status = "okay";
 236 };
 237
 238 &wifi {
 239         status = "okay";
 240
 241         mediatek,mtd-eeprom = <&factory 0x0>;
 242 };