target/linux/mediatek/dts/mt7981b-cetron-ct3003.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 /dts-v1/;
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/leds/common.h>
   7
   8 #include "mt7981.dtsi"
   9
  10 / {
  11         model = "Cetron CT3003";
  12         compatible = "cetron,ct3003", "mediatek,mt7981";
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 label-mac-device = &gmac0;
  17                 led-boot = &led_status_red;
  18                 led-failsafe = &led_status_red;
  19                 led-running = &led_status_green;
  20                 led-upgrade = &led_status_green;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25         };
  26
  27         memory {
  28                 reg = <0 0x40000000 0 0x10000000>;
  29         };
  30
  31         gpio-keys {
  32                 compatible = "gpio-keys";
  33
  34                 reset {
  35                         label = "reset";
  36                         linux,code = <KEY_RESTART>;
  37                         gpios = <&pio 1 GPIO_ACTIVE_LOW>;
  38                 };
  39
  40                 wps {
  41                         label = "wps";
  42                         linux,code = <KEY_WPS_BUTTON>;
  43                         gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  44                 };
  45         };
  46
  47         leds {
  48                 compatible = "gpio-leds";
  49
  50                 led_status_red: led_status_red {
  51                         function = LED_FUNCTION_STATUS;
  52                         color = <LED_COLOR_ID_RED>;
  53                         gpios = <&pio 3 GPIO_ACTIVE_LOW>;
  54                 };
  55
  56                 led_status_green: led_status_green {
  57                         function = LED_FUNCTION_STATUS;
  58                         color = <LED_COLOR_ID_GREEN>;
  59                         gpios = <&pio 7 GPIO_ACTIVE_LOW>;
  60                 };
  61         };
  62 };
  63
  64 &eth {
  65         status = "okay";
  66
  67         gmac0: mac@0 {
  68                 compatible = "mediatek,eth-mac";
  69                 reg = <0>;
  70                 phy-mode = "2500base-x";
  71
  72                 nvmem-cells = <&macaddr_art_0 0>;
  73                 nvmem-cell-names = "mac-address";
  74
  75                 fixed-link {
  76                         speed = <2500>;
  77                         full-duplex;
  78                         pause;
  79                 };
  80         };
  81 };
  82
  83 &mdio_bus {
  84         switch: switch@1f {
  85                 compatible = "mediatek,mt7531";
  86                 reg = <31>;
  87                 reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
  88                 interrupt-controller;
  89                 #interrupt-cells = <1>;
  90                 interrupt-parent = <&pio>;
  91                 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
  92         };
  93 };
  94
  95 &spi0 {
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&spi0_flash_pins>;
  98         status = "okay";
  99
 100         spi_nand@0 {
 101                 compatible = "spi-nand";
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104                 reg = <0>;
 105
 106                 spi-max-frequency = <52000000>;
 107                 spi-tx-bus-width = <4>;
 108                 spi-rx-bus-width = <4>;
 109
 110                 mediatek,nmbm;
 111                 mediatek,bmt-max-ratio = <1>;
 112                 mediatek,bmt-max-reserved-blocks = <64>;
 113
 114                 partitions {
 115                         compatible = "fixed-partitions";
 116                         #address-cells = <1>;
 117                         #size-cells = <1>;
 118
 119                         partition@0 {
 120                                 label = "BL2";
 121                                 reg = <0x0000000 0x0100000>;
 122                                 read-only;
 123                         };
 124
 125                         partition@100000 {
 126                                 label = "u-boot-env";
 127                                 reg = <0x0100000 0x0080000>;
 128                         };
 129
 130                         partition@180000 {
 131                                 label = "art";
 132                                 reg = <0x0180000 0x0100000>;
 133                                 read-only;
 134
 135                                 nvmem-layout {
 136                                         compatible = "fixed-layout";
 137                                         #address-cells = <1>;
 138                                         #size-cells = <1>;
 139
 140                                         macaddr_art_0: macaddr@0 {
 141                                                 compatible = "mac-base";
 142                                                 reg = <0x0 0x6>;
 143                                                 #nvmem-cell-cells = <1>;
 144                                         };
 145                                 };
 146                         };
 147
 148                         factory: partition@280000 {
 149                                 label = "Factory";
 150                                 reg = <0x0280000 0x0100000>;
 151                                 read-only;
 152                         };
 153
 154                         partition@380000 {
 155                                 label = "FIP";
 156                                 reg = <0x0380000 0x0200000>;
 157                                 read-only;
 158                         };
 159
 160                         partition@580000 {
 161                                 label = "ubi";
 162                                 reg = <0x0580000 0x2000000>;
 163                         };
 164
 165                         partition@2580000 {
 166                                 label = "ubi_backup";
 167                                 reg = <0x2580000 0x2000000>;
 168                         };
 169
 170                         partition@4580000 {
 171                                 label = "Config_backup";
 172                                 reg = <0x4580000 0x0400000>;
 173                         };
 174                 };
 175         };
 176 };
 177
 178 &switch {
 179         ports {
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182
 183                 port@0 {
 184                         reg = <0>;
 185                         label = "lan1";
 186                 };
 187
 188                 port@1 {
 189                         reg = <1>;
 190                         label = "lan2";
 191                 };
 192
 193                 port@2 {
 194                         reg = <2>;
 195                         label = "lan3";
 196                 };
 197
 198                 port@3 {
 199                         reg = <3>;
 200                         label = "wan";
 201                         nvmem-cells = <&macaddr_art_0 3>;
 202                         nvmem-cell-names = "mac-address";
 203                 };
 204
 205                 port@6 {
 206                         reg = <6>;
 207                         ethernet = <&gmac0>;
 208                         phy-mode = "2500base-x";
 209
 210                         fixed-link {
 211                                 speed = <2500>;
 212                                 full-duplex;
 213                                 pause;
 214                         };
 215                 };
 216         };
 217 };
 218
 219 &pio {
 220         spi0_flash_pins: spi0-pins {
 221                 mux {
 222                         function = "spi";
 223                         groups = "spi0", "spi0_wp_hold";
 224                 };
 225
 226                 conf-pu {
 227                         pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
 228                         drive-strength = <MTK_DRIVE_8mA>;
 229                         bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
 230                 };
 231
 232                 conf-pd {
 233                         pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
 234                         drive-strength = <MTK_DRIVE_8mA>;
 235                         bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
 236                 };
 237         };
 238 };
 239
 240 &uart0 {
 241         status = "okay";
 242 };
 243
 244 &watchdog {
 245         status = "okay";
 246 };
 247
 248 &wifi {
 249         status = "okay";
 250
 251         mediatek,mtd-eeprom = <&factory 0x0>;
 252 };