target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts

   1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/leds/common.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 #include "mt7622.dtsi"
   9 #include "mt6380.dtsi"
  10
  11 / {
  12         model = "TOTOLINK A8000RU";
  13         compatible = "totolink,a8000ru", "mediatek,mt7622";
  14
  15         aliases {
  16                 label-mac-device = &gmac0;
  17                 led-boot = &led_status;
  18                 led-failsafe = &led_status;
  19                 led-running = &led_status;
  20                 led-upgrade = &led_status;
  21                 serial0 = &uart0;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  27         };
  28
  29         cpus {
  30                 cpu@0 {
  31                         proc-supply = <&mt6380_vcpu_reg>;
  32                         sram-supply = <&mt6380_vm_reg>;
  33                 };
  34
  35                 cpu@1 {
  36                         proc-supply = <&mt6380_vcpu_reg>;
  37                         sram-supply = <&mt6380_vm_reg>;
  38                 };
  39         };
  40
  41         gpio-keys {
  42                 compatible = "gpio-keys";
  43
  44                 reset {
  45                         label = "reset";
  46                         linux,code = <KEY_RESTART>;
  47                         gpios = <&pio 0 GPIO_ACTIVE_LOW>;
  48                 };
  49
  50                 wps {
  51                         label = "wps";
  52                         linux,code = <KEY_WPS_BUTTON>;
  53                         gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  54                 };
  55         };
  56
  57         gpio-leds {
  58                 compatible = "gpio-leds";
  59
  60                 led_status: status_red {
  61                         function = LED_FUNCTION_STATUS;
  62                         color = <LED_COLOR_ID_RED>;
  63                         gpios = <&pio 81 GPIO_ACTIVE_LOW>;
  64                         default-state = "on";
  65                 };
  66         };
  67
  68         reg_1p8v: regulator-1p8v {
  69                 compatible = "regulator-fixed";
  70                 regulator-name = "fixed-1.8V";
  71                 regulator-min-microvolt = <1800000>;
  72                 regulator-max-microvolt = <1800000>;
  73                 regulator-always-on;
  74         };
  75
  76         reg_3p3v: regulator-3p3v {
  77                 compatible = "regulator-fixed";
  78                 regulator-name = "fixed-3.3V";
  79                 regulator-min-microvolt = <3300000>;
  80                 regulator-max-microvolt = <3300000>;
  81                 regulator-boot-on;
  82                 regulator-always-on;
  83         };
  84
  85         reg_5v: regulator-5v {
  86                 compatible = "regulator-fixed";
  87                 regulator-name = "fixed-5V";
  88                 regulator-min-microvolt = <5000000>;
  89                 regulator-max-microvolt = <5000000>;
  90                 regulator-boot-on;
  91                 regulator-always-on;
  92         };
  93
  94         rtkgsw: rtkgsw@0 {
  95                 compatible = "mediatek,rtk-gsw";
  96                 mediatek,ethsys = <&ethsys>;
  97                 mediatek,mdio = <&mdio>;
  98                 mediatek,reset-pin = <&pio 54 0>;
  99                 status = "okay";
 100         };
 101 };
 102
 103 &pcie0 {
 104         pinctrl-names = "default";
 105         pinctrl-0 = <&pcie0_pins>;
 106         status = "okay";
 107 };
 108
 109 &slot0 {
 110         mt7615@0,0 {
 111                 reg = <0x0000 0 0 0 0>;
 112                 mediatek,mtd-eeprom = <&factory 0x5000>;
 113                 ieee80211-freq-limit = <5490000 6000000>;
 114         };
 115 };
 116
 117 &pcie1 {
 118         pinctrl-names = "default";
 119         pinctrl-0 = <&pcie1_pins>;
 120         status = "okay";
 121 };
 122
 123 &slot1 {
 124         mt7615@0,0 {
 125                 reg = <0x0000 0 0 0 0>;
 126                 mediatek,mtd-eeprom = <&factory 0x10000>;
 127                 ieee80211-freq-limit = <5000000 5490000>;
 128         };
 129 };
 130
 131 &pio {
 132         eth_pins: eth-pins {
 133                 mux {
 134                         function = "eth";
 135                         groups = "mdc_mdio", "rgmii_via_gmac2";
 136                 };
 137         };
 138
 139         pcie0_pins: pcie0-pins {
 140                 mux {
 141                         function = "pcie";
 142                         groups = "pcie0_pad_perst",
 143                                  "pcie0_1_waken",
 144                                  "pcie0_1_clkreq";
 145                 };
 146         };
 147
 148         pcie1_pins: pcie1-pins {
 149                 mux {
 150                         function = "pcie";
 151                         groups = "pcie1_pad_perst",
 152                                  "pcie1_0_waken",
 153                                  "pcie1_0_clkreq";
 154                 };
 155         };
 156
 157         pmic_bus_pins: pmic-bus-pins {
 158                 mux {
 159                         function = "pmic";
 160                         groups = "pmic_bus";
 161                 };
 162         };
 163
 164         /* serial NAND is shared pin with SPI-NOR */
 165         serial_nand_pins: serial-nand-pins {
 166                 mux {
 167                         function = "flash";
 168                         groups = "snfi";
 169                 };
 170         };
 171
 172         uart0_pins: uart0-pins {
 173                 mux {
 174                         function = "uart";
 175                         groups = "uart0_0_tx_rx" ;
 176                 };
 177         };
 178
 179         watchdog_pins: watchdog-pins {
 180                 mux {
 181                         function = "watchdog";
 182                         groups = "watchdog";
 183                 };
 184         };
 185
 186         epa_elna_pins: epa-elna-pins {
 187                 mux {
 188                         function = "antsel";
 189                         groups = "antsel0", "antsel1", "antsel2", "antsel3",
 190                                 "antsel4", "antsel5", "antsel6", "antsel7",
 191                                 "antsel8", "antsel9", "antsel12", "antsel13",
 192                                 "antsel14", "antsel15", "antsel16", "antsel17";
 193                 };
 194         };
 195 };
 196
 197 &eth {
 198         status = "okay";
 199         pinctrl-names = "default";
 200         pinctrl-0 = <&eth_pins>;
 201
 202         gmac0: mac@0 {
 203                 compatible = "mediatek,eth-mac";
 204                 reg = <0>;
 205                 nvmem-cells = <&macaddr_factory_2a>;
 206                 nvmem-cell-names = "mac-address";
 207                 phy-connection-type = "2500base-x";
 208                 fixed-link {
 209                         speed = <2500>;
 210                         full-duplex;
 211                         pause;
 212                 };
 213         };
 214
 215         gmac1: mac@1 {
 216                 compatible = "mediatek,eth-mac";
 217                 reg = <1>;
 218                 phy-mode = "rgmii";
 219                 nvmem-cells = <&macaddr_factory_24>;
 220                 nvmem-cell-names = "mac-address";
 221                 fixed-link {
 222                         speed = <1000>;
 223                         full-duplex;
 224                         pause;
 225                 };
 226         };
 227
 228         mdio: mdio-bus {
 229                 #address-cells = <1>;
 230                 #size-cells = <0>;
 231         };
 232 };
 233
 234 &pwrap {
 235         pinctrl-names = "default";
 236         pinctrl-0 = <&pmic_bus_pins>;
 237         status = "okay";
 238 };
 239
 240 &bch {
 241         status = "okay";
 242 };
 243
 244 &snfi {
 245         pinctrl-names = "default";
 246         pinctrl-0 = <&serial_nand_pins>;
 247         status = "okay";
 248         flash@0 {
 249                 compatible = "spi-nand";
 250                 reg = <0>;
 251                 spi-tx-bus-width = <4>;
 252                 spi-rx-bus-width = <4>;
 253                 nand-ecc-engine = <&snfi>;
 254                 mediatek,bmt-v2;
 255
 256                 partitions {
 257                         compatible = "fixed-partitions";
 258                         #address-cells = <1>;
 259                         #size-cells = <1>;
 260
 261                         partition@0 {
 262                                 label = "Preloader";
 263                                 reg = <0x0 0x80000>;
 264                                 read-only;
 265                         };
 266
 267                         partition@80000 {
 268                                 label = "ATF";
 269                                 reg = <0x80000 0x40000>;
 270                                 read-only;
 271                         };
 272
 273                         partition@c0000 {
 274                                 label = "u-boot";
 275                                 reg = <0xc0000 0x80000>;
 276                                 read-only;
 277                         };
 278
 279                         partition@140000 {
 280                                 label = "u-boot-env";
 281                                 reg = <0x140000 0x80000>;
 282                                 read-only;
 283                         };
 284
 285                         factory: partition@1c0000 {
 286                                 label = "factory";
 287                                 reg = <0x1c0000 0x40000>;
 288                                 read-only;
 289
 290                                 nvmem-layout {
 291                                         compatible = "fixed-layout";
 292                                         #address-cells = <1>;
 293                                         #size-cells = <1>;
 294
 295                                         macaddr_factory_24: macaddr@24 {
 296                                                 reg = <0x24 0x6>;
 297                                         };
 298
 299                                         macaddr_factory_2a: macaddr@2a {
 300                                                 reg = <0x2a 0x6>;
 301                                         };
 302                                 };
 303                         };
 304
 305                         partition@200000 {
 306                                 label = "ubi";
 307                                 reg = <0x200000 0x6400000>;
 308                         };
 309
 310                         partition@6600000 {
 311                                 label = "User_data";
 312                                 reg = <0x6600000 0x100000>;
 313                         };
 314
 315                         /* size of this partition varies due to BMT & bad blocks. */
 316                         partition@6700000 {
 317                                 label = "reserved";
 318                                 reg = <0x6700000 0>;
 319                         };
 320                 };
 321         };
 322 };
 323
 324 &ssusb {
 325         vusb33-supply = <&reg_3p3v>;
 326         vbus-supply = <&reg_5v>;
 327         status = "okay";
 328 };
 329
 330 &u3phy {
 331         status = "okay";
 332 };
 333
 334 &uart0 {
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&uart0_pins>;
 337         status = "okay";
 338 };
 339
 340 &watchdog {
 341         pinctrl-names = "default";
 342         pinctrl-0 = <&watchdog_pins>;
 343         status = "okay";
 344 };
 345
 346 &wmac {
 347         pinctrl-names = "default";
 348         pinctrl-0 = <&epa_elna_pins>;
 349         mediatek,mtd-eeprom = <&factory 0x0>;
 350         status = "okay";
 351 };