target/linux/lantiq/patches-3.7/0301-gptu.path

   1 Index: linux-3.7-rc8/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
   2 ===================================================================
   3 --- linux-3.7-rc8.orig/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h      2012-12-13 10:34:27.044276614 +0100
   4 +++ linux-3.7-rc8/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h   2012-12-13 10:41:34.332287326 +0100
   5 @@ -90,5 +90,8 @@
   6  extern void ltq_pmu_enable(unsigned int module);
   7  extern void ltq_pmu_disable(unsigned int module);
   8
   9 +/* allow tapi driver to read the gptu value */
  10 +long gptu_get_count(struct clk *clk);
  11 +
  12  #endif /* CONFIG_SOC_TYPE_XWAY */
  13  #endif /* _LTQ_XWAY_H__ */
  14 Index: linux-3.7-rc8/arch/mips/lantiq/xway/gptu.c
  15 ===================================================================
  16 --- linux-3.7-rc8.orig/arch/mips/lantiq/xway/gptu.c     2012-12-13 10:34:27.044276614 +0100
  17 +++ linux-3.7-rc8/arch/mips/lantiq/xway/gptu.c  2012-12-13 10:34:30.564276702 +0100
  18 @@ -105,8 +105,11 @@
  19         gptu_w32(CON_CNT | CON_EDGE_ANY | CON_SYNC | CON_CLK_INT,
  20                 GPTU_CON(clk->bits));
  21         gptu_w32(1, GPTU_RLD(clk->bits));
  22 -       gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN);
  23 +/*     gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN);*/
  24         gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits));
  25 +
  26 +       printk("%s:%s[%d]%X %X %X\n", __FILE__, __func__, __LINE__, gptu_r32(GPTU_CON(clk->bits)), gptu_r32(GPTU_RLD(clk->bits)), gptu_r32(GPTU_RUN(clk->bits)));
  27 +
  28         return 0;
  29  }
  30
  31 @@ -119,6 +122,12 @@
  32         free_irq(irqres[clk->bits].start, NULL);
  33  }
  34
  35 +long gptu_get_count(struct clk *clk)
  36 +{
  37 +       return gptu_r32(GPTU_CNT(clk->bits));
  38 +}
  39 +EXPORT_SYMBOL_GPL(gptu_get_count);
  40 +
  41  static inline void clkdev_add_gptu(struct device *dev, const char *con,
  42                                                         unsigned int timer)
  43  {
  44 Index: linux-3.7-rc8/arch/mips/lantiq/xway/timer.c
  45 ===================================================================
  46 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  47 +++ linux-3.7-rc8/arch/mips/lantiq/xway/timer.c 2012-12-13 10:41:16.360286872 +0100
  48 @@ -0,0 +1,841 @@
  49 +#include <linux/kernel.h>
  50 +#include <linux/module.h>
  51 +#include <linux/version.h>
  52 +#include <linux/types.h>
  53 +#include <linux/fs.h>
  54 +#include <linux/miscdevice.h>
  55 +#include <linux/init.h>
  56 +#include <linux/uaccess.h>
  57 +#include <linux/unistd.h>
  58 +#include <linux/errno.h>
  59 +#include <linux/interrupt.h>
  60 +#include <linux/sched.h>
  61 +
  62 +#include <asm/irq.h>
  63 +#include <asm/div64.h>
  64 +#include "../clk.h"
  65 +
  66 +#include <lantiq_soc.h>
  67 +#include <lantiq_irq.h>
  68 +#include <lantiq_timer.h>
  69 +
  70 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS  6
  71 +
  72 +#ifdef TIMER1A
  73 +#define FIRST_TIMER                    TIMER1A
  74 +#else
  75 +#define FIRST_TIMER                    2
  76 +#endif
  77 +
  78 +/*
  79 + *  GPTC divider is set or not.
  80 + */
  81 +#define GPTU_CLC_RMC_IS_SET            0
  82 +
  83 +/*
  84 + *  Timer Interrupt (IRQ)
  85 + */
  86 +/*  Must be adjusted when ICU driver is available */
  87 +#define TIMER_INTERRUPT                        (INT_NUM_IM3_IRL0 + 22)
  88 +
  89 +/*
  90 + *  Bits Operation
  91 + */
  92 +#define GET_BITS(x, msb, lsb)          \
  93 +       (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
  94 +#define SET_BITS(x, msb, lsb, value)   \
  95 +       (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
  96 +       (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
  97 +
  98 +/*
  99 + *  GPTU Register Mapping
 100 + */
 101 +#define LQ_GPTU                        (KSEG1 + 0x1E100A00)
 102 +#define LQ_GPTU_CLC            ((volatile u32 *)(LQ_GPTU + 0x0000))
 103 +#define LQ_GPTU_ID                     ((volatile u32 *)(LQ_GPTU + 0x0008))
 104 +#define LQ_GPTU_CON(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 105 +#define LQ_GPTU_RUN(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 106 +#define LQ_GPTU_RELOAD(n, X)   ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 107 +#define LQ_GPTU_COUNT(n, X)    ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 108 +#define LQ_GPTU_IRNEN          ((volatile u32 *)(LQ_GPTU + 0x00F4))
 109 +#define LQ_GPTU_IRNICR         ((volatile u32 *)(LQ_GPTU + 0x00F8))
 110 +#define LQ_GPTU_IRNCR          ((volatile u32 *)(LQ_GPTU + 0x00FC))
 111 +
 112 +/*
 113 + *  Clock Control Register
 114 + */
 115 +#define GPTU_CLC_SMC                   GET_BITS(*LQ_GPTU_CLC, 23, 16)
 116 +#define GPTU_CLC_RMC                   GET_BITS(*LQ_GPTU_CLC, 15, 8)
 117 +#define GPTU_CLC_FSOE                  (*LQ_GPTU_CLC & (1 << 5))
 118 +#define GPTU_CLC_EDIS                  (*LQ_GPTU_CLC & (1 << 3))
 119 +#define GPTU_CLC_SPEN                  (*LQ_GPTU_CLC & (1 << 2))
 120 +#define GPTU_CLC_DISS                  (*LQ_GPTU_CLC & (1 << 1))
 121 +#define GPTU_CLC_DISR                  (*LQ_GPTU_CLC & (1 << 0))
 122 +
 123 +#define GPTU_CLC_SMC_SET(value)                SET_BITS(0, 23, 16, (value))
 124 +#define GPTU_CLC_RMC_SET(value)                SET_BITS(0, 15, 8, (value))
 125 +#define GPTU_CLC_FSOE_SET(value)       ((value) ? (1 << 5) : 0)
 126 +#define GPTU_CLC_SBWE_SET(value)       ((value) ? (1 << 4) : 0)
 127 +#define GPTU_CLC_EDIS_SET(value)       ((value) ? (1 << 3) : 0)
 128 +#define GPTU_CLC_SPEN_SET(value)       ((value) ? (1 << 2) : 0)
 129 +#define GPTU_CLC_DISR_SET(value)       ((value) ? (1 << 0) : 0)
 130 +
 131 +/*
 132 + *  ID Register
 133 + */
 134 +#define GPTU_ID_ID                     GET_BITS(*LQ_GPTU_ID, 15, 8)
 135 +#define GPTU_ID_CFG                    GET_BITS(*LQ_GPTU_ID, 7, 5)
 136 +#define GPTU_ID_REV                    GET_BITS(*LQ_GPTU_ID, 4, 0)
 137 +
 138 +/*
 139 + *  Control Register of Timer/Counter nX
 140 + *    n is the index of block (1 based index)
 141 + *    X is either A or B
 142 + */
 143 +#define GPTU_CON_SRC_EG(n, X)          (*LQ_GPTU_CON(n, X) & (1 << 10))
 144 +#define GPTU_CON_SRC_EXT(n, X)         (*LQ_GPTU_CON(n, X) & (1 << 9))
 145 +#define GPTU_CON_SYNC(n, X)            (*LQ_GPTU_CON(n, X) & (1 << 8))
 146 +#define GPTU_CON_EDGE(n, X)            GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
 147 +#define GPTU_CON_INV(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 5))
 148 +#define GPTU_CON_EXT(n, X)             (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
 149 +#define GPTU_CON_STP(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 3))
 150 +#define GPTU_CON_CNT(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 2))
 151 +#define GPTU_CON_DIR(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 1))
 152 +#define GPTU_CON_EN(n, X)              (*LQ_GPTU_CON(n, X) & (1 << 0))
 153 +
 154 +#define GPTU_CON_SRC_EG_SET(value)     ((value) ? 0 : (1 << 10))
 155 +#define GPTU_CON_SRC_EXT_SET(value)    ((value) ? (1 << 9) : 0)
 156 +#define GPTU_CON_SYNC_SET(value)       ((value) ? (1 << 8) : 0)
 157 +#define GPTU_CON_EDGE_SET(value)       SET_BITS(0, 7, 6, (value))
 158 +#define GPTU_CON_INV_SET(value)                ((value) ? (1 << 5) : 0)
 159 +#define GPTU_CON_EXT_SET(value)                ((value) ? (1 << 4) : 0)
 160 +#define GPTU_CON_STP_SET(value)                ((value) ? (1 << 3) : 0)
 161 +#define GPTU_CON_CNT_SET(value)                ((value) ? (1 << 2) : 0)
 162 +#define GPTU_CON_DIR_SET(value)                ((value) ? (1 << 1) : 0)
 163 +
 164 +#define GPTU_RUN_RL_SET(value)         ((value) ? (1 << 2) : 0)
 165 +#define GPTU_RUN_CEN_SET(value)                ((value) ? (1 << 1) : 0)
 166 +#define GPTU_RUN_SEN_SET(value)                ((value) ? (1 << 0) : 0)
 167 +
 168 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 169 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 170 +
 171 +#define TIMER_FLAG_MASK_SIZE(x)                (x & 0x0001)
 172 +#define TIMER_FLAG_MASK_TYPE(x)                (x & 0x0002)
 173 +#define TIMER_FLAG_MASK_STOP(x)                (x & 0x0004)
 174 +#define TIMER_FLAG_MASK_DIR(x)         (x & 0x0008)
 175 +#define TIMER_FLAG_NONE_EDGE           0x0000
 176 +#define TIMER_FLAG_MASK_EDGE(x)                (x & 0x0030)
 177 +#define TIMER_FLAG_REAL                        0x0000
 178 +#define TIMER_FLAG_INVERT              0x0040
 179 +#define TIMER_FLAG_MASK_INVERT(x)      (x & 0x0040)
 180 +#define TIMER_FLAG_MASK_TRIGGER(x)     (x & 0x0070)
 181 +#define TIMER_FLAG_MASK_SYNC(x)                (x & 0x0080)
 182 +#define TIMER_FLAG_CALLBACK_IN_HB      0x0200
 183 +#define TIMER_FLAG_MASK_HANDLE(x)      (x & 0x0300)
 184 +#define TIMER_FLAG_MASK_SRC(x)         (x & 0x1000)
 185 +
 186 +struct timer_dev_timer {
 187 +       unsigned int f_irq_on;
 188 +       unsigned int irq;
 189 +       unsigned int flag;
 190 +       unsigned long arg1;
 191 +       unsigned long arg2;
 192 +};
 193 +
 194 +struct timer_dev {
 195 +       struct mutex gptu_mutex;
 196 +       unsigned int number_of_timers;
 197 +       unsigned int occupation;
 198 +       unsigned int f_gptu_on;
 199 +       struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
 200 +};
 201 +
 202 +
 203 +unsigned int ltq_get_fpi_bus_clock(int fpi) {
 204 +       struct clk *clk = clk_get_fpi();
 205 +       return clk_get_rate(clk);
 206 +}
 207 +
 208 +
 209 +static long gptu_ioctl(struct file *, unsigned int, unsigned long);
 210 +static int gptu_open(struct inode *, struct file *);
 211 +static int gptu_release(struct inode *, struct file *);
 212 +
 213 +static struct file_operations gptu_fops = {
 214 +       .owner = THIS_MODULE,
 215 +       .unlocked_ioctl = gptu_ioctl,
 216 +       .open = gptu_open,
 217 +       .release = gptu_release
 218 +};
 219 +
 220 +static struct miscdevice gptu_miscdev = {
 221 +       .minor = MISC_DYNAMIC_MINOR,
 222 +       .name = "gptu",
 223 +       .fops = &gptu_fops,
 224 +};
 225 +
 226 +static struct timer_dev timer_dev;
 227 +
 228 +static irqreturn_t timer_irq_handler(int irq, void *p)
 229 +{
 230 +       unsigned int timer;
 231 +       unsigned int flag;
 232 +       struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
 233 +
 234 +       timer = irq - TIMER_INTERRUPT;
 235 +       if (timer < timer_dev.number_of_timers
 236 +               && dev_timer == &timer_dev.timer[timer]) {
 237 +               /*  Clear interrupt.    */
 238 +               ltq_w32(1 << timer, LQ_GPTU_IRNCR);
 239 +
 240 +               /*  Call user hanler or signal. */
 241 +               flag = dev_timer->flag;
 242 +               if (!(timer & 0x01)
 243 +                       || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 244 +                       /* 16-bit timer or timer A of 32-bit timer  */
 245 +                       switch (TIMER_FLAG_MASK_HANDLE(flag)) {
 246 +                       case TIMER_FLAG_CALLBACK_IN_IRQ:
 247 +                       case TIMER_FLAG_CALLBACK_IN_HB:
 248 +                               if (dev_timer->arg1)
 249 +                                       (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
 250 +                               break;
 251 +                       case TIMER_FLAG_SIGNAL:
 252 +                               send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
 253 +                               break;
 254 +                       }
 255 +               }
 256 +       }
 257 +       return IRQ_HANDLED;
 258 +}
 259 +
 260 +static inline void lq_enable_gptu(void)
 261 +{
 262 +       struct clk *clk = clk_get_sys("ltq_gptu", NULL);
 263 +       clk_enable(clk);
 264 +
 265 +       //ltq_pmu_enable(PMU_GPT);
 266 +
 267 +       /*  Set divider as 1, disable write protection for SPEN, enable module. */
 268 +       *LQ_GPTU_CLC =
 269 +               GPTU_CLC_SMC_SET(0x00) |
 270 +               GPTU_CLC_RMC_SET(0x01) |
 271 +               GPTU_CLC_FSOE_SET(0) |
 272 +               GPTU_CLC_SBWE_SET(1) |
 273 +               GPTU_CLC_EDIS_SET(0) |
 274 +               GPTU_CLC_SPEN_SET(0) |
 275 +               GPTU_CLC_DISR_SET(0);
 276 +}
 277 +
 278 +static inline void lq_disable_gptu(void)
 279 +{
 280 +       struct clk *clk = clk_get_sys("ltq_gptu", NULL);
 281 +       ltq_w32(0x00, LQ_GPTU_IRNEN);
 282 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 283 +
 284 +       /*  Set divider as 0, enable write protection for SPEN, disable module. */
 285 +       *LQ_GPTU_CLC =
 286 +               GPTU_CLC_SMC_SET(0x00) |
 287 +               GPTU_CLC_RMC_SET(0x00) |
 288 +               GPTU_CLC_FSOE_SET(0) |
 289 +               GPTU_CLC_SBWE_SET(0) |
 290 +               GPTU_CLC_EDIS_SET(0) |
 291 +               GPTU_CLC_SPEN_SET(0) |
 292 +               GPTU_CLC_DISR_SET(1);
 293 +
 294 +       clk_enable(clk);
 295 +}
 296 +
 297 +int lq_request_timer(unsigned int timer, unsigned int flag,
 298 +       unsigned long value, unsigned long arg1, unsigned long arg2)
 299 +{
 300 +       int ret = 0;
 301 +       unsigned int con_reg, irnen_reg;
 302 +       int n, X;
 303 +
 304 +       if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
 305 +               return -EINVAL;
 306 +
 307 +       printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
 308 +               timer, flag, value);
 309 +
 310 +       if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
 311 +               value &= 0xFFFF;
 312 +       else
 313 +               timer &= ~0x01;
 314 +
 315 +       mutex_lock(&timer_dev.gptu_mutex);
 316 +
 317 +       /*
 318 +        *  Allocate timer.
 319 +        */
 320 +       if (timer < FIRST_TIMER) {
 321 +               unsigned int mask;
 322 +               unsigned int shift;
 323 +               /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
 324 +               unsigned int offset = TIMER2A;
 325 +
 326 +               /*
 327 +                *  Pick up a free timer.
 328 +                */
 329 +               if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 330 +                       mask = 1 << offset;
 331 +                       shift = 1;
 332 +               } else {
 333 +                       mask = 3 << offset;
 334 +                       shift = 2;
 335 +               }
 336 +               for (timer = offset;
 337 +                    timer < offset + timer_dev.number_of_timers;
 338 +                    timer += shift, mask <<= shift)
 339 +                       if (!(timer_dev.occupation & mask)) {
 340 +                               timer_dev.occupation |= mask;
 341 +                               break;
 342 +                       }
 343 +               if (timer >= offset + timer_dev.number_of_timers) {
 344 +                       printk("failed![%d]\n", __LINE__);
 345 +                       mutex_unlock(&timer_dev.gptu_mutex);
 346 +                       return -EINVAL;
 347 +               } else
 348 +                       ret = timer;
 349 +       } else {
 350 +               register unsigned int mask;
 351 +
 352 +               /*
 353 +                *  Check if the requested timer is free.
 354 +                */
 355 +               mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 356 +               if ((timer_dev.occupation & mask)) {
 357 +                       printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
 358 +                               __LINE__, mask, timer_dev.occupation);
 359 +                       mutex_unlock(&timer_dev.gptu_mutex);
 360 +                       return -EBUSY;
 361 +               } else {
 362 +                       timer_dev.occupation |= mask;
 363 +                       ret = 0;
 364 +               }
 365 +       }
 366 +
 367 +       /*
 368 +        *  Prepare control register value.
 369 +        */
 370 +       switch (TIMER_FLAG_MASK_EDGE(flag)) {
 371 +       default:
 372 +       case TIMER_FLAG_NONE_EDGE:
 373 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 374 +               break;
 375 +       case TIMER_FLAG_RISE_EDGE:
 376 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 377 +               break;
 378 +       case TIMER_FLAG_FALL_EDGE:
 379 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 380 +               break;
 381 +       case TIMER_FLAG_ANY_EDGE:
 382 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 383 +               break;
 384 +       }
 385 +       if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
 386 +               con_reg |=
 387 +                       TIMER_FLAG_MASK_SRC(flag) ==
 388 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
 389 +                       GPTU_CON_SRC_EXT_SET(0);
 390 +       else
 391 +               con_reg |=
 392 +                       TIMER_FLAG_MASK_SRC(flag) ==
 393 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
 394 +                       GPTU_CON_SRC_EG_SET(0);
 395 +       con_reg |=
 396 +               TIMER_FLAG_MASK_SYNC(flag) ==
 397 +               TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
 398 +               GPTU_CON_SYNC_SET(1);
 399 +       con_reg |=
 400 +               TIMER_FLAG_MASK_INVERT(flag) ==
 401 +               TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 402 +       con_reg |=
 403 +               TIMER_FLAG_MASK_SIZE(flag) ==
 404 +               TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
 405 +               GPTU_CON_EXT_SET(1);
 406 +       con_reg |=
 407 +               TIMER_FLAG_MASK_STOP(flag) ==
 408 +               TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 409 +       con_reg |=
 410 +               TIMER_FLAG_MASK_TYPE(flag) ==
 411 +               TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
 412 +               GPTU_CON_CNT_SET(1);
 413 +       con_reg |=
 414 +               TIMER_FLAG_MASK_DIR(flag) ==
 415 +               TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 416 +
 417 +       /*
 418 +        *  Fill up running data.
 419 +        */
 420 +       timer_dev.timer[timer - FIRST_TIMER].flag = flag;
 421 +       timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
 422 +       timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
 423 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 424 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
 425 +
 426 +       /*
 427 +        *  Enable GPTU module.
 428 +        */
 429 +       if (!timer_dev.f_gptu_on) {
 430 +               lq_enable_gptu();
 431 +               timer_dev.f_gptu_on = 1;
 432 +       }
 433 +
 434 +       /*
 435 +        *  Enable IRQ.
 436 +        */
 437 +       if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
 438 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
 439 +                       timer_dev.timer[timer - FIRST_TIMER].arg1 =
 440 +                               (unsigned long) find_task_by_vpid((int) arg1);
 441 +
 442 +               irnen_reg = 1 << (timer - FIRST_TIMER);
 443 +
 444 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
 445 +                   || (TIMER_FLAG_MASK_HANDLE(flag) ==
 446 +                       TIMER_FLAG_CALLBACK_IN_IRQ
 447 +                       && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
 448 +                       enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 449 +                       timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
 450 +               }
 451 +       } else
 452 +               irnen_reg = 0;
 453 +
 454 +       /*
 455 +        *  Write config register, reload value and enable interrupt.
 456 +        */
 457 +       n = timer >> 1;
 458 +       X = timer & 0x01;
 459 +       *LQ_GPTU_CON(n, X) = con_reg;
 460 +       *LQ_GPTU_RELOAD(n, X) = value;
 461 +       /* printk("reload value = %d\n", (u32)value); */
 462 +       *LQ_GPTU_IRNEN |= irnen_reg;
 463 +
 464 +       mutex_unlock(&timer_dev.gptu_mutex);
 465 +       printk("successful!\n");
 466 +       return ret;
 467 +}
 468 +EXPORT_SYMBOL(lq_request_timer);
 469 +
 470 +int lq_free_timer(unsigned int timer)
 471 +{
 472 +       unsigned int flag;
 473 +       unsigned int mask;
 474 +       int n, X;
 475 +
 476 +       if (!timer_dev.f_gptu_on)
 477 +               return -EINVAL;
 478 +
 479 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 480 +               return -EINVAL;
 481 +
 482 +       mutex_lock(&timer_dev.gptu_mutex);
 483 +
 484 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 485 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 486 +               timer &= ~0x01;
 487 +
 488 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 489 +       if (((timer_dev.occupation & mask) ^ mask)) {
 490 +               mutex_unlock(&timer_dev.gptu_mutex);
 491 +               return -EINVAL;
 492 +       }
 493 +
 494 +       n = timer >> 1;
 495 +       X = timer & 0x01;
 496 +
 497 +       if (GPTU_CON_EN(n, X))
 498 +               *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 499 +
 500 +       *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
 501 +       *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
 502 +
 503 +       if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
 504 +               disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 505 +               timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
 506 +       }
 507 +
 508 +       timer_dev.occupation &= ~mask;
 509 +       if (!timer_dev.occupation && timer_dev.f_gptu_on) {
 510 +               lq_disable_gptu();
 511 +               timer_dev.f_gptu_on = 0;
 512 +       }
 513 +
 514 +       mutex_unlock(&timer_dev.gptu_mutex);
 515 +
 516 +       return 0;
 517 +}
 518 +EXPORT_SYMBOL(lq_free_timer);
 519 +
 520 +int lq_start_timer(unsigned int timer, int is_resume)
 521 +{
 522 +       unsigned int flag;
 523 +       unsigned int mask;
 524 +       int n, X;
 525 +
 526 +       if (!timer_dev.f_gptu_on)
 527 +               return -EINVAL;
 528 +
 529 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 530 +               return -EINVAL;
 531 +
 532 +       mutex_lock(&timer_dev.gptu_mutex);
 533 +
 534 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 535 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 536 +               timer &= ~0x01;
 537 +
 538 +       mask = (TIMER_FLAG_MASK_SIZE(flag) ==
 539 +       TIMER_FLAG_16BIT ? 1 : 3) << timer;
 540 +       if (((timer_dev.occupation & mask) ^ mask)) {
 541 +               mutex_unlock(&timer_dev.gptu_mutex);
 542 +               return -EINVAL;
 543 +       }
 544 +
 545 +       n = timer >> 1;
 546 +       X = timer & 0x01;
 547 +
 548 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
 549 +
 550 +
 551 +       mutex_unlock(&timer_dev.gptu_mutex);
 552 +
 553 +       return 0;
 554 +}
 555 +EXPORT_SYMBOL(lq_start_timer);
 556 +
 557 +int lq_stop_timer(unsigned int timer)
 558 +{
 559 +       unsigned int flag;
 560 +       unsigned int mask;
 561 +       int n, X;
 562 +
 563 +       if (!timer_dev.f_gptu_on)
 564 +               return -EINVAL;
 565 +
 566 +       if (timer < FIRST_TIMER
 567 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 568 +               return -EINVAL;
 569 +
 570 +       mutex_lock(&timer_dev.gptu_mutex);
 571 +
 572 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 573 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 574 +               timer &= ~0x01;
 575 +
 576 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 577 +       if (((timer_dev.occupation & mask) ^ mask)) {
 578 +               mutex_unlock(&timer_dev.gptu_mutex);
 579 +               return -EINVAL;
 580 +       }
 581 +
 582 +       n = timer >> 1;
 583 +       X = timer & 0x01;
 584 +
 585 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 586 +
 587 +       mutex_unlock(&timer_dev.gptu_mutex);
 588 +
 589 +       return 0;
 590 +}
 591 +EXPORT_SYMBOL(lq_stop_timer);
 592 +
 593 +int lq_reset_counter_flags(u32 timer, u32 flags)
 594 +{
 595 +       unsigned int oflag;
 596 +       unsigned int mask, con_reg;
 597 +       int n, X;
 598 +
 599 +       if (!timer_dev.f_gptu_on)
 600 +               return -EINVAL;
 601 +
 602 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 603 +               return -EINVAL;
 604 +
 605 +       mutex_lock(&timer_dev.gptu_mutex);
 606 +
 607 +       oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
 608 +       if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
 609 +               timer &= ~0x01;
 610 +
 611 +       mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 612 +       if (((timer_dev.occupation & mask) ^ mask)) {
 613 +               mutex_unlock(&timer_dev.gptu_mutex);
 614 +               return -EINVAL;
 615 +       }
 616 +
 617 +       switch (TIMER_FLAG_MASK_EDGE(flags)) {
 618 +       default:
 619 +       case TIMER_FLAG_NONE_EDGE:
 620 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 621 +               break;
 622 +       case TIMER_FLAG_RISE_EDGE:
 623 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 624 +               break;
 625 +       case TIMER_FLAG_FALL_EDGE:
 626 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 627 +               break;
 628 +       case TIMER_FLAG_ANY_EDGE:
 629 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 630 +               break;
 631 +       }
 632 +       if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
 633 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
 634 +       else
 635 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
 636 +       con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
 637 +       con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 638 +       con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
 639 +       con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 640 +       con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
 641 +       con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 642 +
 643 +       timer_dev.timer[timer - FIRST_TIMER].flag = flags;
 644 +       if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
 645 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
 646 +
 647 +       n = timer >> 1;
 648 +       X = timer & 0x01;
 649 +
 650 +       *LQ_GPTU_CON(n, X) = con_reg;
 651 +       smp_wmb();
 652 +       mutex_unlock(&timer_dev.gptu_mutex);
 653 +       return 0;
 654 +}
 655 +EXPORT_SYMBOL(lq_reset_counter_flags);
 656 +
 657 +int lq_get_count_value(unsigned int timer, unsigned long *value)
 658 +{
 659 +       unsigned int flag;
 660 +       unsigned int mask;
 661 +       int n, X;
 662 +
 663 +       if (!timer_dev.f_gptu_on)
 664 +               return -EINVAL;
 665 +
 666 +       if (timer < FIRST_TIMER
 667 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 668 +               return -EINVAL;
 669 +
 670 +       mutex_lock(&timer_dev.gptu_mutex);
 671 +
 672 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 673 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 674 +               timer &= ~0x01;
 675 +
 676 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 677 +       if (((timer_dev.occupation & mask) ^ mask)) {
 678 +               mutex_unlock(&timer_dev.gptu_mutex);
 679 +               return -EINVAL;
 680 +       }
 681 +
 682 +       n = timer >> 1;
 683 +       X = timer & 0x01;
 684 +
 685 +       *value = *LQ_GPTU_COUNT(n, X);
 686 +
 687 +
 688 +       mutex_unlock(&timer_dev.gptu_mutex);
 689 +
 690 +       return 0;
 691 +}
 692 +EXPORT_SYMBOL(lq_get_count_value);
 693 +
 694 +u32 lq_cal_divider(unsigned long freq)
 695 +{
 696 +       u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
 697 +       u32 clock_divider = 1;
 698 +       module_freq = fpi * 1000;
 699 +       do_div(module_freq, clock_divider * freq);
 700 +       return module_freq;
 701 +}
 702 +EXPORT_SYMBOL(lq_cal_divider);
 703 +
 704 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
 705 +       int is_ext_src, unsigned int handle_flag, unsigned long arg1,
 706 +       unsigned long arg2)
 707 +{
 708 +       unsigned long divider;
 709 +       unsigned int flag;
 710 +
 711 +       divider = lq_cal_divider(freq);
 712 +       if (divider == 0)
 713 +               return -EINVAL;
 714 +       flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
 715 +               | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
 716 +               | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
 717 +               | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
 718 +               | TIMER_FLAG_MASK_HANDLE(handle_flag);
 719 +
 720 +       printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
 721 +               timer, freq, divider);
 722 +       return lq_request_timer(timer, flag, divider, arg1, arg2);
 723 +}
 724 +EXPORT_SYMBOL(lq_set_timer);
 725 +
 726 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
 727 +       unsigned long arg1, unsigned long arg2)
 728 +{
 729 +       printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
 730 +       return lq_request_timer(timer, flag, reload, arg1, arg2);
 731 +}
 732 +EXPORT_SYMBOL(lq_set_counter);
 733 +
 734 +static long gptu_ioctl(struct file *file, unsigned int cmd,
 735 +       unsigned long arg)
 736 +{
 737 +       int ret;
 738 +       struct gptu_ioctl_param param;
 739 +
 740 +       if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
 741 +               return -EFAULT;
 742 +       copy_from_user(&param, (void *) arg, sizeof(param));
 743 +
 744 +       if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
 745 +              || GPTU_SET_COUNTER) && param.timer < 2)
 746 +            || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
 747 +           && !access_ok(VERIFY_WRITE, arg,
 748 +                          sizeof(struct gptu_ioctl_param)))
 749 +               return -EFAULT;
 750 +
 751 +       switch (cmd) {
 752 +       case GPTU_REQUEST_TIMER:
 753 +               ret = lq_request_timer(param.timer, param.flag, param.value,
 754 +                                    (unsigned long) param.pid,
 755 +                                    (unsigned long) param.sig);
 756 +               if (ret > 0) {
 757 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 758 +                                     timer, &ret, sizeof(&ret));
 759 +                       ret = 0;
 760 +               }
 761 +               break;
 762 +       case GPTU_FREE_TIMER:
 763 +               ret = lq_free_timer(param.timer);
 764 +               break;
 765 +       case GPTU_START_TIMER:
 766 +               ret = lq_start_timer(param.timer, param.flag);
 767 +               break;
 768 +       case GPTU_STOP_TIMER:
 769 +               ret = lq_stop_timer(param.timer);
 770 +               break;
 771 +       case GPTU_GET_COUNT_VALUE:
 772 +               ret = lq_get_count_value(param.timer, &param.value);
 773 +               if (!ret)
 774 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 775 +                                     value, &param.value,
 776 +                                     sizeof(param.value));
 777 +               break;
 778 +       case GPTU_CALCULATE_DIVIDER:
 779 +               param.value = lq_cal_divider(param.value);
 780 +               if (param.value == 0)
 781 +                       ret = -EINVAL;
 782 +               else {
 783 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 784 +                                     value, &param.value,
 785 +                                     sizeof(param.value));
 786 +                       ret = 0;
 787 +               }
 788 +               break;
 789 +       case GPTU_SET_TIMER:
 790 +               ret = lq_set_timer(param.timer, param.value,
 791 +                                TIMER_FLAG_MASK_STOP(param.flag) !=
 792 +                                TIMER_FLAG_ONCE ? 1 : 0,
 793 +                                TIMER_FLAG_MASK_SRC(param.flag) ==
 794 +                                TIMER_FLAG_EXT_SRC ? 1 : 0,
 795 +                                TIMER_FLAG_MASK_HANDLE(param.flag) ==
 796 +                                TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
 797 +                                TIMER_FLAG_NO_HANDLE,
 798 +                                (unsigned long) param.pid,
 799 +                                (unsigned long) param.sig);
 800 +               if (ret > 0) {
 801 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 802 +                                     timer, &ret, sizeof(&ret));
 803 +                       ret = 0;
 804 +               }
 805 +               break;
 806 +       case GPTU_SET_COUNTER:
 807 +               lq_set_counter(param.timer, param.flag, param.value, 0, 0);
 808 +               if (ret > 0) {
 809 +                       copy_to_user(&((struct gptu_ioctl_param *) arg)->
 810 +                                     timer, &ret, sizeof(&ret));
 811 +                       ret = 0;
 812 +               }
 813 +               break;
 814 +       default:
 815 +               ret = -ENOTTY;
 816 +       }
 817 +
 818 +       return ret;
 819 +}
 820 +
 821 +static int gptu_open(struct inode *inode, struct file *file)
 822 +{
 823 +       return 0;
 824 +}
 825 +
 826 +static int gptu_release(struct inode *inode, struct file *file)
 827 +{
 828 +       return 0;
 829 +}
 830 +
 831 +int __init lq_gptu_init(void)
 832 +{
 833 +       int ret;
 834 +       unsigned int i;
 835 +
 836 +       ltq_w32(0, LQ_GPTU_IRNEN);
 837 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 838 +
 839 +       memset(&timer_dev, 0, sizeof(timer_dev));
 840 +       mutex_init(&timer_dev.gptu_mutex);
 841 +
 842 +       lq_enable_gptu();
 843 +       timer_dev.number_of_timers = GPTU_ID_CFG * 2;
 844 +       lq_disable_gptu();
 845 +       if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
 846 +               timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
 847 +       printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
 848 +
 849 +       ret = misc_register(&gptu_miscdev);
 850 +       if (ret) {
 851 +               printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
 852 +               return ret;
 853 +       } else {
 854 +               printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
 855 +       }
 856 +
 857 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
 858 +               ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
 859 +               if (ret) {
 860 +                       for (; i >= 0; i--)
 861 +                               free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
 862 +                       misc_deregister(&gptu_miscdev);
 863 +                       printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
 864 +                       return ret;
 865 +               } else {
 866 +                       timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
 867 +                       disable_irq(timer_dev.timer[i].irq);
 868 +                       printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
 869 +               }
 870 +       }
 871 +
 872 +       return 0;
 873 +}
 874 +
 875 +void __exit lq_gptu_exit(void)
 876 +{
 877 +       unsigned int i;
 878 +
 879 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
 880 +               if (timer_dev.timer[i].f_irq_on)
 881 +                       disable_irq(timer_dev.timer[i].irq);
 882 +               free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
 883 +       }
 884 +       lq_disable_gptu();
 885 +       misc_deregister(&gptu_miscdev);
 886 +}
 887 +
 888 +module_init(lq_gptu_init);
 889 +module_exit(lq_gptu_exit);
 890 Index: linux-3.7-rc8/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
 891 ===================================================================
 892 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 893 +++ linux-3.7-rc8/arch/mips/include/asm/mach-lantiq/lantiq_timer.h      2012-12-13 10:34:30.564276702 +0100
 894 @@ -0,0 +1,155 @@
 895 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
 896 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
 897 +
 898 +
 899 +/******************************************************************************
 900 +       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
 901 +
 902 +                               No Warranty
 903 +   Because the program is licensed free of charge, there is no warranty for
 904 +   the program, to the extent permitted by applicable law.  Except when
 905 +   otherwise stated in writing the copyright holders and/or other parties
 906 +   provide the program "as is" without warranty of any kind, either
 907 +   expressed or implied, including, but not limited to, the implied
 908 +   warranties of merchantability and fitness for a particular purpose. The
 909 +   entire risk as to the quality and performance of the program is with
 910 +   you.  should the program prove defective, you assume the cost of all
 911 +   necessary servicing, repair or correction.
 912 +
 913 +   In no event unless required by applicable law or agreed to in writing
 914 +   will any copyright holder, or any other party who may modify and/or
 915 +   redistribute the program as permitted above, be liable to you for
 916 +   damages, including any general, special, incidental or consequential
 917 +   damages arising out of the use or inability to use the program
 918 +   (including but not limited to loss of data or data being rendered
 919 +   inaccurate or losses sustained by you or third parties or a failure of
 920 +   the program to operate with any other programs), even if such holder or
 921 +   other party has been advised of the possibility of such damages.
 922 +******************************************************************************/
 923 +
 924 +
 925 +/*
 926 + * ####################################
 927 + *              Definition
 928 + * ####################################
 929 + */
 930 +
 931 +/*
 932 + *  Available Timer/Counter Index
 933 + */
 934 +#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
 935 +#define TIMER_ANY                       0x00
 936 +#define TIMER1A                         TIMER(1, 0)
 937 +#define TIMER1B                         TIMER(1, 1)
 938 +#define TIMER2A                         TIMER(2, 0)
 939 +#define TIMER2B                         TIMER(2, 1)
 940 +#define TIMER3A                         TIMER(3, 0)
 941 +#define TIMER3B                         TIMER(3, 1)
 942 +
 943 +/*
 944 + *  Flag of Timer/Counter
 945 + *  These flags specify the way in which timer is configured.
 946 + */
 947 +/*  Bit size of timer/counter.                      */
 948 +#define TIMER_FLAG_16BIT                0x0000
 949 +#define TIMER_FLAG_32BIT                0x0001
 950 +/*  Switch between timer and counter.               */
 951 +#define TIMER_FLAG_TIMER                0x0000
 952 +#define TIMER_FLAG_COUNTER              0x0002
 953 +/*  Stop or continue when overflowing/underflowing. */
 954 +#define TIMER_FLAG_ONCE                 0x0000
 955 +#define TIMER_FLAG_CYCLIC               0x0004
 956 +/*  Count up or counter down.                       */
 957 +#define TIMER_FLAG_UP                   0x0000
 958 +#define TIMER_FLAG_DOWN                 0x0008
 959 +/*  Count on specific level or edge.                */
 960 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
 961 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
 962 +#define TIMER_FLAG_RISE_EDGE            0x0010
 963 +#define TIMER_FLAG_FALL_EDGE            0x0020
 964 +#define TIMER_FLAG_ANY_EDGE             0x0030
 965 +/*  Signal is syncronous to module clock or not.    */
 966 +#define TIMER_FLAG_UNSYNC               0x0000
 967 +#define TIMER_FLAG_SYNC                 0x0080
 968 +/*  Different interrupt handle type.                */
 969 +#define TIMER_FLAG_NO_HANDLE            0x0000
 970 +#if defined(__KERNEL__)
 971 +    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
 972 +#endif  //  defined(__KERNEL__)
 973 +#define TIMER_FLAG_SIGNAL               0x0300
 974 +/*  Internal clock source or external clock source  */
 975 +#define TIMER_FLAG_INT_SRC              0x0000
 976 +#define TIMER_FLAG_EXT_SRC              0x1000
 977 +
 978 +
 979 +/*
 980 + *  ioctl Command
 981 + */
 982 +#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
 983 +#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
 984 +#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
 985 +#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
 986 +#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
 987 +#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
 988 +#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
 989 +#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
 990 +
 991 +/*
 992 + *  Data Type Used to Call ioctl
 993 + */
 994 +struct gptu_ioctl_param {
 995 +    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 996 +                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
 997 +                                                 *  timer/counter. If it's zero, a timer/counter would  *
 998 +                                                 *  be dynamically allocated and ID would be stored in  *
 999 +                                                 *  this field.                                         *
1000 +                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
1001 +                                                 *  ignored.                                            *
1002 +                                                 *  In other command, this field is ID of timer/counter *
1003 +                                                 *  allocated.                                          */
1004 +    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
1005 +                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
1006 +                                                 *  specify how to configure timer/counter.             *
1007 +                                                 *  In command GPTU_START_TIMER, zero indicate start    *
1008 +                                                 *  and non-zero indicate resume timer/counter.         *
1009 +                                                 *  In other command, this field is ignored.            */
1010 +    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
1011 +                                                 *  init/reload value.                                  *
1012 +                                                 *  In command GPTU_SET_TIMER, this field contains      *
1013 +                                                 *  frequency (0.001Hz) of timer.                       *
1014 +                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
1015 +                                                 *  value would be stored in this field.                *
1016 +                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
1017 +                                                 *  contains frequency wanted, and after calculation,   *
1018 +                                                 *  divider would be stored in this field to overwrite  *
1019 +                                                 *  the frequency.                                      *
1020 +                                                 *  In other command, this field is ignored.            */
1021 +    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
1022 +                                                 *  if signal is required, this field contains process  *
1023 +                                                 *  ID to which signal would be sent.                   *
1024 +                                                 *  In other command, this field is ignored.            */
1025 +    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
1026 +                                                 *  if signal is required, this field contains signal   *
1027 +                                                 *  number which would be sent.                         *
1028 +                                                 *  In other command, this field is ignored.            */
1029 +};
1030 +
1031 +/*
1032 + * ####################################
1033 + *              Data Type
1034 + * ####################################
1035 + */
1036 +typedef void (*timer_callback)(unsigned long arg);
1037 +
1038 +extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
1039 +extern int lq_free_timer(unsigned int);
1040 +extern int lq_start_timer(unsigned int, int);
1041 +extern int lq_stop_timer(unsigned int);
1042 +extern int lq_reset_counter_flags(u32 timer, u32 flags);
1043 +extern int lq_get_count_value(unsigned int, unsigned long *);
1044 +extern u32 lq_cal_divider(unsigned long);
1045 +extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
1046 +extern int lq_set_counter(unsigned int timer, unsigned int flag,
1047 +       u32 reload, unsigned long arg1, unsigned long arg2);
1048 +
1049 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */