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[openwrt/openwrt.git] / target / linux / lantiq / patches-3.7 / 0116-NET-MIPS-lantiq-update-etop-driver-for-devicetree.patch
1 From c7b0e371e1c5e2f6258decfeb948e0dda7109afc Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 24 Oct 2012 19:50:30 +0200
4 Subject: [PATCH 116/123] NET: MIPS: lantiq: update etop driver for devicetree
5
6 ---
7 drivers/net/ethernet/lantiq_etop.c | 470 +++++++++++++++++++++++++-----------
8 1 file changed, 333 insertions(+), 137 deletions(-)
9
10 --- a/drivers/net/ethernet/lantiq_etop.c
11 +++ b/drivers/net/ethernet/lantiq_etop.c
12 @@ -12,7 +12,7 @@
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 *
16 - * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
17 + * Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
18 */
19
20 #include <linux/kernel.h>
21 @@ -36,6 +36,10 @@
22 #include <linux/io.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/module.h>
25 +#include <linux/clk.h>
26 +#include <linux/of_net.h>
27 +#include <linux/of_irq.h>
28 +#include <linux/of_platform.h>
29
30 #include <asm/checksum.h>
31
32 @@ -71,25 +75,56 @@
33 #define ETOP_MII_REVERSE 0xe
34 #define ETOP_PLEN_UNDER 0x40
35 #define ETOP_CGEN 0x800
36 +#define ETOP_CFG_MII0 0x01
37
38 -/* use 2 static channels for TX/RX */
39 -#define LTQ_ETOP_TX_CHANNEL 1
40 -#define LTQ_ETOP_RX_CHANNEL 6
41 -#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
42 -#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
43 +#define LTQ_GBIT_MDIO_CTL 0xCC
44 +#define LTQ_GBIT_MDIO_DATA 0xd0
45 +#define LTQ_GBIT_GCTL0 0x68
46 +#define LTQ_GBIT_PMAC_HD_CTL 0x8c
47 +#define LTQ_GBIT_P0_CTL 0x4
48 +#define LTQ_GBIT_PMAC_RX_IPG 0xa8
49 +
50 +#define PMAC_HD_CTL_AS (1 << 19)
51 +#define PMAC_HD_CTL_RXSH (1 << 22)
52 +
53 +/* Switch Enable (0=disable, 1=enable) */
54 +#define GCTL0_SE 0x80000000
55 +/* Disable MDIO auto polling (0=disable, 1=enable) */
56 +#define PX_CTL_DMDIO 0x00400000
57 +
58 +/* register information for the gbit's MDIO bus */
59 +#define MDIO_XR9_REQUEST 0x00008000
60 +#define MDIO_XR9_READ 0x00000800
61 +#define MDIO_XR9_WRITE 0x00000400
62 +#define MDIO_XR9_REG_MASK 0x1f
63 +#define MDIO_XR9_ADDR_MASK 0x1f
64 +#define MDIO_XR9_RD_MASK 0xffff
65 +#define MDIO_XR9_REG_OFFSET 0
66 +#define MDIO_XR9_ADDR_OFFSET 5
67 +#define MDIO_XR9_WR_OFFSET 16
68
69 +#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \
70 + (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
71 +
72 +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
73 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
74 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
75 #define ltq_etop_w32_mask(x, y, z) \
76 ltq_w32_mask(x, y, ltq_etop_membase + (z))
77
78 -#define DRV_VERSION "1.0"
79 +#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x))
80 +#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y))
81 +#define ltq_gbit_w32_mask(x, y, z) \
82 + ltq_w32_mask(x, y, ltq_gbit_membase + (z))
83 +
84 +#define DRV_VERSION "1.2"
85
86 static void __iomem *ltq_etop_membase;
87 +static void __iomem *ltq_gbit_membase;
88
89 struct ltq_etop_chan {
90 - int idx;
91 int tx_free;
92 + int irq;
93 struct net_device *netdev;
94 struct napi_struct napi;
95 struct ltq_dma_channel dma;
96 @@ -99,22 +134,35 @@ struct ltq_etop_chan {
97 struct ltq_etop_priv {
98 struct net_device *netdev;
99 struct platform_device *pdev;
100 - struct ltq_eth_data *pldata;
101 struct resource *res;
102
103 struct mii_bus *mii_bus;
104 struct phy_device *phydev;
105
106 - struct ltq_etop_chan ch[MAX_DMA_CHAN];
107 - int tx_free[MAX_DMA_CHAN >> 1];
108 + struct ltq_etop_chan txch;
109 + struct ltq_etop_chan rxch;
110 +
111 + int tx_irq;
112 + int rx_irq;
113 +
114 + const void *mac;
115 + int mii_mode;
116
117 spinlock_t lock;
118 +
119 + struct clk *clk_ppe;
120 + struct clk *clk_switch;
121 + struct clk *clk_ephy;
122 + struct clk *clk_ephycgu;
123 };
124
125 +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
126 + int phy_reg, u16 phy_data);
127 +
128 static int
129 ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
130 {
131 - ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
132 + ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
133 if (!ch->skb[ch->dma.desc])
134 return -ENOMEM;
135 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
136 @@ -149,8 +197,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
137 spin_unlock_irqrestore(&priv->lock, flags);
138
139 skb_put(skb, len);
140 + skb->dev = ch->netdev;
141 skb->protocol = eth_type_trans(skb, ch->netdev);
142 netif_receive_skb(skb);
143 + ch->netdev->stats.rx_packets++;
144 + ch->netdev->stats.rx_bytes += len;
145 }
146
147 static int
148 @@ -158,8 +209,10 @@ ltq_etop_poll_rx(struct napi_struct *nap
149 {
150 struct ltq_etop_chan *ch = container_of(napi,
151 struct ltq_etop_chan, napi);
152 + struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
153 int rx = 0;
154 int complete = 0;
155 + unsigned long flags;
156
157 while ((rx < budget) && !complete) {
158 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
159 @@ -173,7 +226,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
160 }
161 if (complete || !rx) {
162 napi_complete(&ch->napi);
163 + spin_lock_irqsave(&priv->lock, flags);
164 ltq_dma_ack_irq(&ch->dma);
165 + spin_unlock_irqrestore(&priv->lock, flags);
166 }
167 return rx;
168 }
169 @@ -185,12 +240,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
170 container_of(napi, struct ltq_etop_chan, napi);
171 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
172 struct netdev_queue *txq =
173 - netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
174 + netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
175 unsigned long flags;
176
177 spin_lock_irqsave(&priv->lock, flags);
178 while ((ch->dma.desc_base[ch->tx_free].ctl &
179 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
180 + ch->netdev->stats.tx_packets++;
181 + ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
182 dev_kfree_skb_any(ch->skb[ch->tx_free]);
183 ch->skb[ch->tx_free] = NULL;
184 memset(&ch->dma.desc_base[ch->tx_free], 0,
185 @@ -203,7 +260,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
186 if (netif_tx_queue_stopped(txq))
187 netif_tx_start_queue(txq);
188 napi_complete(&ch->napi);
189 + spin_lock_irqsave(&priv->lock, flags);
190 ltq_dma_ack_irq(&ch->dma);
191 + spin_unlock_irqrestore(&priv->lock, flags);
192 return 1;
193 }
194
195 @@ -211,9 +270,10 @@ static irqreturn_t
196 ltq_etop_dma_irq(int irq, void *_priv)
197 {
198 struct ltq_etop_priv *priv = _priv;
199 - int ch = irq - LTQ_DMA_CH0_INT;
200 -
201 - napi_schedule(&priv->ch[ch].napi);
202 + if (irq == priv->txch.dma.irq)
203 + napi_schedule(&priv->txch.napi);
204 + else
205 + napi_schedule(&priv->rxch.napi);
206 return IRQ_HANDLED;
207 }
208
209 @@ -225,7 +285,7 @@ ltq_etop_free_channel(struct net_device
210 ltq_dma_free(&ch->dma);
211 if (ch->dma.irq)
212 free_irq(ch->dma.irq, priv);
213 - if (IS_RX(ch->idx)) {
214 + if (ch == &priv->txch) {
215 int desc;
216 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
217 dev_kfree_skb_any(ch->skb[ch->dma.desc]);
218 @@ -236,23 +296,55 @@ static void
219 ltq_etop_hw_exit(struct net_device *dev)
220 {
221 struct ltq_etop_priv *priv = netdev_priv(dev);
222 - int i;
223
224 - ltq_pmu_disable(PMU_PPE);
225 - for (i = 0; i < MAX_DMA_CHAN; i++)
226 - if (IS_TX(i) || IS_RX(i))
227 - ltq_etop_free_channel(dev, &priv->ch[i]);
228 + clk_disable(priv->clk_ppe);
229 +
230 + if (of_machine_is_compatible("lantiq,ar9"))
231 + clk_disable(priv->clk_switch);
232 +
233 + if (of_machine_is_compatible("lantiq,ase")) {
234 + clk_disable(priv->clk_ephy);
235 + clk_disable(priv->clk_ephycgu);
236 + }
237 +
238 + ltq_etop_free_channel(dev, &priv->txch);
239 + ltq_etop_free_channel(dev, &priv->rxch);
240 +}
241 +
242 +static void
243 +ltq_etop_gbit_init(struct net_device *dev)
244 +{
245 + struct ltq_etop_priv *priv = netdev_priv(dev);
246 +
247 + clk_enable(priv->clk_switch);
248 +
249 + ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
250 + /** Disable MDIO auto polling mode */
251 + ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
252 + /* set 1522 packet size */
253 + ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
254 + /* disable pmac & dmac headers */
255 + ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
256 + LTQ_GBIT_PMAC_HD_CTL);
257 + /* Due to traffic halt when burst length 8,
258 + replace default IPG value with 0x3B */
259 + ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
260 }
261
262 static int
263 ltq_etop_hw_init(struct net_device *dev)
264 {
265 struct ltq_etop_priv *priv = netdev_priv(dev);
266 - int i;
267
268 - ltq_pmu_enable(PMU_PPE);
269 + clk_enable(priv->clk_ppe);
270 +
271 + if (of_machine_is_compatible("lantiq,ar9")) {
272 + ltq_etop_gbit_init(dev);
273 + /* force the etops link to the gbit to MII */
274 + priv->mii_mode = PHY_INTERFACE_MODE_MII;
275 + }
276
277 - switch (priv->pldata->mii_mode) {
278 + switch (priv->mii_mode) {
279 case PHY_INTERFACE_MODE_RMII:
280 ltq_etop_w32_mask(ETOP_MII_MASK,
281 ETOP_MII_REVERSE, LTQ_ETOP_CFG);
282 @@ -264,39 +356,68 @@ ltq_etop_hw_init(struct net_device *dev)
283 break;
284
285 default:
286 + if (of_machine_is_compatible("lantiq,ase")) {
287 + clk_enable(priv->clk_ephy);
288 + /* disable external MII */
289 + ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
290 + /* enable clock for internal PHY */
291 + clk_enable(priv->clk_ephycgu);
292 + /* we need to write this magic to the internal phy to
293 + make it work */
294 + ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
295 + pr_info("Selected EPHY mode\n");
296 + break;
297 + }
298 netdev_err(dev, "unknown mii mode %d\n",
299 - priv->pldata->mii_mode);
300 + priv->mii_mode);
301 return -ENOTSUPP;
302 }
303
304 /* enable crc generation */
305 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
306
307 + return 0;
308 +}
309 +
310 +static int
311 +ltq_etop_dma_init(struct net_device *dev)
312 +{
313 + struct ltq_etop_priv *priv = netdev_priv(dev);
314 + int tx = priv->tx_irq - LTQ_DMA_ETOP;
315 + int rx = priv->rx_irq - LTQ_DMA_ETOP;
316 + int err;
317 +
318 ltq_dma_init_port(DMA_PORT_ETOP);
319
320 - for (i = 0; i < MAX_DMA_CHAN; i++) {
321 - int irq = LTQ_DMA_CH0_INT + i;
322 - struct ltq_etop_chan *ch = &priv->ch[i];
323 -
324 - ch->idx = ch->dma.nr = i;
325 -
326 - if (IS_TX(i)) {
327 - ltq_dma_alloc_tx(&ch->dma);
328 - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
329 - "etop_tx", priv);
330 - } else if (IS_RX(i)) {
331 - ltq_dma_alloc_rx(&ch->dma);
332 - for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
333 - ch->dma.desc++)
334 - if (ltq_etop_alloc_skb(ch))
335 - return -ENOMEM;
336 - ch->dma.desc = 0;
337 - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
338 - "etop_rx", priv);
339 + priv->txch.dma.nr = tx;
340 + ltq_dma_alloc_tx(&priv->txch.dma);
341 + err = request_irq(priv->tx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
342 + "eth_tx", priv);
343 + if (err) {
344 + netdev_err(dev, "failed to allocate tx irq\n");
345 + goto err_out;
346 + }
347 + priv->txch.dma.irq = priv->tx_irq;
348 +
349 + priv->rxch.dma.nr = rx;
350 + ltq_dma_alloc_rx(&priv->rxch.dma);
351 + for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
352 + priv->rxch.dma.desc++) {
353 + if (ltq_etop_alloc_skb(&priv->rxch)) {
354 + netdev_err(dev, "failed to allocate skbs\n");
355 + err = -ENOMEM;
356 + goto err_out;
357 }
358 - ch->dma.irq = irq;
359 }
360 - return 0;
361 + priv->rxch.dma.desc = 0;
362 + err = request_irq(priv->rx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
363 + "eth_rx", priv);
364 + if (err)
365 + netdev_err(dev, "failed to allocate rx irq\n");
366 + else
367 + priv->rxch.dma.irq = priv->rx_irq;
368 +err_out:
369 + return err;
370 }
371
372 static void
373 @@ -312,7 +433,10 @@ ltq_etop_get_settings(struct net_device
374 {
375 struct ltq_etop_priv *priv = netdev_priv(dev);
376
377 - return phy_ethtool_gset(priv->phydev, cmd);
378 + if (priv->phydev)
379 + return phy_ethtool_gset(priv->phydev, cmd);
380 + else
381 + return 0;
382 }
383
384 static int
385 @@ -320,7 +444,10 @@ ltq_etop_set_settings(struct net_device
386 {
387 struct ltq_etop_priv *priv = netdev_priv(dev);
388
389 - return phy_ethtool_sset(priv->phydev, cmd);
390 + if (priv->phydev)
391 + return phy_ethtool_sset(priv->phydev, cmd);
392 + else
393 + return 0;
394 }
395
396 static int
397 @@ -328,7 +455,10 @@ ltq_etop_nway_reset(struct net_device *d
398 {
399 struct ltq_etop_priv *priv = netdev_priv(dev);
400
401 - return phy_start_aneg(priv->phydev);
402 + if (priv->phydev)
403 + return phy_start_aneg(priv->phydev);
404 + else
405 + return 0;
406 }
407
408 static const struct ethtool_ops ltq_etop_ethtool_ops = {
409 @@ -339,6 +469,39 @@ static const struct ethtool_ops ltq_etop
410 };
411
412 static int
413 +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
414 + int phy_reg, u16 phy_data)
415 +{
416 + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
417 + (phy_data << MDIO_XR9_WR_OFFSET) |
418 + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
419 + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
420 +
421 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
422 + ;
423 + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
424 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
425 + ;
426 + return 0;
427 +}
428 +
429 +static int
430 +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
431 +{
432 + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
433 + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
434 + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
435 +
436 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
437 + ;
438 + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
439 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
440 + ;
441 + val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
442 + return val;
443 +}
444 +
445 +static int
446 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
447 {
448 u32 val = MDIO_REQUEST |
449 @@ -379,14 +542,11 @@ ltq_etop_mdio_probe(struct net_device *d
450 {
451 struct ltq_etop_priv *priv = netdev_priv(dev);
452 struct phy_device *phydev = NULL;
453 - int phy_addr;
454
455 - for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
456 - if (priv->mii_bus->phy_map[phy_addr]) {
457 - phydev = priv->mii_bus->phy_map[phy_addr];
458 - break;
459 - }
460 - }
461 + if (of_machine_is_compatible("lantiq,ase"))
462 + phydev = priv->mii_bus->phy_map[8];
463 + else
464 + phydev = priv->mii_bus->phy_map[0];
465
466 if (!phydev) {
467 netdev_err(dev, "no PHY found\n");
468 @@ -394,7 +554,7 @@ ltq_etop_mdio_probe(struct net_device *d
469 }
470
471 phydev = phy_connect(dev, dev_name(&phydev->dev), &ltq_etop_mdio_link,
472 - 0, priv->pldata->mii_mode);
473 + 0, priv->mii_mode);
474
475 if (IS_ERR(phydev)) {
476 netdev_err(dev, "Could not attach to PHY\n");
477 @@ -408,6 +568,9 @@ ltq_etop_mdio_probe(struct net_device *d
478 | SUPPORTED_Autoneg
479 | SUPPORTED_MII
480 | SUPPORTED_TP);
481 + if (of_machine_is_compatible("lantiq,ar9"))
482 + phydev->supported &= SUPPORTED_1000baseT_Half
483 + | SUPPORTED_1000baseT_Full;
484
485 phydev->advertising = phydev->supported;
486 priv->phydev = phydev;
487 @@ -433,8 +596,13 @@ ltq_etop_mdio_init(struct net_device *de
488 }
489
490 priv->mii_bus->priv = dev;
491 - priv->mii_bus->read = ltq_etop_mdio_rd;
492 - priv->mii_bus->write = ltq_etop_mdio_wr;
493 + if (of_machine_is_compatible("lantiq,ar9")) {
494 + priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
495 + priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
496 + } else {
497 + priv->mii_bus->read = ltq_etop_mdio_rd;
498 + priv->mii_bus->write = ltq_etop_mdio_wr;
499 + }
500 priv->mii_bus->name = "ltq_mii";
501 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
502 priv->pdev->name, priv->pdev->id);
503 @@ -483,17 +651,19 @@ static int
504 ltq_etop_open(struct net_device *dev)
505 {
506 struct ltq_etop_priv *priv = netdev_priv(dev);
507 - int i;
508 + unsigned long flags;
509
510 - for (i = 0; i < MAX_DMA_CHAN; i++) {
511 - struct ltq_etop_chan *ch = &priv->ch[i];
512 + napi_enable(&priv->txch.napi);
513 + napi_enable(&priv->rxch.napi);
514 +
515 + spin_lock_irqsave(&priv->lock, flags);
516 + ltq_dma_open(&priv->txch.dma);
517 + ltq_dma_open(&priv->rxch.dma);
518 + spin_unlock_irqrestore(&priv->lock, flags);
519 +
520 + if (priv->phydev)
521 + phy_start(priv->phydev);
522
523 - if (!IS_TX(i) && (!IS_RX(i)))
524 - continue;
525 - ltq_dma_open(&ch->dma);
526 - napi_enable(&ch->napi);
527 - }
528 - phy_start(priv->phydev);
529 netif_tx_start_all_queues(dev);
530 return 0;
531 }
532 @@ -502,18 +672,19 @@ static int
533 ltq_etop_stop(struct net_device *dev)
534 {
535 struct ltq_etop_priv *priv = netdev_priv(dev);
536 - int i;
537 + unsigned long flags;
538
539 netif_tx_stop_all_queues(dev);
540 - phy_stop(priv->phydev);
541 - for (i = 0; i < MAX_DMA_CHAN; i++) {
542 - struct ltq_etop_chan *ch = &priv->ch[i];
543 -
544 - if (!IS_RX(i) && !IS_TX(i))
545 - continue;
546 - napi_disable(&ch->napi);
547 - ltq_dma_close(&ch->dma);
548 - }
549 + if (priv->phydev)
550 + phy_stop(priv->phydev);
551 + napi_disable(&priv->txch.napi);
552 + napi_disable(&priv->rxch.napi);
553 +
554 + spin_lock_irqsave(&priv->lock, flags);
555 + ltq_dma_close(&priv->txch.dma);
556 + ltq_dma_close(&priv->rxch.dma);
557 + spin_unlock_irqrestore(&priv->lock, flags);
558 +
559 return 0;
560 }
561
562 @@ -523,16 +694,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
563 int queue = skb_get_queue_mapping(skb);
564 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
565 struct ltq_etop_priv *priv = netdev_priv(dev);
566 - struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
567 - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
568 - int len;
569 + struct ltq_dma_desc *desc =
570 + &priv->txch.dma.desc_base[priv->txch.dma.desc];
571 unsigned long flags;
572 u32 byte_offset;
573 + int len;
574
575 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
576
577 - if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
578 - dev_kfree_skb_any(skb);
579 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
580 + priv->txch.skb[priv->txch.dma.desc]) {
581 netdev_err(dev, "tx ring full\n");
582 netif_tx_stop_queue(txq);
583 return NETDEV_TX_BUSY;
584 @@ -540,7 +711,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
585
586 /* dma needs to start on a 16 byte aligned address */
587 byte_offset = CPHYSADDR(skb->data) % 16;
588 - ch->skb[ch->dma.desc] = skb;
589 + priv->txch.skb[priv->txch.dma.desc] = skb;
590
591 dev->trans_start = jiffies;
592
593 @@ -550,11 +721,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
594 wmb();
595 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
596 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
597 - ch->dma.desc++;
598 - ch->dma.desc %= LTQ_DESC_NUM;
599 + priv->txch.dma.desc++;
600 + priv->txch.dma.desc %= LTQ_DESC_NUM;
601 spin_unlock_irqrestore(&priv->lock, flags);
602
603 - if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
604 + if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
605 netif_tx_stop_queue(txq);
606
607 return NETDEV_TX_OK;
608 @@ -633,34 +804,32 @@ ltq_etop_init(struct net_device *dev)
609 struct ltq_etop_priv *priv = netdev_priv(dev);
610 struct sockaddr mac;
611 int err;
612 - bool random_mac = false;
613
614 ether_setup(dev);
615 dev->watchdog_timeo = 10 * HZ;
616 err = ltq_etop_hw_init(dev);
617 if (err)
618 goto err_hw;
619 + err = ltq_etop_dma_init(dev);
620 + if (err)
621 + goto err_hw;
622 +
623 ltq_etop_change_mtu(dev, 1500);
624
625 - memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
626 + memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
627 if (!is_valid_ether_addr(mac.sa_data)) {
628 pr_warn("etop: invalid MAC, using random\n");
629 - eth_random_addr(mac.sa_data);
630 - random_mac = true;
631 + random_ether_addr(mac.sa_data);
632 }
633
634 err = ltq_etop_set_mac_address(dev, &mac);
635 if (err)
636 goto err_netdev;
637 -
638 - /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
639 - if (random_mac)
640 - dev->addr_assign_type |= NET_ADDR_RANDOM;
641 -
642 ltq_etop_set_multicast_list(dev);
643 - err = ltq_etop_mdio_init(dev);
644 - if (err)
645 - goto err_netdev;
646 + if (!ltq_etop_mdio_init(dev))
647 + dev->ethtool_ops = &ltq_etop_ethtool_ops;
648 + else
649 + pr_warn("etop: mdio probe failed\n");;
650 return 0;
651
652 err_netdev:
653 @@ -680,6 +849,9 @@ ltq_etop_tx_timeout(struct net_device *d
654 err = ltq_etop_hw_init(dev);
655 if (err)
656 goto err_hw;
657 + err = ltq_etop_dma_init(dev);
658 + if (err)
659 + goto err_hw;
660 dev->trans_start = jiffies;
661 netif_wake_queue(dev);
662 return;
663 @@ -703,14 +875,19 @@ static const struct net_device_ops ltq_e
664 .ndo_tx_timeout = ltq_etop_tx_timeout,
665 };
666
667 -static int __init
668 +static int __devinit
669 ltq_etop_probe(struct platform_device *pdev)
670 {
671 struct net_device *dev;
672 struct ltq_etop_priv *priv;
673 - struct resource *res;
674 + struct resource *res, *gbit_res, irqres[2];
675 int err;
676 - int i;
677 +
678 + err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
679 + if (err != 2) {
680 + dev_err(&pdev->dev, "failed to get etop irqs\n");
681 + return -EINVAL;
682 + }
683
684 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
685 if (!res) {
686 @@ -736,30 +913,58 @@ ltq_etop_probe(struct platform_device *p
687 goto err_out;
688 }
689
690 - dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
691 - if (!dev) {
692 - err = -ENOMEM;
693 - goto err_out;
694 + if (of_machine_is_compatible("lantiq,ar9")) {
695 + gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
696 + if (!gbit_res) {
697 + dev_err(&pdev->dev, "failed to get gbit resource\n");
698 + err = -ENOENT;
699 + goto err_out;
700 + }
701 + ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
702 + gbit_res->start, resource_size(gbit_res));
703 + if (!ltq_gbit_membase) {
704 + dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
705 + pdev->id);
706 + err = -ENOMEM;
707 + goto err_out;
708 + }
709 }
710 +
711 + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
712 strcpy(dev->name, "eth%d");
713 dev->netdev_ops = &ltq_eth_netdev_ops;
714 - dev->ethtool_ops = &ltq_etop_ethtool_ops;
715 priv = netdev_priv(dev);
716 priv->res = res;
717 priv->pdev = pdev;
718 - priv->pldata = dev_get_platdata(&pdev->dev);
719 priv->netdev = dev;
720 + priv->tx_irq = irqres[0].start;
721 + priv->rx_irq = irqres[1].start;
722 + priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
723 + priv->mac = of_get_mac_address(pdev->dev.of_node);
724 +
725 + priv->clk_ppe = clk_get(&pdev->dev, NULL);
726 + if (IS_ERR(priv->clk_ppe))
727 + return PTR_ERR(priv->clk_ppe);
728 + if (of_machine_is_compatible("lantiq,ar9")) {
729 + priv->clk_switch = clk_get(&pdev->dev, "switch");
730 + if (IS_ERR(priv->clk_switch))
731 + return PTR_ERR(priv->clk_switch);
732 + }
733 + if (of_machine_is_compatible("lantiq,ase")) {
734 + priv->clk_ephy = clk_get(&pdev->dev, "ephy");
735 + if (IS_ERR(priv->clk_ephy))
736 + return PTR_ERR(priv->clk_ephy);
737 + priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
738 + if (IS_ERR(priv->clk_ephycgu))
739 + return PTR_ERR(priv->clk_ephycgu);
740 + }
741 +
742 spin_lock_init(&priv->lock);
743
744 - for (i = 0; i < MAX_DMA_CHAN; i++) {
745 - if (IS_TX(i))
746 - netif_napi_add(dev, &priv->ch[i].napi,
747 - ltq_etop_poll_tx, 8);
748 - else if (IS_RX(i))
749 - netif_napi_add(dev, &priv->ch[i].napi,
750 - ltq_etop_poll_rx, 32);
751 - priv->ch[i].netdev = dev;
752 - }
753 + netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
754 + netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
755 + priv->txch.netdev = dev;
756 + priv->rxch.netdev = dev;
757
758 err = register_netdev(dev);
759 if (err)
760 @@ -788,32 +993,23 @@ ltq_etop_remove(struct platform_device *
761 return 0;
762 }
763
764 +static const struct of_device_id ltq_etop_match[] = {
765 + { .compatible = "lantiq,etop-xway" },
766 + {},
767 +};
768 +MODULE_DEVICE_TABLE(of, ltq_etop_match);
769 +
770 static struct platform_driver ltq_mii_driver = {
771 + .probe = ltq_etop_probe,
772 .remove = __devexit_p(ltq_etop_remove),
773 .driver = {
774 .name = "ltq_etop",
775 .owner = THIS_MODULE,
776 + .of_match_table = ltq_etop_match,
777 },
778 };
779
780 -int __init
781 -init_ltq_etop(void)
782 -{
783 - int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
784 -
785 - if (ret)
786 - pr_err("ltq_etop: Error registering platform driver!");
787 - return ret;
788 -}
789 -
790 -static void __exit
791 -exit_ltq_etop(void)
792 -{
793 - platform_driver_unregister(&ltq_mii_driver);
794 -}
795 -
796 -module_init(init_ltq_etop);
797 -module_exit(exit_ltq_etop);
798 +module_platform_driver(ltq_mii_driver);
799
800 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
801 MODULE_DESCRIPTION("Lantiq SoC ETOP");
OpenWrt Source Repository