target/linux/lantiq/patches-3.7/0114-SPI-MIPS-lantiq-adds-spi-xway.patch

   1 From db447f1a18106aa4d32438ab72ff57024b34cee4 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 16 Aug 2012 09:57:01 +0200
   4 Subject: [PATCH 114/123] SPI: MIPS: lantiq: adds spi-xway
   5
   6 This patch adds support for the SPI core found on several Lantiq SoCs.
   7 The Driver has been runtime tested in combination with m25p80 Flash Devices
   8 on Amazon_SE and VR9.
   9
  10 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
  11 Signed-off-by: John Crispin <blogic@openwrt.org>
  12 ---
  13  drivers/spi/Kconfig    |    8 +
  14  drivers/spi/Makefile   |    1 +
  15  drivers/spi/spi-xway.c |  977 ++++++++++++++++++++++++++++++++++++++++++++++++
  16  3 files changed, 986 insertions(+)
  17  create mode 100644 drivers/spi/spi-xway.c
  18
  19 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
  20 index 1acae35..d79a587 100644
  21 --- a/drivers/spi/Kconfig
  22 +++ b/drivers/spi/Kconfig
  23 @@ -434,6 +434,14 @@ config SPI_NUC900
  24         help
  25           SPI driver for Nuvoton NUC900 series ARM SoCs
  26
  27 +config SPI_XWAY
  28 +       tristate "Lantiq XWAY SPI controller"
  29 +       depends on LANTIQ && SOC_TYPE_XWAY
  30 +       select SPI_BITBANG
  31 +       help
  32 +         This driver supports the Lantiq SoC SPI controller in master
  33 +         mode.
  34 +
  35  #
  36  # Add new SPI master controllers in alphabetical order above this line
  37  #
  38 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
  39 index c48df47..7e344a9 100644
  40 --- a/drivers/spi/Makefile
  41 +++ b/drivers/spi/Makefile
  42 @@ -66,4 +66,5 @@ obj-$(CONFIG_SPI_TOPCLIFF_PCH)                += spi-topcliff-pch.o
  43  obj-$(CONFIG_SPI_TXX9)                 += spi-txx9.o
  44  obj-$(CONFIG_SPI_XCOMM)                += spi-xcomm.o
  45  obj-$(CONFIG_SPI_XILINX)               += spi-xilinx.o
  46 +obj-$(CONFIG_SPI_XWAY)         += spi-xway.o
  47
  48 diff --git a/drivers/spi/spi-xway.c b/drivers/spi/spi-xway.c
  49 new file mode 100644
  50 index 0000000..8441085
  51 --- /dev/null
  52 +++ b/drivers/spi/spi-xway.c
  53 @@ -0,0 +1,977 @@
  54 +/*
  55 + * Lantiq SoC SPI controller
  56 + *
  57 + * Copyright (C) 2011 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
  58 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
  59 + *
  60 + * This program is free software; you can distribute it and/or modify it
  61 + * under the terms of the GNU General Public License (Version 2) as
  62 + * published by the Free Software Foundation.
  63 + */
  64 +
  65 +#include <linux/init.h>
  66 +#include <linux/module.h>
  67 +#include <linux/workqueue.h>
  68 +#include <linux/platform_device.h>
  69 +#include <linux/io.h>
  70 +#include <linux/sched.h>
  71 +#include <linux/delay.h>
  72 +#include <linux/interrupt.h>
  73 +#include <linux/completion.h>
  74 +#include <linux/spinlock.h>
  75 +#include <linux/err.h>
  76 +#include <linux/clk.h>
  77 +#include <linux/spi/spi.h>
  78 +#include <linux/spi/spi_bitbang.h>
  79 +#include <linux/of_irq.h>
  80 +
  81 +#include <lantiq_soc.h>
  82 +
  83 +#define LTQ_SPI_CLC            0x00    /* Clock control */
  84 +#define LTQ_SPI_PISEL          0x04    /* Port input select */
  85 +#define LTQ_SPI_ID             0x08    /* Identification */
  86 +#define LTQ_SPI_CON            0x10    /* Control */
  87 +#define LTQ_SPI_STAT           0x14    /* Status */
  88 +#define LTQ_SPI_WHBSTATE       0x18    /* Write HW modified state */
  89 +#define LTQ_SPI_TB             0x20    /* Transmit buffer */
  90 +#define LTQ_SPI_RB             0x24    /* Receive buffer */
  91 +#define LTQ_SPI_RXFCON         0x30    /* Receive FIFO control */
  92 +#define LTQ_SPI_TXFCON         0x34    /* Transmit FIFO control */
  93 +#define LTQ_SPI_FSTAT          0x38    /* FIFO status */
  94 +#define LTQ_SPI_BRT            0x40    /* Baudrate timer */
  95 +#define LTQ_SPI_BRSTAT         0x44    /* Baudrate timer status */
  96 +#define LTQ_SPI_SFCON          0x60    /* Serial frame control */
  97 +#define LTQ_SPI_SFSTAT         0x64    /* Serial frame status */
  98 +#define LTQ_SPI_GPOCON         0x70    /* General purpose output control */
  99 +#define LTQ_SPI_GPOSTAT                0x74    /* General purpose output status */
 100 +#define LTQ_SPI_FGPO           0x78    /* Forced general purpose output */
 101 +#define LTQ_SPI_RXREQ          0x80    /* Receive request */
 102 +#define LTQ_SPI_RXCNT          0x84    /* Receive count */
 103 +#define LTQ_SPI_DMACON         0xEC    /* DMA control */
 104 +#define LTQ_SPI_IRNEN          0xF4    /* Interrupt node enable */
 105 +#define LTQ_SPI_IRNICR         0xF8    /* Interrupt node interrupt capture */
 106 +#define LTQ_SPI_IRNCR          0xFC    /* Interrupt node control */
 107 +
 108 +#define LTQ_SPI_CLC_SMC_SHIFT  16      /* Clock divider for sleep mode */
 109 +#define LTQ_SPI_CLC_SMC_MASK   0xFF
 110 +#define LTQ_SPI_CLC_RMC_SHIFT  8       /* Clock divider for normal run mode */
 111 +#define LTQ_SPI_CLC_RMC_MASK   0xFF
 112 +#define LTQ_SPI_CLC_DISS       BIT(1)  /* Disable status bit */
 113 +#define LTQ_SPI_CLC_DISR       BIT(0)  /* Disable request bit */
 114 +
 115 +#define LTQ_SPI_ID_TXFS_SHIFT  24      /* Implemented TX FIFO size */
 116 +#define LTQ_SPI_ID_TXFS_MASK   0x3F
 117 +#define LTQ_SPI_ID_RXFS_SHIFT  16      /* Implemented RX FIFO size */
 118 +#define LTQ_SPI_ID_RXFS_MASK   0x3F
 119 +#define LTQ_SPI_ID_REV_MASK    0x1F    /* Hardware revision number */
 120 +#define LTQ_SPI_ID_CFG         BIT(5)  /* DMA interface support */
 121 +
 122 +#define LTQ_SPI_CON_BM_SHIFT   16      /* Data width selection */
 123 +#define LTQ_SPI_CON_BM_MASK    0x1F
 124 +#define LTQ_SPI_CON_EM         BIT(24) /* Echo mode */
 125 +#define LTQ_SPI_CON_IDLE       BIT(23) /* Idle bit value */
 126 +#define LTQ_SPI_CON_ENBV       BIT(22) /* Enable byte valid control */
 127 +#define LTQ_SPI_CON_RUEN       BIT(12) /* Receive underflow error enable */
 128 +#define LTQ_SPI_CON_TUEN       BIT(11) /* Transmit underflow error enable */
 129 +#define LTQ_SPI_CON_AEN                BIT(10) /* Abort error enable */
 130 +#define LTQ_SPI_CON_REN                BIT(9)  /* Receive overflow error enable */
 131 +#define LTQ_SPI_CON_TEN                BIT(8)  /* Transmit overflow error enable */
 132 +#define LTQ_SPI_CON_LB         BIT(7)  /* Loopback control */
 133 +#define LTQ_SPI_CON_PO         BIT(6)  /* Clock polarity control */
 134 +#define LTQ_SPI_CON_PH         BIT(5)  /* Clock phase control */
 135 +#define LTQ_SPI_CON_HB         BIT(4)  /* Heading control */
 136 +#define LTQ_SPI_CON_RXOFF      BIT(1)  /* Switch receiver off */
 137 +#define LTQ_SPI_CON_TXOFF      BIT(0)  /* Switch transmitter off */
 138 +
 139 +#define LTQ_SPI_STAT_RXBV_MASK 0x7
 140 +#define LTQ_SPI_STAT_RXBV_SHIFT        28
 141 +#define LTQ_SPI_STAT_BSY       BIT(13) /* Busy flag */
 142 +#define LTQ_SPI_STAT_RUE       BIT(12) /* Receive underflow error flag */
 143 +#define LTQ_SPI_STAT_TUE       BIT(11) /* Transmit underflow error flag */
 144 +#define LTQ_SPI_STAT_AE                BIT(10) /* Abort error flag */
 145 +#define LTQ_SPI_STAT_RE                BIT(9)  /* Receive error flag */
 146 +#define LTQ_SPI_STAT_TE                BIT(8)  /* Transmit error flag */
 147 +#define LTQ_SPI_STAT_MS                BIT(1)  /* Master/slave select bit */
 148 +#define LTQ_SPI_STAT_EN                BIT(0)  /* Enable bit */
 149 +
 150 +#define LTQ_SPI_WHBSTATE_SETTUE        BIT(15) /* Set transmit underflow error flag */
 151 +#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
 152 +#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
 153 +#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
 154 +#define LTQ_SPI_WHBSTATE_CLRTUE        BIT(11) /* Clear transmit underflow error
 155 +                                               flag */
 156 +#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
 157 +#define LTQ_SPI_WHBSTATE_CLRRE BIT(9)  /* Clear receive error flag */
 158 +#define LTQ_SPI_WHBSTATE_CLRTE BIT(8)  /* Clear transmit error flag */
 159 +#define LTQ_SPI_WHBSTATE_SETME BIT(7)  /* Set mode error flag */
 160 +#define LTQ_SPI_WHBSTATE_CLRME BIT(6)  /* Clear mode error flag */
 161 +#define LTQ_SPI_WHBSTATE_SETRUE        BIT(5)  /* Set receive underflow error flag */
 162 +#define LTQ_SPI_WHBSTATE_CLRRUE        BIT(4)  /* Clear receive underflow error flag */
 163 +#define LTQ_SPI_WHBSTATE_SETMS BIT(3)  /* Set master select bit */
 164 +#define LTQ_SPI_WHBSTATE_CLRMS BIT(2)  /* Clear master select bit */
 165 +#define LTQ_SPI_WHBSTATE_SETEN BIT(1)  /* Set enable bit (operational mode) */
 166 +#define LTQ_SPI_WHBSTATE_CLREN BIT(0)  /* Clear enable bit (config mode */
 167 +#define LTQ_SPI_WHBSTATE_CLR_ERRORS    0x0F50
 168 +
 169 +#define LTQ_SPI_RXFCON_RXFITL_SHIFT    8 /* FIFO interrupt trigger level */
 170 +#define LTQ_SPI_RXFCON_RXFITL_MASK     0x3F
 171 +#define LTQ_SPI_RXFCON_RXFLU           BIT(1)  /* FIFO flush */
 172 +#define LTQ_SPI_RXFCON_RXFEN           BIT(0)  /* FIFO enable */
 173 +
 174 +#define LTQ_SPI_TXFCON_TXFITL_SHIFT    8 /* FIFO interrupt trigger level */
 175 +#define LTQ_SPI_TXFCON_TXFITL_MASK     0x3F
 176 +#define LTQ_SPI_TXFCON_TXFLU           BIT(1)  /* FIFO flush */
 177 +#define LTQ_SPI_TXFCON_TXFEN           BIT(0)  /* FIFO enable */
 178 +
 179 +#define LTQ_SPI_FSTAT_RXFFL_MASK       0x3f
 180 +#define LTQ_SPI_FSTAT_RXFFL_SHIFT      0
 181 +#define LTQ_SPI_FSTAT_TXFFL_MASK       0x3f
 182 +#define LTQ_SPI_FSTAT_TXFFL_SHIFT      8
 183 +
 184 +#define LTQ_SPI_GPOCON_ISCSBN_SHIFT    8
 185 +#define LTQ_SPI_GPOCON_INVOUTN_SHIFT   0
 186 +
 187 +#define LTQ_SPI_FGPO_SETOUTN_SHIFT     8
 188 +#define LTQ_SPI_FGPO_CLROUTN_SHIFT     0
 189 +
 190 +#define LTQ_SPI_RXREQ_RXCNT_MASK       0xFFFF  /* Receive count value */
 191 +#define LTQ_SPI_RXCNT_TODO_MASK                0xFFFF  /* Recevie to-do value */
 192 +
 193 +#define LTQ_SPI_IRNEN_F                BIT(3)  /* Frame end interrupt request */
 194 +#define LTQ_SPI_IRNEN_E                BIT(2)  /* Error end interrupt request */
 195 +#define LTQ_SPI_IRNEN_T                BIT(1)  /* Transmit end interrupt request */
 196 +#define LTQ_SPI_IRNEN_R                BIT(0)  /* Receive end interrupt request */
 197 +#define LTQ_SPI_IRNEN_ALL      0xF
 198 +
 199 +struct ltq_spi {
 200 +       struct spi_bitbang      bitbang;
 201 +       struct completion       done;
 202 +       spinlock_t              lock;
 203 +
 204 +       struct device           *dev;
 205 +       void __iomem            *base;
 206 +       struct clk              *fpiclk;
 207 +       struct clk              *spiclk;
 208 +
 209 +       int                     status;
 210 +       int                     irq[3];
 211 +
 212 +       const u8                *tx;
 213 +       u8                      *rx;
 214 +       u32                     tx_cnt;
 215 +       u32                     rx_cnt;
 216 +       u32                     len;
 217 +       struct spi_transfer     *curr_transfer;
 218 +
 219 +       u32 (*get_tx) (struct ltq_spi *);
 220 +
 221 +       u16                     txfs;
 222 +       u16                     rxfs;
 223 +       unsigned                dma_support:1;
 224 +       unsigned                cfg_mode:1;
 225 +};
 226 +
 227 +static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi)
 228 +{
 229 +       return spi_master_get_devdata(spi->master);
 230 +}
 231 +
 232 +static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg)
 233 +{
 234 +       return ioread32be(hw->base + reg);
 235 +}
 236 +
 237 +static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg)
 238 +{
 239 +       iowrite32be(val, hw->base + reg);
 240 +}
 241 +
 242 +static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg)
 243 +{
 244 +       u32 val;
 245 +
 246 +       val = ltq_spi_reg_read(hw, reg);
 247 +       val |= bits;
 248 +       ltq_spi_reg_write(hw, val, reg);
 249 +}
 250 +
 251 +static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg)
 252 +{
 253 +       u32 val;
 254 +
 255 +       val = ltq_spi_reg_read(hw, reg);
 256 +       val &= ~bits;
 257 +       ltq_spi_reg_write(hw, val, reg);
 258 +}
 259 +
 260 +static void ltq_spi_hw_enable(struct ltq_spi *hw)
 261 +{
 262 +       u32 clc;
 263 +
 264 +       /* Power-up module */
 265 +       clk_enable(hw->spiclk);
 266 +
 267 +       /*
 268 +        * Set clock divider for run mode to 1 to
 269 +        * run at same frequency as FPI bus
 270 +        */
 271 +       clc = (1 << LTQ_SPI_CLC_RMC_SHIFT);
 272 +       ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC);
 273 +}
 274 +
 275 +static void ltq_spi_hw_disable(struct ltq_spi *hw)
 276 +{
 277 +       /* Set clock divider to 0 and set module disable bit */
 278 +       ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC);
 279 +
 280 +       /* Power-down module */
 281 +       clk_disable(hw->spiclk);
 282 +}
 283 +
 284 +static void ltq_spi_reset_fifos(struct ltq_spi *hw)
 285 +{
 286 +       u32 val;
 287 +
 288 +       /*
 289 +        * Enable and flush FIFOs. Set interrupt trigger level to
 290 +        * half of FIFO count implemented in hardware.
 291 +        */
 292 +       if (hw->txfs > 1) {
 293 +               val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1);
 294 +               val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
 295 +               ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON);
 296 +       }
 297 +
 298 +       if (hw->rxfs > 1) {
 299 +               val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1);
 300 +               val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
 301 +               ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON);
 302 +       }
 303 +}
 304 +
 305 +static inline int ltq_spi_wait_ready(struct ltq_spi *hw)
 306 +{
 307 +       u32 stat;
 308 +       unsigned long timeout;
 309 +
 310 +       timeout = jiffies + msecs_to_jiffies(200);
 311 +
 312 +       do {
 313 +               stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT);
 314 +               if (!(stat & LTQ_SPI_STAT_BSY))
 315 +                       return 0;
 316 +
 317 +               cond_resched();
 318 +       } while (!time_after_eq(jiffies, timeout));
 319 +
 320 +       dev_err(hw->dev, "SPI wait ready timed out stat: %x\n", stat);
 321 +
 322 +       return -ETIMEDOUT;
 323 +}
 324 +
 325 +static void ltq_spi_config_mode_set(struct ltq_spi *hw)
 326 +{
 327 +       if (hw->cfg_mode)
 328 +               return;
 329 +
 330 +       /*
 331 +        * Putting the SPI module in config mode is only safe if no
 332 +        * transfer is in progress as indicated by busy flag STATE.BSY.
 333 +        */
 334 +       if (ltq_spi_wait_ready(hw)) {
 335 +               ltq_spi_reset_fifos(hw);
 336 +               hw->status = -ETIMEDOUT;
 337 +       }
 338 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
 339 +
 340 +       hw->cfg_mode = 1;
 341 +}
 342 +
 343 +static void ltq_spi_run_mode_set(struct ltq_spi *hw)
 344 +{
 345 +       if (!hw->cfg_mode)
 346 +               return;
 347 +
 348 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
 349 +
 350 +       hw->cfg_mode = 0;
 351 +}
 352 +
 353 +static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw)
 354 +{
 355 +       const u8 *tx = hw->tx;
 356 +       u32 data = *tx++;
 357 +
 358 +       hw->tx_cnt++;
 359 +       hw->tx++;
 360 +
 361 +       return data;
 362 +}
 363 +
 364 +static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw)
 365 +{
 366 +       const u16 *tx = (u16 *) hw->tx;
 367 +       u32 data = *tx++;
 368 +
 369 +       hw->tx_cnt += 2;
 370 +       hw->tx += 2;
 371 +
 372 +       return data;
 373 +}
 374 +
 375 +static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw)
 376 +{
 377 +       const u32 *tx = (u32 *) hw->tx;
 378 +       u32 data = *tx++;
 379 +
 380 +       hw->tx_cnt += 4;
 381 +       hw->tx += 4;
 382 +
 383 +       return data;
 384 +}
 385 +
 386 +static void ltq_spi_bits_per_word_set(struct spi_device *spi)
 387 +{
 388 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 389 +       u32 bm;
 390 +       u8 bits_per_word = spi->bits_per_word;
 391 +
 392 +       /*
 393 +        * Use either default value of SPI device or value
 394 +        * from current transfer.
 395 +        */
 396 +       if (hw->curr_transfer && hw->curr_transfer->bits_per_word)
 397 +               bits_per_word = hw->curr_transfer->bits_per_word;
 398 +
 399 +       if (bits_per_word <= 8)
 400 +               hw->get_tx = ltq_spi_tx_word_u8;
 401 +       else if (bits_per_word <= 16)
 402 +               hw->get_tx = ltq_spi_tx_word_u16;
 403 +       else if (bits_per_word <= 32)
 404 +               hw->get_tx = ltq_spi_tx_word_u32;
 405 +
 406 +       /* CON.BM value = bits_per_word - 1 */
 407 +       bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT;
 408 +
 409 +       ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK <<
 410 +                            LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON);
 411 +       ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON);
 412 +}
 413 +
 414 +static void ltq_spi_speed_set(struct spi_device *spi)
 415 +{
 416 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 417 +       u32 br, max_speed_hz, spi_clk;
 418 +       u32 speed_hz = spi->max_speed_hz;
 419 +
 420 +       /*
 421 +        * Use either default value of SPI device or value
 422 +        * from current transfer.
 423 +        */
 424 +       if (hw->curr_transfer && hw->curr_transfer->speed_hz)
 425 +               speed_hz = hw->curr_transfer->speed_hz;
 426 +
 427 +       /*
 428 +        * SPI module clock is derived from FPI bus clock dependent on
 429 +        * divider value in CLC.RMS which is always set to 1.
 430 +        */
 431 +       spi_clk = clk_get_rate(hw->fpiclk);
 432 +
 433 +       /*
 434 +        * Maximum SPI clock frequency in master mode is half of
 435 +        * SPI module clock frequency. Maximum reload value of
 436 +        * baudrate generator BR is 2^16.
 437 +        */
 438 +       max_speed_hz = spi_clk / 2;
 439 +       if (speed_hz >= max_speed_hz)
 440 +               br = 0;
 441 +       else
 442 +               br = (max_speed_hz / speed_hz) - 1;
 443 +
 444 +       if (br > 0xFFFF)
 445 +               br = 0xFFFF;
 446 +
 447 +       ltq_spi_reg_write(hw, br, LTQ_SPI_BRT);
 448 +}
 449 +
 450 +static void ltq_spi_clockmode_set(struct spi_device *spi)
 451 +{
 452 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 453 +       u32 con;
 454 +
 455 +       con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
 456 +
 457 +       /*
 458 +        * SPI mode mapping in CON register:
 459 +        * Mode CPOL CPHA CON.PO CON.PH
 460 +        *  0    0    0      0      1
 461 +        *  1    0    1      0      0
 462 +        *  2    1    0      1      1
 463 +        *  3    1    1      1      0
 464 +        */
 465 +       if (spi->mode & SPI_CPHA)
 466 +               con &= ~LTQ_SPI_CON_PH;
 467 +       else
 468 +               con |= LTQ_SPI_CON_PH;
 469 +
 470 +       if (spi->mode & SPI_CPOL)
 471 +               con |= LTQ_SPI_CON_PO;
 472 +       else
 473 +               con &= ~LTQ_SPI_CON_PO;
 474 +
 475 +       /* Set heading control */
 476 +       if (spi->mode & SPI_LSB_FIRST)
 477 +               con &= ~LTQ_SPI_CON_HB;
 478 +       else
 479 +               con |= LTQ_SPI_CON_HB;
 480 +
 481 +       ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
 482 +}
 483 +
 484 +static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t)
 485 +{
 486 +       u32 con;
 487 +
 488 +       con = ltq_spi_reg_read(hw, LTQ_SPI_CON);
 489 +
 490 +       if (t) {
 491 +               if (t->tx_buf && t->rx_buf) {
 492 +                       con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
 493 +               } else if (t->rx_buf) {
 494 +                       con &= ~LTQ_SPI_CON_RXOFF;
 495 +                       con |= LTQ_SPI_CON_TXOFF;
 496 +               } else if (t->tx_buf) {
 497 +                       con &= ~LTQ_SPI_CON_TXOFF;
 498 +                       con |= LTQ_SPI_CON_RXOFF;
 499 +               }
 500 +       } else
 501 +               con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF);
 502 +
 503 +       ltq_spi_reg_write(hw, con, LTQ_SPI_CON);
 504 +}
 505 +
 506 +static void ltq_spi_internal_cs_activate(struct spi_device *spi)
 507 +{
 508 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 509 +       u32 fgpo;
 510 +
 511 +       fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT));
 512 +       ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
 513 +}
 514 +
 515 +static void ltq_spi_internal_cs_deactivate(struct spi_device *spi)
 516 +{
 517 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 518 +       u32 fgpo;
 519 +
 520 +       fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
 521 +       ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
 522 +}
 523 +
 524 +static void ltq_spi_chipselect(struct spi_device *spi, int cs)
 525 +{
 526 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 527 +
 528 +       switch (cs) {
 529 +       case BITBANG_CS_ACTIVE:
 530 +               ltq_spi_bits_per_word_set(spi);
 531 +               ltq_spi_speed_set(spi);
 532 +               ltq_spi_clockmode_set(spi);
 533 +               ltq_spi_run_mode_set(hw);
 534 +               ltq_spi_internal_cs_activate(spi);
 535 +               break;
 536 +
 537 +       case BITBANG_CS_INACTIVE:
 538 +               ltq_spi_internal_cs_deactivate(spi);
 539 +               ltq_spi_config_mode_set(hw);
 540 +               break;
 541 +       }
 542 +}
 543 +
 544 +static int ltq_spi_setup_transfer(struct spi_device *spi,
 545 +                                 struct spi_transfer *t)
 546 +{
 547 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 548 +       u8 bits_per_word = spi->bits_per_word;
 549 +
 550 +       hw->curr_transfer = t;
 551 +
 552 +       if (t && t->bits_per_word)
 553 +               bits_per_word = t->bits_per_word;
 554 +
 555 +       if (bits_per_word > 32)
 556 +               return -EINVAL;
 557 +
 558 +       ltq_spi_config_mode_set(hw);
 559 +
 560 +       return 0;
 561 +}
 562 +
 563 +static int ltq_spi_setup(struct spi_device *spi)
 564 +{
 565 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 566 +       u32 gpocon, fgpo;
 567 +
 568 +       /* Set default word length to 8 if not set */
 569 +       if (!spi->bits_per_word)
 570 +               spi->bits_per_word = 8;
 571 +
 572 +       if (spi->bits_per_word > 32)
 573 +               return -EINVAL;
 574 +
 575 +       /*
 576 +        * Up to six GPIOs can be connected to the SPI module
 577 +        * via GPIO alternate function to control the chip select lines.
 578 +        */
 579 +       gpocon = (1 << (spi->chip_select +
 580 +                       LTQ_SPI_GPOCON_ISCSBN_SHIFT));
 581 +
 582 +       if (spi->mode & SPI_CS_HIGH)
 583 +               gpocon |= (1 << spi->chip_select);
 584 +
 585 +       fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT));
 586 +
 587 +       ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON);
 588 +       ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO);
 589 +
 590 +       return 0;
 591 +}
 592 +
 593 +static void ltq_spi_cleanup(struct spi_device *spi)
 594 +{
 595 +
 596 +}
 597 +
 598 +static void ltq_spi_txfifo_write(struct ltq_spi *hw)
 599 +{
 600 +       u32 fstat, data;
 601 +       u16 fifo_space;
 602 +
 603 +       /* Determine how much FIFOs are free for TX data */
 604 +       fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
 605 +       fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) &
 606 +                                       LTQ_SPI_FSTAT_TXFFL_MASK);
 607 +
 608 +       if (!fifo_space)
 609 +               return;
 610 +
 611 +       while (hw->tx_cnt < hw->len && fifo_space) {
 612 +               data = hw->get_tx(hw);
 613 +               ltq_spi_reg_write(hw, data, LTQ_SPI_TB);
 614 +               fifo_space--;
 615 +       }
 616 +}
 617 +
 618 +static void ltq_spi_rxfifo_read(struct ltq_spi *hw)
 619 +{
 620 +       u32 fstat, data, *rx32;
 621 +       u16 fifo_fill;
 622 +       u8 rxbv, shift, *rx8;
 623 +
 624 +       /* Determine how much FIFOs are filled with RX data */
 625 +       fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
 626 +       fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT)
 627 +                       & LTQ_SPI_FSTAT_RXFFL_MASK);
 628 +
 629 +       if (!fifo_fill)
 630 +               return;
 631 +
 632 +       /*
 633 +        * The 32 bit FIFO is always used completely independent from the
 634 +        * bits_per_word value. Thus four bytes have to be read at once
 635 +        * per FIFO.
 636 +        */
 637 +       rx32 = (u32 *) hw->rx;
 638 +       while (hw->len - hw->rx_cnt >= 4 && fifo_fill) {
 639 +               *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB);
 640 +               hw->rx_cnt += 4;
 641 +               hw->rx += 4;
 642 +               fifo_fill--;
 643 +       }
 644 +
 645 +       /*
 646 +        * If there are remaining bytes, read byte count from STAT.RXBV
 647 +        * register and read the data byte-wise.
 648 +        */
 649 +       while (fifo_fill && hw->rx_cnt < hw->len) {
 650 +               rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >>
 651 +                       LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK;
 652 +               data = ltq_spi_reg_read(hw, LTQ_SPI_RB);
 653 +
 654 +               shift = (rxbv - 1) * 8;
 655 +               rx8 = hw->rx;
 656 +
 657 +               while (rxbv) {
 658 +                       *rx8++ = (data >> shift) & 0xFF;
 659 +                       rxbv--;
 660 +                       shift -= 8;
 661 +                       hw->rx_cnt++;
 662 +                       hw->rx++;
 663 +               }
 664 +
 665 +               fifo_fill--;
 666 +       }
 667 +}
 668 +
 669 +static void ltq_spi_rxreq_set(struct ltq_spi *hw)
 670 +{
 671 +       u32 rxreq, rxreq_max, rxtodo;
 672 +
 673 +       rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK;
 674 +
 675 +       /*
 676 +        * In RX-only mode the serial clock is activated only after writing
 677 +        * the expected amount of RX bytes into RXREQ register.
 678 +        * To avoid receive overflows at high clocks it is better to request
 679 +        * only the amount of bytes that fits into all FIFOs. This value
 680 +        * depends on the FIFO size implemented in hardware.
 681 +        */
 682 +       rxreq = hw->len - hw->rx_cnt;
 683 +       rxreq_max = hw->rxfs << 2;
 684 +       rxreq = min(rxreq_max, rxreq);
 685 +
 686 +       if (!rxtodo && rxreq)
 687 +               ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ);
 688 +}
 689 +
 690 +static inline void ltq_spi_complete(struct ltq_spi *hw)
 691 +{
 692 +       complete(&hw->done);
 693 +}
 694 +
 695 +irqreturn_t ltq_spi_tx_irq(int irq, void *data)
 696 +{
 697 +       struct ltq_spi *hw = data;
 698 +       unsigned long flags;
 699 +       int completed = 0;
 700 +
 701 +       spin_lock_irqsave(&hw->lock, flags);
 702 +
 703 +       if (hw->tx_cnt < hw->len)
 704 +               ltq_spi_txfifo_write(hw);
 705 +
 706 +       if (hw->tx_cnt == hw->len)
 707 +               completed = 1;
 708 +
 709 +       spin_unlock_irqrestore(&hw->lock, flags);
 710 +
 711 +       if (completed)
 712 +               ltq_spi_complete(hw);
 713 +
 714 +       return IRQ_HANDLED;
 715 +}
 716 +
 717 +irqreturn_t ltq_spi_rx_irq(int irq, void *data)
 718 +{
 719 +       struct ltq_spi *hw = data;
 720 +       unsigned long flags;
 721 +       int completed = 0;
 722 +
 723 +       spin_lock_irqsave(&hw->lock, flags);
 724 +
 725 +       if (hw->rx_cnt < hw->len) {
 726 +               ltq_spi_rxfifo_read(hw);
 727 +
 728 +               if (hw->tx && hw->tx_cnt < hw->len)
 729 +                       ltq_spi_txfifo_write(hw);
 730 +       }
 731 +
 732 +       if (hw->rx_cnt == hw->len)
 733 +               completed = 1;
 734 +       else if (!hw->tx)
 735 +               ltq_spi_rxreq_set(hw);
 736 +
 737 +       spin_unlock_irqrestore(&hw->lock, flags);
 738 +
 739 +       if (completed)
 740 +               ltq_spi_complete(hw);
 741 +
 742 +       return IRQ_HANDLED;
 743 +}
 744 +
 745 +irqreturn_t ltq_spi_err_irq(int irq, void *data)
 746 +{
 747 +       struct ltq_spi *hw = data;
 748 +       unsigned long flags;
 749 +
 750 +       spin_lock_irqsave(&hw->lock, flags);
 751 +
 752 +       /* Disable all interrupts */
 753 +       ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
 754 +
 755 +       /* Clear all error flags */
 756 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
 757 +
 758 +       /* Flush FIFOs */
 759 +       ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
 760 +       ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
 761 +
 762 +       hw->status = -EIO;
 763 +       spin_unlock_irqrestore(&hw->lock, flags);
 764 +
 765 +       ltq_spi_complete(hw);
 766 +
 767 +       return IRQ_HANDLED;
 768 +}
 769 +
 770 +static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 771 +{
 772 +       struct ltq_spi *hw = ltq_spi_to_hw(spi);
 773 +       u32 irq_flags = 0;
 774 +
 775 +       hw->tx = t->tx_buf;
 776 +       hw->rx = t->rx_buf;
 777 +       hw->len = t->len;
 778 +       hw->tx_cnt = 0;
 779 +       hw->rx_cnt = 0;
 780 +       hw->status = 0;
 781 +       INIT_COMPLETION(hw->done);
 782 +
 783 +       ltq_spi_xmit_set(hw, t);
 784 +
 785 +       /* Enable error interrupts */
 786 +       ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
 787 +
 788 +       if (hw->tx) {
 789 +               /* Initially fill TX FIFO with as much data as possible */
 790 +               ltq_spi_txfifo_write(hw);
 791 +               irq_flags |= LTQ_SPI_IRNEN_T;
 792 +
 793 +               /* Always enable RX interrupt in Full Duplex mode */
 794 +               if (hw->rx)
 795 +                       irq_flags |= LTQ_SPI_IRNEN_R;
 796 +       } else if (hw->rx) {
 797 +               /* Start RX clock */
 798 +               ltq_spi_rxreq_set(hw);
 799 +
 800 +               /* Enable RX interrupt to receive data from RX FIFOs */
 801 +               irq_flags |= LTQ_SPI_IRNEN_R;
 802 +       }
 803 +
 804 +       /* Enable TX or RX interrupts */
 805 +       ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN);
 806 +       wait_for_completion_interruptible(&hw->done);
 807 +
 808 +       /* Disable all interrupts */
 809 +       ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN);
 810 +
 811 +       /*
 812 +        * Return length of current transfer for bitbang utility code if
 813 +        * no errors occured during transmission.
 814 +        */
 815 +       if (!hw->status)
 816 +               hw->status = hw->len;
 817 +
 818 +       return hw->status;
 819 +}
 820 +
 821 +static const struct ltq_spi_irq_map {
 822 +       char *name;
 823 +       irq_handler_t handler;
 824 +} ltq_spi_irqs[] = {
 825 +       { "spi_rx", ltq_spi_rx_irq },
 826 +       { "spi_tx", ltq_spi_tx_irq },
 827 +       { "spi_err", ltq_spi_err_irq },
 828 +};
 829 +
 830 +static int __devinit ltq_spi_probe(struct platform_device *pdev)
 831 +{
 832 +       struct resource irqres[3];
 833 +       struct spi_master *master;
 834 +       struct resource *r;
 835 +       struct ltq_spi *hw;
 836 +       int ret, i;
 837 +       u32 data, id;
 838 +
 839 +       if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 3) != 3) {
 840 +               dev_err(&pdev->dev, "IRQ settings missing in device tree\n");
 841 +               return -EINVAL;
 842 +       }
 843 +
 844 +       master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi));
 845 +       if (!master) {
 846 +               dev_err(&pdev->dev, "spi_alloc_master\n");
 847 +               ret = -ENOMEM;
 848 +               goto err;
 849 +       }
 850 +
 851 +       hw = spi_master_get_devdata(master);
 852 +
 853 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 854 +       if (r == NULL) {
 855 +               dev_err(&pdev->dev, "platform_get_resource\n");
 856 +               ret = -ENOENT;
 857 +               goto err_master;
 858 +       }
 859 +
 860 +       r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
 861 +                       pdev->name);
 862 +       if (!r) {
 863 +               dev_err(&pdev->dev, "failed to request memory region\n");
 864 +               ret = -ENXIO;
 865 +               goto err_master;
 866 +       }
 867 +
 868 +       hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r));
 869 +       if (!hw->base) {
 870 +               dev_err(&pdev->dev, "failed to remap memory region\n");
 871 +               ret = -ENXIO;
 872 +               goto err_master;
 873 +       }
 874 +
 875 +       memset(hw->irq, 0, sizeof(hw->irq));
 876 +       for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) {
 877 +               hw->irq[i] = irqres[i].start;
 878 +               ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler,
 879 +                                 0, ltq_spi_irqs[i].name, hw);
 880 +               if (ret) {
 881 +                       dev_err(&pdev->dev, "failed to request %s irq (%d)\n",
 882 +                                       ltq_spi_irqs[i].name, hw->irq[i]);
 883 +                       goto err_irq;
 884 +               }
 885 +       }
 886 +
 887 +       hw->fpiclk = clk_get_fpi();
 888 +       if (IS_ERR(hw->fpiclk)) {
 889 +               dev_err(&pdev->dev, "failed to get fpi clock\n");
 890 +               ret = PTR_ERR(hw->fpiclk);
 891 +               goto err_clk;
 892 +       }
 893 +
 894 +       hw->spiclk = clk_get(&pdev->dev, NULL);
 895 +       if (IS_ERR(hw->spiclk)) {
 896 +               dev_err(&pdev->dev, "failed to get spi clock gate\n");
 897 +               ret = PTR_ERR(hw->spiclk);
 898 +               goto err_clk;
 899 +       }
 900 +
 901 +       hw->bitbang.master = spi_master_get(master);
 902 +       hw->bitbang.chipselect = ltq_spi_chipselect;
 903 +       hw->bitbang.setup_transfer = ltq_spi_setup_transfer;
 904 +       hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs;
 905 +
 906 +       if (of_machine_is_compatible("lantiq,ase"))
 907 +               master->num_chipselect = 3;
 908 +       else
 909 +               master->num_chipselect = 6;
 910 +       master->bus_num = pdev->id;
 911 +       master->setup = ltq_spi_setup;
 912 +       master->cleanup = ltq_spi_cleanup;
 913 +       master->dev.of_node = pdev->dev.of_node;
 914 +
 915 +       hw->dev = &pdev->dev;
 916 +       init_completion(&hw->done);
 917 +       spin_lock_init(&hw->lock);
 918 +
 919 +       ltq_spi_hw_enable(hw);
 920 +
 921 +       /* Read module capabilities */
 922 +       id = ltq_spi_reg_read(hw, LTQ_SPI_ID);
 923 +       hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
 924 +       hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK;
 925 +       hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0;
 926 +
 927 +       ltq_spi_config_mode_set(hw);
 928 +
 929 +       /* Enable error checking, disable TX/RX, set idle value high */
 930 +       data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
 931 +           LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN |
 932 +           LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE;
 933 +       ltq_spi_reg_write(hw, data, LTQ_SPI_CON);
 934 +
 935 +       /* Enable master mode and clear error flags */
 936 +       ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS |
 937 +                         LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
 938 +
 939 +       /* Reset GPIO/CS registers */
 940 +       ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON);
 941 +       ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO);
 942 +
 943 +       /* Enable and flush FIFOs */
 944 +       ltq_spi_reset_fifos(hw);
 945 +
 946 +       ret = spi_bitbang_start(&hw->bitbang);
 947 +       if (ret) {
 948 +               dev_err(&pdev->dev, "spi_bitbang_start failed\n");
 949 +               goto err_bitbang;
 950 +       }
 951 +
 952 +       platform_set_drvdata(pdev, hw);
 953 +
 954 +       pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n",
 955 +               id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support);
 956 +
 957 +       return 0;
 958 +
 959 +err_bitbang:
 960 +       ltq_spi_hw_disable(hw);
 961 +
 962 +err_clk:
 963 +       if (hw->fpiclk)
 964 +               clk_put(hw->fpiclk);
 965 +       if (hw->spiclk)
 966 +               clk_put(hw->spiclk);
 967 +
 968 +err_irq:
 969 +       clk_put(hw->fpiclk);
 970 +
 971 +       for (; i > 0; i--)
 972 +               free_irq(hw->irq[i], hw);
 973 +
 974 +err_master:
 975 +       spi_master_put(master);
 976 +
 977 +err:
 978 +       return ret;
 979 +}
 980 +
 981 +static int __devexit ltq_spi_remove(struct platform_device *pdev)
 982 +{
 983 +       struct ltq_spi *hw = platform_get_drvdata(pdev);
 984 +       int ret, i;
 985 +
 986 +       ret = spi_bitbang_stop(&hw->bitbang);
 987 +       if (ret)
 988 +               return ret;
 989 +
 990 +       platform_set_drvdata(pdev, NULL);
 991 +
 992 +       ltq_spi_config_mode_set(hw);
 993 +       ltq_spi_hw_disable(hw);
 994 +
 995 +       for (i = 0; i < ARRAY_SIZE(hw->irq); i++)
 996 +               if (0 < hw->irq[i])
 997 +                       free_irq(hw->irq[i], hw);
 998 +
 999 +       if (hw->fpiclk)
1000 +               clk_put(hw->fpiclk);
1001 +       if (hw->spiclk)
1002 +               clk_put(hw->spiclk);
1003 +
1004 +       spi_master_put(hw->bitbang.master);
1005 +
1006 +       return 0;
1007 +}
1008 +
1009 +static const struct of_device_id ltq_spi_match[] = {
1010 +       { .compatible = "lantiq,spi-xway" },
1011 +       {},
1012 +};
1013 +MODULE_DEVICE_TABLE(of, ltq_spi_match);
1014 +
1015 +static struct platform_driver ltq_spi_driver = {
1016 +       .probe = ltq_spi_probe,
1017 +       .remove = __devexit_p(ltq_spi_remove),
1018 +       .driver = {
1019 +               .name = "spi-xway",
1020 +               .owner = THIS_MODULE,
1021 +               .of_match_table = ltq_spi_match,
1022 +       },
1023 +};
1024 +
1025 +module_platform_driver(ltq_spi_driver);
1026 +
1027 +MODULE_DESCRIPTION("Lantiq SoC SPI controller driver");
1028 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
1029 +MODULE_LICENSE("GPL");
1030 +MODULE_ALIAS("platform:spi-xway");
1031 --
1032 1.7.10.4
1033