target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
   5
   6 / {
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         compatible = "lantiq,xway", "lantiq,vr9";
  10
  11         aliases {
  12                 serial0 = &asc1;
  13         };
  14
  15         chosen {
  16                 stdout-path = "serial0:115200n8";
  17         };
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu@0 {
  24                         compatible = "mips,mips34Kc";
  25                         reg = <0>;
  26                 };
  27         };
  28
  29         cputemp {
  30                 compatible = "lantiq,cputemp";
  31         };
  32
  33         reboot {
  34                 compatible = "syscon-reboot";
  35
  36                 regmap = <&rcu0>;
  37                 offset = <0x10>;
  38                 mask = <0xe0000000>;
  39         };
  40
  41         biu@1f800000 {
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44                 compatible = "lantiq,biu", "simple-bus";
  45                 reg = <0x1f800000 0x800000>;
  46                 ranges = <0x0 0x1f800000 0x7fffff>;
  47
  48                 icu0: icu@80200 {
  49                         #address-cells = <0>;
  50                         #interrupt-cells = <1>;
  51                         interrupt-controller;
  52                         compatible = "lantiq,icu";
  53                         reg = <0x80200 0xc8     /* icu0 */
  54                                0x80300 0xc8>;   /* icu1 */
  55                 };
  56
  57                 watchdog@803f0 {
  58                         compatible = "lantiq,xrx100-wdt", "lantiq,xrx100-wdt";
  59                         reg = <0x803f0 0x10>;
  60
  61                         regmap = <&rcu0>;
  62                 };
  63         };
  64
  65         sram@1f000000 {
  66                 #address-cells = <1>;
  67                 #size-cells = <1>;
  68                 compatible = "lantiq,sram", "simple-bus";
  69                 reg = <0x1f000000 0x800000>;
  70                 ranges = <0x0 0x1f000000 0x7fffff>;
  71
  72                 eiu0: eiu@101000 {
  73                         #address-cells = <0>;
  74                         #interrupt-cells = <1>;
  75                         interrupt-controller;
  76                         compatible = "lantiq,eiu-xway";
  77                         reg = <0x101000 0x1000>;
  78                         interrupt-parent = <&icu0>;
  79                         lantiq,eiu-irqs = <166 135 66 40 41 42>;
  80                 };
  81
  82                 pmu0: pmu@102000 {
  83                         compatible = "lantiq,pmu-xway";
  84                         reg = <0x102000 0x1000>;
  85                 };
  86
  87                 cgu0: cgu@103000 {
  88                         compatible = "lantiq,cgu-xway";
  89                         reg = <0x103000 0x1000>;
  90                 };
  91
  92                 dcdc@106a00 {
  93                         compatible = "lantiq,dcdc-xrx200";
  94                         reg = <0x106a00 0x200>;
  95                 };
  96
  97                 vmmc: vmmc@107000 {
  98                         status = "disabled";
  99                         compatible = "lantiq,vmmc-xway";
 100                         reg = <0x107000 0x300>;
 101                         interrupt-parent = <&icu0>;
 102                         interrupts = <150 151 152 153 154 155>;
 103                 };
 104
 105                 pcie0_phy: phy@106800 {
 106                         compatible = "lantiq,vrx200-pcie-phy";
 107                         reg = <0x106800 0x100>;
 108                         lantiq,rcu = <&rcu0>;
 109                         lantiq,rcu-endian-offset = <0x4c>;
 110                         lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
 111                         big-endian;
 112                         resets = <&reset0 12 24>, <&reset0 22 22>;
 113                         reset-names = "phy", "pcie";
 114                         #phy-cells = <1>;
 115                 };
 116
 117                 rcu0: rcu@203000 {
 118                         #address-cells = <1>;
 119                         #size-cells = <1>;
 120                         compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
 121                         reg = <0x203000 0x100>;
 122                         ranges = <0x0 0x203000 0x100>;
 123                         big-endian;
 124
 125                         gphy0: gphy@20 {
 126                                 compatible = "lantiq,xrx200-gphy";
 127                                 reg = <0x20 0x4>;
 128
 129                                 resets = <&reset0 31 30>, <&reset1 7 7>;
 130                                 reset-names = "gphy", "gphy2";
 131                         };
 132
 133                         gphy1: gphy@68 {
 134                                 compatible = "lantiq,xrx200-gphy";
 135                                 reg = <0x68 0x4>;
 136
 137                                 resets = <&reset0 29 28>, <&reset1 6 6>;
 138                                 reset-names = "gphy", "gphy2";
 139                         };
 140
 141                         reset0: reset-controller@10 {
 142                                 compatible = "lantiq,xrx200-reset";
 143                                 reg = <0x10 4>, <0x14 4>;
 144
 145                                 #reset-cells = <2>;
 146                         };
 147
 148                         reset1: reset-controller@48 {
 149                                 compatible = "lantiq,xrx200-reset";
 150                                 reg = <0x48 4>, <0x24 4>;
 151
 152                                 #reset-cells = <2>;
 153                         };
 154
 155                         usb_phy0: usb2-phy@18 {
 156                                 compatible = "lantiq,xrx200-usb2-phy";
 157                                 reg = <0x18 4>, <0x38 4>;
 158                                 status = "disabled";
 159
 160                                 resets = <&reset1 4 4>, <&reset0 4 4>;
 161                                 reset-names = "phy", "ctrl";
 162                                 #phy-cells = <0>;
 163                         };
 164
 165                         usb_phy1: usb2-phy@34 {
 166                                 compatible = "lantiq,xrx200-usb2-phy";
 167                                 reg = <0x34 4>, <0x3c 4>;
 168                                 status = "disabled";
 169
 170                                 resets = <&reset1 5 5>, <&reset0 4 4>;
 171                                 reset-names = "phy", "ctrl";
 172                                 #phy-cells = <0>;
 173                         };
 174                 };
 175         };
 176
 177         fpi@10000000 {
 178                 compatible = "lantiq,xrx200-fpi", "simple-bus";
 179                 ranges = <0x0 0x10000000 0xf000000>;
 180                 reg =   <0x1f400000 0x1000>,
 181                         <0x10000000 0xf000000>;
 182                 regmap = <&rcu0>;
 183                 offset-endianness = <0x4c>;
 184                 #address-cells = <1>;
 185                 #size-cells = <1>;
 186
 187                 localbus: localbus@0 {
 188                         #address-cells = <2>;
 189                         #size-cells = <1>;
 190                         ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
 191                                 1 0 0x4000000 0x4000010>; /* addsel1 */
 192                         compatible = "lantiq,localbus", "simple-mfd";
 193                 };
 194
 195                 gptu@e100a00 {
 196                         compatible = "lantiq,gptu-xway";
 197                         reg = <0xe100a00 0x100>;
 198                         interrupt-parent = <&icu0>;
 199                         interrupts = <126 127 128 129 130 131>;
 200                 };
 201
 202                 usif: usif@da00000 {
 203                         compatible = "lantiq,usif";
 204                         reg = <0xda00000 0x1000000>;
 205                         interrupt-parent = <&icu0>;
 206                         interrupts = <29 125 107 108 109 110>;
 207                         status = "disabled";
 208                 };
 209
 210                 spi: spi@e100800 {
 211                         compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
 212                         reg = <0xe100800 0x100>;
 213                         interrupt-parent = <&icu0>;
 214                         interrupts = <22 23 24>;
 215                         interrupt-names = "spi_rx", "spi_tx", "spi_err",
 216                                         "spi_frm";
 217                         #address-cells = <1>;
 218                         #size-cells = <0>;
 219                         pinctrl-names = "default";
 220                         pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>;
 221                         status = "disabled";
 222                 };
 223
 224                 gpio: pinmux@e100b10 {
 225                         compatible = "lantiq,xrx200-pinctrl";
 226                         #gpio-cells = <2>;
 227                         gpio-controller;
 228                         gpio-ranges = <&gpio 0 0 50>;
 229                         reg = <0xe100b10 0xa0>;
 230
 231                         gphy0_led0_pins: gphy0-led0 {
 232                                 mux {
 233                                         lantiq,groups = "gphy0 led0";
 234                                         lantiq,function = "gphy";
 235                                         lantiq,open-drain = <0>;
 236                                         lantiq,pull = <2>;
 237                                         lantiq,output = <1>;
 238                                 };
 239                         };
 240
 241                         gphy0_led1_pins: gphy0-led1 {
 242                                 mux {
 243                                         lantiq,groups = "gphy0 led1";
 244                                         lantiq,function = "gphy";
 245                                         lantiq,open-drain = <0>;
 246                                         lantiq,pull = <2>;
 247                                         lantiq,output = <1>;
 248                                 };
 249                         };
 250
 251                         gphy0_led2_pins: gphy0-led2 {
 252                                 mux {
 253                                         lantiq,groups = "gphy0 led2";
 254                                         lantiq,function = "gphy";
 255                                         lantiq,open-drain = <0>;
 256                                         lantiq,pull = <2>;
 257                                         lantiq,output = <1>;
 258                                 };
 259                         };
 260
 261                         gphy1_led0_pins: gphy1-led0 {
 262                                 mux {
 263                                         lantiq,groups = "gphy1 led0";
 264                                         lantiq,function = "gphy";
 265                                         lantiq,open-drain = <0>;
 266                                         lantiq,pull = <2>;
 267                                         lantiq,output = <1>;
 268                                 };
 269                         };
 270
 271                         gphy1_led1_pins: gphy1-led1 {
 272                                 mux {
 273                                         lantiq,groups = "gphy1 led1";
 274                                         lantiq,function = "gphy";
 275                                         lantiq,open-drain = <0>;
 276                                         lantiq,pull = <2>;
 277                                         lantiq,output = <1>;
 278                                 };
 279                         };
 280
 281                         gphy1_led2_pins: gphy1-led2 {
 282                                 mux {
 283                                         lantiq,groups = "gphy1 led2";
 284                                         lantiq,function = "gphy";
 285                                         lantiq,open-drain = <0>;
 286                                         lantiq,pull = <2>;
 287                                         lantiq,output = <1>;
 288                                 };
 289                         };
 290
 291                         mdio_pins: mdio-pins {
 292                                 mux {
 293                                         lantiq,groups = "mdio";
 294                                         lantiq,function = "mdio";
 295                                 };
 296                         };
 297
 298                         nand_pins: nand-pins {
 299                                 mux-0 {
 300                                         lantiq,groups = "nand cle", "nand ale",
 301                                                         "nand rd";
 302                                         lantiq,function = "ebu";
 303                                         lantiq,output = <1>;
 304                                         lantiq,open-drain = <0>;
 305                                         lantiq,pull = <0>;
 306                                 };
 307                                 mux-1 {
 308                                         lantiq,groups = "nand rdy";
 309                                         lantiq,function = "ebu";
 310                                         lantiq,output = <0>;
 311                                         lantiq,pull = <2>;
 312                                 };
 313                         };
 314
 315                         nand_cs1_pins: nand-cs1 {
 316                                 mux {
 317                                         lantiq,groups = "nand cs1";
 318                                         lantiq,function = "ebu";
 319                                         lantiq,open-drain = <0>;
 320                                         lantiq,pull = <0>;
 321                                 };
 322                         };
 323
 324                         pci_gnt1_pins: pci-gnt1 {
 325                                 mux {
 326                                         lantiq,groups = "gnt1";
 327                                         lantiq,function = "pci";
 328                                         lantiq,output = <1>;
 329                                         lantiq,open-drain = <0>;
 330                                         lantiq,pull = <0>;
 331                                 };
 332                         };
 333
 334                         pci_req1_pins: pci-req1 {
 335                                 mux {
 336                                         lantiq,groups = "req1";
 337                                         lantiq,function = "pci";
 338                                         lantiq,output = <0>;
 339                                         lantiq,open-drain = <1>;
 340                                         lantiq,pull = <2>;
 341                                 };
 342                         };
 343
 344                         spi_pins: spi-pins {
 345                                 mux-0 {
 346                                         lantiq,groups = "spi_di";
 347                                         lantiq,function = "spi";
 348                                 };
 349                                 mux-1 {
 350                                         lantiq,groups = "spi_do", "spi_clk";
 351                                         lantiq,function = "spi";
 352                                         lantiq,output = <1>;
 353                                 };
 354                         };
 355
 356                         spi_cs4_pins: spi-cs4 {
 357                                 mux {
 358                                         lantiq,groups = "spi_cs4";
 359                                         lantiq,function = "spi";
 360                                         lantiq,output = <1>;
 361                                 };
 362                         };
 363
 364                         stp_pins: stp-pins {
 365                                 mux {
 366                                         lantiq,groups = "stp";
 367                                         lantiq,function = "stp";
 368                                         lantiq,pull = <0>;
 369                                         lantiq,open-drain = <0>;
 370                                         lantiq,output = <1>;
 371                                 };
 372                         };
 373                 };
 374
 375                 stp: stp@e100bb0 {
 376                         status = "disabled";
 377                         compatible = "lantiq,gpio-stp-xway";
 378                         reg = <0xe100bb0 0x40>;
 379                         #gpio-cells = <2>;
 380                         gpio-controller;
 381
 382                         pinctrl-0 = <&stp_pins>;
 383                         pinctrl-names = "default";
 384
 385                         lantiq,shadow = <0xffffff>;
 386                         lantiq,groups = <0x7>;
 387                         lantiq,dsl = <0x0>;
 388                         lantiq,phy1 = <0x0>;
 389                         lantiq,phy2 = <0x0>;
 390                 };
 391
 392                 asc1: serial@e100c00 {
 393                         compatible = "lantiq,asc";
 394                         reg = <0xe100c00 0x400>;
 395                         interrupt-parent = <&icu0>;
 396                         interrupts = <112 113 114>;
 397                 };
 398
 399                 deu@e103100 {
 400                         compatible = "lantiq,deu-xrx200";
 401                         reg = <0xe103100 0xf00>;
 402                 };
 403
 404                 dma0: dma@e104100 {
 405                         compatible = "lantiq,dma-xway";
 406                         reg = <0xe104100 0x800>;
 407                 };
 408
 409                 ebu0: ebu@e105300 {
 410                         compatible = "lantiq,ebu-xway";
 411                         reg = <0xe105300 0x100>;
 412                 };
 413
 414                 usb0: usb@e101000 {
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                         status = "disabled";
 418                         compatible = "lantiq,xrx200-usb";
 419                         reg = <0xe101000 0x1000
 420                                 0xe120000 0x3f000>;
 421                         interrupt-parent = <&icu0>;
 422                         interrupts = <62 91>;
 423                         dr_mode = "host";
 424                         phys = <&usb_phy0>;
 425                         phy-names = "usb2-phy";
 426
 427                         ehci_port1: port@1 {
 428                                 reg = <1>;
 429                                 #trigger-source-cells = <0>;
 430                         };
 431                 };
 432
 433                 usb1: usb@e106000 {
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         status = "disabled";
 437                         compatible = "lantiq,xrx200-usb";
 438                         reg = <0xe106000 0x1000>;
 439                         interrupt-parent = <&icu0>;
 440                         interrupts = <91>;
 441                         dr_mode = "host";
 442                         phys = <&usb_phy1>;
 443                         phy-names = "usb2-phy";
 444
 445                         ehci_port2: port@1 {
 446                                 reg = <1>;
 447                                 #trigger-source-cells = <0>;
 448                         };
 449                 };
 450
 451                 eth0: eth@e108000 {
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454                         compatible = "lantiq,xrx200-net";
 455                         reg = < 0xe108000 0x3000 /* switch */
 456                                 0xe10b100 0x70 /* mdio */
 457                                 0xe10b1d8 0x30 /* mii */
 458                                 0xe10b308 0x30 /* pmac */
 459                         >;
 460                         interrupt-parent = <&icu0>;
 461                         interrupts = <75 73 72>;
 462                         resets = <&reset0 21 16>, <&reset0 8 8>;
 463                         reset-names = "switch", "ppe";
 464                         lantiq,phys = <&gphy0>, <&gphy1>;
 465                         pinctrl-0 = <&mdio_pins>;
 466                         pinctrl-names = "default";
 467                 };
 468
 469                 mei@e116000 {
 470                         compatible = "lantiq,mei-xrx200";
 471                         reg = <0xe116000 0x9c>;
 472                         interrupt-parent = <&icu0>;
 473                         interrupts = <63>;
 474                 };
 475
 476                 ppe@e234000 {
 477                         compatible = "lantiq,ppe-xrx200";
 478                         reg = <0xe234000 0x3ffd>;
 479                         interrupt-parent = <&icu0>;
 480                         interrupts = <96>;
 481                         resets = <&reset0 3 3>, <&reset0 11 11>, <&reset0 23 23>;
 482                         reset-names = "dsp", "dfe", "tc";
 483                 };
 484
 485                 pcie0: pcie@d900000 {
 486                         status = "disabled";
 487
 488                         compatible = "lantiq,pcie-xrx200";
 489
 490                         #interrupt-cells = <1>;
 491                         #size-cells = <2>;
 492                         #address-cells = <3>;
 493
 494                         reg = <0xd900000 0x1000>;
 495
 496                         ranges = <0x2000000 0 0x1c000000 0xc000000 0 0x1000000>;
 497
 498                         interrupt-parent = <&icu0>;
 499                         interrupts = <161 144>;
 500
 501                         phys = <&pcie0_phy LANTIQ_PCIE_PHY_MODE_36MHZ>;
 502                         phy-names = "pcie";
 503
 504                         resets = <&reset0 22 22>;
 505
 506                         lantiq,rcu = <&rcu0>;
 507
 508                         device_type = "pci";
 509
 510                         pcie_bridge0: bridge@0 {
 511                                 #size-cells = <2>;
 512                                 #address-cells = <3>;
 513                                 reg = <0 0 0 0 0>;
 514                                 ranges;
 515                         };
 516                 };
 517
 518                 pci0: pci@e105400 {
 519                         status = "disabled";
 520
 521                         #address-cells = <3>;
 522                         #size-cells = <2>;
 523                         #interrupt-cells = <1>;
 524                         compatible = "lantiq,pci-xway";
 525                         bus-range = <0x0 0x0>;
 526                         ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000   /* pci memory */
 527                                 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */
 528
 529                         reg = <0xe105400 0x400>, <0x7000000 0x8000>;
 530                         reg-names = "ctrl", "config";
 531
 532                         lantiq,bus-clock = <33333333>;
 533                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 534                         interrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */
 535                         req-mask = <0x1>; /* GNT1 */
 536
 537                         resets = <&reset0 13 13>;
 538                         reset-names = "pci";
 539
 540                         device_type = "pci";
 541                 };
 542         };
 543
 544         vdsl {
 545                 compatible = "lantiq,vdsl-vrx200";
 546         };
 547 };