lantiq: specify the PCIe controller's interrupt, size and address cells
[openwrt/staging/blogic.git] / target / linux / lantiq / dts / vr9.dtsi
1 #include <dt-bindings/gpio/gpio.h>
2
3 / {
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "lantiq,xway", "lantiq,vr9";
7
8 cpus {
9 cpu@0 {
10 compatible = "mips,mips34Kc";
11 };
12 };
13
14 memory@0 {
15 device_type = "memory";
16 };
17
18 cputemp@0 {
19 compatible = "lantiq,cputemp";
20 };
21
22 biu@1F800000 {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 compatible = "lantiq,biu", "simple-bus";
26 reg = <0x1F800000 0x800000>;
27 ranges = <0x0 0x1F800000 0x7FFFFF>;
28
29 icu0: icu@80200 {
30 #interrupt-cells = <1>;
31 interrupt-controller;
32 compatible = "lantiq,icu";
33 reg = <0x80200 0x28
34 0x80228 0x28
35 0x80250 0x28
36 0x80278 0x28
37 0x802a0 0x28>;
38 };
39
40 watchdog@803F0 {
41 compatible = "lantiq,wdt";
42 reg = <0x803F0 0x10>;
43 };
44 };
45
46 sram@1F000000 {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "lantiq,sram", "simple-bus";
50 reg = <0x1F000000 0x800000>;
51 ranges = <0x0 0x1F000000 0x7FFFFF>;
52
53 eiu0: eiu@101000 {
54 #interrupt-cells = <1>;
55 interrupt-controller;
56 compatible = "lantiq,eiu-xway";
57 reg = <0x101000 0x1000>;
58 interrupt-parent = <&icu0>;
59 lantiq,eiu-irqs = <166 135 66 40 41 42>;
60 };
61
62 pmu0: pmu@102000 {
63 compatible = "lantiq,pmu-xway";
64 reg = <0x102000 0x1000>;
65 };
66
67 cgu0: cgu@103000 {
68 compatible = "lantiq,cgu-xway";
69 reg = <0x103000 0x1000>;
70 };
71
72 dcdc@106a00 {
73 compatible = "lantiq,dcdc-xrx200";
74 reg = <0x106a00 0x200>;
75 };
76
77 vmmc@107000 {
78 status = "disabled";
79 compatible = "lantiq,vmmc-xway";
80 reg = <0x103000 0x400>;
81 interrupt-parent = <&icu0>;
82 interrupts = <150 151 152 153 154 155>;
83 };
84
85 rcu0: rcu@203000 {
86 compatible = "lantiq,rcu-xrx200";
87 reg = <0x203000 0x1000>;
88 /* irq for thermal sensor */
89 interrupt-parent = <&icu0>;
90 interrupts = <115>;
91 };
92
93 xbar0: xbar@400000 {
94 compatible = "lantiq,xbar-xway";
95 reg = <0x400000 0x1000>;
96 };
97 };
98
99 fpi@10000000 {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 compatible = "lantiq,fpi", "simple-bus";
103 ranges = <0x0 0x10000000 0xEEFFFFF>;
104 reg = <0x10000000 0xEF00000>;
105
106 localbus@0 {
107 #address-cells = <2>;
108 #size-cells = <1>;
109 ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
110 1 0 0x4000000 0x4000010>; /* addsel1 */
111 compatible = "lantiq,localbus", "simple-bus";
112 };
113
114 gptu@E100A00 {
115 compatible = "lantiq,gptu-xway";
116 reg = <0xE100A00 0x100>;
117 interrupt-parent = <&icu0>;
118 interrupts = <126 127 128 129 130 131>;
119 };
120
121 asc0: serial@E100400 {
122 compatible = "lantiq,asc";
123 reg = <0xE100400 0x400>;
124 interrupt-parent = <&icu0>;
125 interrupts = <104 105 106>;
126 status = "disabled";
127 };
128
129 spi: spi@E100800 {
130 compatible = "lantiq,xrx200-spi";
131 reg = <0xE100800 0x100>;
132 interrupt-parent = <&icu0>;
133 interrupts = <22 23 24>;
134 interrupt-names = "spi_rx", "spi_tx", "spi_err",
135 "spi_frm";
136 #address-cells = <1>;
137 #size-cells = <1>;
138 status = "disabled";
139 };
140
141 gpio: pinmux@E100B10 {
142 compatible = "lantiq,xrx200-pinctrl";
143 #gpio-cells = <2>;
144 gpio-controller;
145 reg = <0xE100B10 0xA0>;
146 };
147
148 asc1: serial@E100C00 {
149 compatible = "lantiq,asc";
150 reg = <0xE100C00 0x400>;
151 interrupt-parent = <&icu0>;
152 interrupts = <112 113 114>;
153 };
154
155 deu@E103100 {
156 compatible = "lantiq,deu-xrx200";
157 reg = <0xE103100 0xf00>;
158 };
159
160 dma0: dma@E104100 {
161 compatible = "lantiq,dma-xway";
162 reg = <0xE104100 0x800>;
163 };
164
165 ebu0: ebu@E105300 {
166 compatible = "lantiq,ebu-xway";
167 reg = <0xE105300 0x100>;
168 };
169
170 ifxhcd@E101000 {
171 status = "disabled";
172 compatible = "lantiq,ifxhcd-xrx200", "lantiq,ifxhcd-xrx200-dwc2";
173 reg = <0xE101000 0x1000
174 0xE120000 0x3f000>;
175 interrupt-parent = <&icu0>;
176 interrupts = <62 91>;
177 };
178
179 ifxhcd@E106000 {
180 status = "disabled";
181 compatible = "lantiq,ifxhcd-xrx200-dwc2";
182 reg = <0xE106000 0x1000>;
183 interrupt-parent = <&icu0>;
184 interrupts = <91>;
185 };
186
187 eth0: eth@E108000 {
188 #address-cells = <1>;
189 #size-cells = <0>;
190 compatible = "lantiq,xrx200-net";
191 reg = < 0xE108000 0x3000 /* switch */
192 0xE10B100 0x70 /* mdio */
193 0xE10B1D8 0x30 /* mii */
194 0xE10B308 0x30 /* pmac */
195 >;
196 interrupt-parent = <&icu0>;
197 interrupts = <75 73 72>;
198 };
199
200 mei@E116000 {
201 compatible = "lantiq,mei-xrx200";
202 reg = <0xE116000 0x9c>;
203 interrupt-parent = <&icu0>;
204 interrupts = <63>;
205 };
206
207 ppe@E234000 {
208 compatible = "lantiq,ppe-xrx200";
209 interrupt-parent = <&icu0>;
210 interrupts = <96>;
211 };
212
213 pcie0: pcie@d900000 {
214 compatible = "lantiq,pcie-xrx200";
215
216 #interrupt-cells = <1>;
217 #size-cells = <2>;
218 #address-cells = <3>;
219
220 interrupt-parent = <&icu0>;
221 interrupts = <161 144>;
222
223 device_type = "pci";
224
225 gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
226 };
227
228 pci0: pci@E105400 {
229 status = "disabled";
230
231 #address-cells = <3>;
232 #size-cells = <2>;
233 #interrupt-cells = <1>;
234 compatible = "lantiq,pci-xway";
235 bus-range = <0x0 0x0>;
236 ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
237 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
238 reg = <0x7000000 0x8000 /* config space */
239 0xE105400 0x400>; /* pci bridge */
240 lantiq,bus-clock = <33333333>;
241 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
242 interrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */
243 req-mask = <0x1>; /* GNT1 */
244 };
245 };
246
247 vdsl {
248 compatible = "lantiq,vdsl-vrx200";
249 };
250 };