projects / openwrt / staging / hauke.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ixp4xx: upgrade to 5.15
[openwrt/staging/hauke.git] / target / linux / ixp4xx / patches-5.15 / 0023-5.18-ARM-ixp4xx-Drop-all-common-code.patch
1 From 18b3b7b323196c11bc7e6cd28655b46482b2d33c Mon Sep 17 00:00:00 2001
2 From: Linus Walleij <linus.walleij@linaro.org>
3 Date: Fri, 11 Feb 2022 23:32:37 +0100
4 Subject: [PATCH 13/14] ARM: ixp4xx: Drop all common code
5
6 After moving away from all the code we depend on in common we can
7 get a clean device tree boot and delete the common code in
8 arch/arm/mach-ixp4xx/common.c altogether.
9
10 Two physical register addresses remain in use, just copy these
11 verbatim into uncompress.h.
12
13 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
14 Link: https://lore.kernel.org/r/20220211223238.648934-13-linus.walleij@linaro.org
15 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
16 ---
17 arch/arm/mach-ixp4xx/Makefile | 2 +-
18 arch/arm/mach-ixp4xx/common.c | 331 ------------------
19 arch/arm/mach-ixp4xx/include/mach/hardware.h | 26 --
20 .../mach-ixp4xx/include/mach/ixp4xx-regs.h | 303 ----------------
21 arch/arm/mach-ixp4xx/include/mach/platform.h | 98 ------
22 .../arm/mach-ixp4xx/include/mach/uncompress.h | 4 +-
23 arch/arm/mach-ixp4xx/irqs.h | 64 ----
24 drivers/crypto/ixp4xx_crypto.c | 1 -
25 drivers/net/ethernet/xscale/ptp_ixp46x.c | 1 -
26 9 files changed, 4 insertions(+), 826 deletions(-)
27 delete mode 100644 arch/arm/mach-ixp4xx/common.c
28 delete mode 100644 arch/arm/mach-ixp4xx/include/mach/hardware.h
29 delete mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
30 delete mode 100644 arch/arm/mach-ixp4xx/include/mach/platform.h
31 delete mode 100644 arch/arm/mach-ixp4xx/irqs.h
32
33 diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
34 index 4ebe35227bf6..3d1c9d854c7f 100644
35 --- a/arch/arm/mach-ixp4xx/Makefile
36 +++ b/arch/arm/mach-ixp4xx/Makefile
37 @@ -1,2 +1,2 @@
38 # SPDX-License-Identifier: GPL-2.0
39 -obj-y += ixp4xx-of.o common.o
40 +obj-y += ixp4xx-of.o
41 diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
42 deleted file mode 100644
43 index 310e1602fbfc..000000000000
44 --- a/arch/arm/mach-ixp4xx/common.c
45 +++ /dev/null
46 @@ -1,331 +0,0 @@
47 -/*
48 - * arch/arm/mach-ixp4xx/common.c
49 - *
50 - * Generic code shared across all IXP4XX platforms
51 - *
52 - * Maintainer: Deepak Saxena <dsaxena@plexity.net>
53 - *
54 - * Copyright 2002 (c) Intel Corporation
55 - * Copyright 2003-2004 (c) MontaVista, Software, Inc.
56 - *
57 - * This file is licensed under the terms of the GNU General Public
58 - * License version 2. This program is licensed "as is" without any
59 - * warranty of any kind, whether express or implied.
60 - */
61 -
62 -#include <linux/kernel.h>
63 -#include <linux/mm.h>
64 -#include <linux/init.h>
65 -#include <linux/serial.h>
66 -#include <linux/tty.h>
67 -#include <linux/platform_device.h>
68 -#include <linux/serial_core.h>
69 -#include <linux/interrupt.h>
70 -#include <linux/bitops.h>
71 -#include <linux/io.h>
72 -#include <linux/export.h>
73 -#include <linux/cpu.h>
74 -#include <linux/pci.h>
75 -#include <linux/sched_clock.h>
76 -#include <linux/soc/ixp4xx/cpu.h>
77 -#include <linux/irqchip/irq-ixp4xx.h>
78 -#include <linux/platform_data/timer-ixp4xx.h>
79 -#include <mach/hardware.h>
80 -#include <linux/uaccess.h>
81 -#include <asm/page.h>
82 -#include <asm/exception.h>
83 -#include <asm/irq.h>
84 -#include <asm/system_misc.h>
85 -#include <asm/mach/map.h>
86 -#include <asm/mach/irq.h>
87 -#include <asm/mach/time.h>
88 -
89 -#include "irqs.h"
90 -
91 -#define IXP4XX_TIMER_FREQ 66666000
92 -
93 -/*************************************************************************
94 - * IXP4xx chipset I/O mapping
95 - *************************************************************************/
96 -static struct map_desc ixp4xx_io_desc[] __initdata = {
97 - { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
98 - .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
99 - .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
100 - .length = IXP4XX_PERIPHERAL_REGION_SIZE,
101 - .type = MT_DEVICE
102 - }, { /* Expansion Bus Config Registers */
103 - .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
104 - .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
105 - .length = IXP4XX_EXP_CFG_REGION_SIZE,
106 - .type = MT_DEVICE
107 - }, { /* PCI Registers */
108 - .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
109 - .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
110 - .length = IXP4XX_PCI_CFG_REGION_SIZE,
111 - .type = MT_DEVICE
112 - },
113 -};
114 -
115 -void __init ixp4xx_map_io(void)
116 -{
117 - iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
118 -}
119 -
120 -void __init ixp4xx_init_irq(void)
121 -{
122 - /*
123 - * ixp4xx does not implement the XScale PWRMODE register
124 - * so it must not call cpu_do_idle().
125 - */
126 - cpu_idle_poll_ctrl(true);
127 -
128 - ixp4xx_irq_init(IXP4XX_INTC_BASE_PHYS,
129 - (cpu_is_ixp46x() || cpu_is_ixp43x()));
130 -}
131 -
132 -void __init ixp4xx_timer_init(void)
133 -{
134 - return ixp4xx_timer_setup(IXP4XX_TIMER_BASE_PHYS,
135 - IRQ_IXP4XX_TIMER1,
136 - IXP4XX_TIMER_FREQ);
137 -}
138 -
139 -static struct resource ixp4xx_udc_resources[] = {
140 - [0] = {
141 - .start = 0xc800b000,
142 - .end = 0xc800bfff,
143 - .flags = IORESOURCE_MEM,
144 - },
145 - [1] = {
146 - .start = IRQ_IXP4XX_USB,
147 - .end = IRQ_IXP4XX_USB,
148 - .flags = IORESOURCE_IRQ,
149 - },
150 -};
151 -
152 -static struct resource ixp4xx_gpio_resource[] = {
153 - {
154 - .start = IXP4XX_GPIO_BASE_PHYS,
155 - .end = IXP4XX_GPIO_BASE_PHYS + 0xfff,
156 - .flags = IORESOURCE_MEM,
157 - },
158 -};
159 -
160 -static struct platform_device ixp4xx_gpio_device = {
161 - .name = "ixp4xx-gpio",
162 - .id = -1,
163 - .dev = {
164 - .coherent_dma_mask = DMA_BIT_MASK(32),
165 - },
166 - .resource = ixp4xx_gpio_resource,
167 - .num_resources = ARRAY_SIZE(ixp4xx_gpio_resource),
168 -};
169 -
170 -/*
171 - * USB device controller. The IXP4xx uses the same controller as PXA25X,
172 - * so we just use the same device.
173 - */
174 -static struct platform_device ixp4xx_udc_device = {
175 - .name = "pxa25x-udc",
176 - .id = -1,
177 - .num_resources = 2,
178 - .resource = ixp4xx_udc_resources,
179 -};
180 -
181 -static struct resource ixp4xx_npe_resources[] = {
182 - {
183 - .start = IXP4XX_NPEA_BASE_PHYS,
184 - .end = IXP4XX_NPEA_BASE_PHYS + 0xfff,
185 - .flags = IORESOURCE_MEM,
186 - },
187 - {
188 - .start = IXP4XX_NPEB_BASE_PHYS,
189 - .end = IXP4XX_NPEB_BASE_PHYS + 0xfff,
190 - .flags = IORESOURCE_MEM,
191 - },
192 - {
193 - .start = IXP4XX_NPEC_BASE_PHYS,
194 - .end = IXP4XX_NPEC_BASE_PHYS + 0xfff,
195 - .flags = IORESOURCE_MEM,
196 - },
197 -
198 -};
199 -
200 -static struct platform_device ixp4xx_npe_device = {
201 - .name = "ixp4xx-npe",
202 - .id = -1,
203 - .num_resources = ARRAY_SIZE(ixp4xx_npe_resources),
204 - .resource = ixp4xx_npe_resources,
205 -};
206 -
207 -static struct resource ixp4xx_qmgr_resources[] = {
208 - {
209 - .start = IXP4XX_QMGR_BASE_PHYS,
210 - .end = IXP4XX_QMGR_BASE_PHYS + 0x3fff,
211 - .flags = IORESOURCE_MEM,
212 - },
213 - {
214 - .start = IRQ_IXP4XX_QM1,
215 - .end = IRQ_IXP4XX_QM1,
216 - .flags = IORESOURCE_IRQ,
217 - },
218 - {
219 - .start = IRQ_IXP4XX_QM2,
220 - .end = IRQ_IXP4XX_QM2,
221 - .flags = IORESOURCE_IRQ,
222 - },
223 -};
224 -
225 -static struct platform_device ixp4xx_qmgr_device = {
226 - .name = "ixp4xx-qmgr",
227 - .id = -1,
228 - .num_resources = ARRAY_SIZE(ixp4xx_qmgr_resources),
229 - .resource = ixp4xx_qmgr_resources,
230 -};
231 -
232 -static struct platform_device *ixp4xx_devices[] __initdata = {
233 - &ixp4xx_npe_device,
234 - &ixp4xx_qmgr_device,
235 - &ixp4xx_gpio_device,
236 - &ixp4xx_udc_device,
237 -};
238 -
239 -static struct resource ixp46x_i2c_resources[] = {
240 - [0] = {
241 - .start = 0xc8011000,
242 - .end = 0xc801101c,
243 - .flags = IORESOURCE_MEM,
244 - },
245 - [1] = {
246 - .start = IRQ_IXP4XX_I2C,
247 - .end = IRQ_IXP4XX_I2C,
248 - .flags = IORESOURCE_IRQ
249 - }
250 -};
251 -
252 -/* A single 32-bit register on IXP46x */
253 -#define IXP4XX_HWRANDOM_BASE_PHYS 0x70002100
254 -
255 -static struct resource ixp46x_hwrandom_resource[] = {
256 - {
257 - .start = IXP4XX_HWRANDOM_BASE_PHYS,
258 - .end = IXP4XX_HWRANDOM_BASE_PHYS + 0x3,
259 - .flags = IORESOURCE_MEM,
260 - },
261 -};
262 -
263 -static struct platform_device ixp46x_hwrandom_device = {
264 - .name = "ixp4xx-hwrandom",
265 - .id = -1,
266 - .dev = {
267 - .coherent_dma_mask = DMA_BIT_MASK(32),
268 - },
269 - .resource = ixp46x_hwrandom_resource,
270 - .num_resources = ARRAY_SIZE(ixp46x_hwrandom_resource),
271 -};
272 -
273 -/*
274 - * I2C controller. The IXP46x uses the same block as the IOP3xx, so
275 - * we just use the same device name.
276 - */
277 -static struct platform_device ixp46x_i2c_controller = {
278 - .name = "IOP3xx-I2C",
279 - .id = 0,
280 - .num_resources = 2,
281 - .resource = ixp46x_i2c_resources
282 -};
283 -
284 -static struct resource ixp46x_ptp_resources[] = {
285 - DEFINE_RES_MEM(IXP4XX_TIMESYNC_BASE_PHYS, SZ_4K),
286 - DEFINE_RES_IRQ_NAMED(IRQ_IXP4XX_GPIO8, "master"),
287 - DEFINE_RES_IRQ_NAMED(IRQ_IXP4XX_GPIO7, "slave"),
288 -};
289 -
290 -static struct platform_device ixp46x_ptp = {
291 - .name = "ptp-ixp46x",
292 - .id = -1,
293 - .resource = ixp46x_ptp_resources,
294 - .num_resources = ARRAY_SIZE(ixp46x_ptp_resources),
295 -};
296 -
297 -static struct platform_device *ixp46x_devices[] __initdata = {
298 - &ixp46x_hwrandom_device,
299 - &ixp46x_i2c_controller,
300 - &ixp46x_ptp,
301 -};
302 -
303 -unsigned long ixp4xx_exp_bus_size;
304 -EXPORT_SYMBOL(ixp4xx_exp_bus_size);
305 -
306 -static struct platform_device_info ixp_dev_info __initdata = {
307 - .name = "ixp4xx_crypto",
308 - .id = 0,
309 - .dma_mask = DMA_BIT_MASK(32),
310 -};
311 -
312 -static int __init ixp_crypto_register(void)
313 -{
314 - struct platform_device *pdev;
315 -
316 - if (!(~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH |
317 - IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) {
318 - printk(KERN_ERR "ixp_crypto: No HW crypto available\n");
319 - return -ENODEV;
320 - }
321 -
322 - pdev = platform_device_register_full(&ixp_dev_info);
323 - if (IS_ERR(pdev))
324 - return PTR_ERR(pdev);
325 -
326 - return 0;
327 -}
328 -
329 -void __init ixp4xx_sys_init(void)
330 -{
331 - ixp4xx_exp_bus_size = SZ_16M;
332 -
333 - platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
334 -
335 - if (IS_ENABLED(CONFIG_CRYPTO_DEV_IXP4XX))
336 - ixp_crypto_register();
337 -
338 - if (cpu_is_ixp46x()) {
339 - int region;
340 -
341 - platform_add_devices(ixp46x_devices,
342 - ARRAY_SIZE(ixp46x_devices));
343 -
344 - for (region = 0; region < 7; region++) {
345 - if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
346 - ixp4xx_exp_bus_size = SZ_32M;
347 - break;
348 - }
349 - }
350 - }
351 -
352 - printk("IXP4xx: Using %luMiB expansion bus window size\n",
353 - ixp4xx_exp_bus_size >> 20);
354 -}
355 -
356 -unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
357 -EXPORT_SYMBOL(ixp4xx_timer_freq);
358 -
359 -void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
360 -{
361 - if (mode == REBOOT_SOFT) {
362 - /* Jump into ROM at address 0 */
363 - soft_restart(0);
364 - } else {
365 - /* Use on-chip reset capability */
366 -
367 - /* set the "key" register to enable access to
368 - * "timer" and "enable" registers
369 - */
370 - *IXP4XX_OSWK = IXP4XX_WDT_KEY;
371 -
372 - /* write 0 to the timer register for an immediate reset */
373 - *IXP4XX_OSWT = 0;
374 -
375 - *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
376 - }
377 -}
378 diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
379 deleted file mode 100644
380 index 41f28fb8e63f..000000000000
381 --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
382 +++ /dev/null
383 @@ -1,26 +0,0 @@
384 -/* SPDX-License-Identifier: GPL-2.0-only */
385 -/*
386 - * arch/arm/mach-ixp4xx/include/mach/hardware.h
387 - *
388 - * Copyright (C) 2002 Intel Corporation.
389 - * Copyright (C) 2003-2004 MontaVista Software, Inc.
390 - */
391 -
392 -/*
393 - * Hardware definitions for IXP4xx based systems
394 - */
395 -
396 -#ifndef __ASM_ARCH_HARDWARE_H__
397 -#define __ASM_ARCH_HARDWARE_H__
398 -
399 -/* Register locations and bits */
400 -#include "ixp4xx-regs.h"
401 -
402 -#ifndef __ASSEMBLER__
403 -#include <linux/soc/ixp4xx/cpu.h>
404 -#endif
405 -
406 -/* Platform helper functions and definitions */
407 -#include "platform.h"
408 -
409 -#endif /* _ASM_ARCH_HARDWARE_H */
410 diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
411 deleted file mode 100644
412 index 74e63d4531aa..000000000000
413 --- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
414 +++ /dev/null
415 @@ -1,303 +0,0 @@
416 -/* SPDX-License-Identifier: GPL-2.0-only */
417 -/*
418 - * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
419 - *
420 - * Register definitions for IXP4xx chipset. This file contains
421 - * register location and bit definitions only. Platform specific
422 - * definitions and helper function declarations are in platform.h
423 - * and machine-name.h.
424 - *
425 - * Copyright (C) 2002 Intel Corporation.
426 - * Copyright (C) 2003-2004 MontaVista Software, Inc.
427 - */
428 -
429 -#ifndef _ASM_ARM_IXP4XX_H_
430 -#define _ASM_ARM_IXP4XX_H_
431 -
432 -/*
433 - * IXP4xx Linux Memory Map:
434 - *
435 - * Phy Size Virt Description
436 - * =========================================================================
437 - *
438 - * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM
439 - *
440 - * 0x48000000 0x04000000 ioremap'd PCI Memory Space
441 - *
442 - * 0x50000000 0x10000000 ioremap'd EXP BUS
443 - *
444 - * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals
445 - *
446 - * 0xC0000000 0x00001000 0xFEF13000 PCI CFG
447 - *
448 - * 0xC4000000 0x00001000 0xFEF14000 EXP CFG
449 - *
450 - * 0x60000000 0x00004000 0xFEF15000 QMgr
451 - */
452 -
453 -/*
454 - * Queue Manager
455 - */
456 -#define IXP4XX_QMGR_BASE_PHYS 0x60000000
457 -
458 -/*
459 - * Peripheral space, including debug UART. Must be section-aligned so that
460 - * it can be used with the low-level debug code.
461 - */
462 -#define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000
463 -#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEC00000)
464 -#define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000
465 -
466 -/*
467 - * PCI Config registers
468 - */
469 -#define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000
470 -#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEC13000)
471 -#define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000
472 -
473 -/*
474 - * Expansion BUS Configuration registers
475 - */
476 -#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000
477 -#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000
478 -#define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000
479 -
480 -#define IXP4XX_EXP_CS0_OFFSET 0x00
481 -#define IXP4XX_EXP_CS1_OFFSET 0x04
482 -#define IXP4XX_EXP_CS2_OFFSET 0x08
483 -#define IXP4XX_EXP_CS3_OFFSET 0x0C
484 -#define IXP4XX_EXP_CS4_OFFSET 0x10
485 -#define IXP4XX_EXP_CS5_OFFSET 0x14
486 -#define IXP4XX_EXP_CS6_OFFSET 0x18
487 -#define IXP4XX_EXP_CS7_OFFSET 0x1C
488 -#define IXP4XX_EXP_CFG0_OFFSET 0x20
489 -#define IXP4XX_EXP_CFG1_OFFSET 0x24
490 -#define IXP4XX_EXP_CFG2_OFFSET 0x28
491 -#define IXP4XX_EXP_CFG3_OFFSET 0x2C
492 -
493 -/*
494 - * Expansion Bus Controller registers.
495 - */
496 -#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
497 -
498 -#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
499 -#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
500 -#define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET)
501 -#define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
502 -#define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
503 -#define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
504 -#define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)
505 -#define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
506 -
507 -#define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET)
508 -#define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET)
509 -#define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET)
510 -#define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
511 -
512 -
513 -/*
514 - * Peripheral Space Register Region Base Addresses
515 - */
516 -#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
517 -#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
518 -#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
519 -#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
520 -#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
521 -#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
522 -#define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
523 -#define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
524 -#define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
525 -#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
526 -#define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
527 -#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
528 -/* ixp46X only */
529 -#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
530 -#define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
531 -#define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
532 -#define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
533 -#define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
534 -#define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
535 -#define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
536 -
537 -
538 -/* The UART is explicitly put in the beginning of fixmap */
539 -#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
540 -#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
541 -#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
542 -#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
543 -#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
544 -#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
545 -#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
546 -#define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
547 -#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
548 -/* ixp46X only */
549 -#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
550 -#define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
551 -#define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
552 -#define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
553 -#define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
554 -#define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
555 -#define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
556 -
557 -/*
558 - * Constants to make it easy to access Timer Control/Status registers
559 - */
560 -#define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */
561 -#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
562 -#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
563 -#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
564 -#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
565 -#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
566 -#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
567 -#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
568 -#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
569 -
570 -/*
571 - * Operating System Timer Register Definitions.
572 - */
573 -
574 -#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
575 -
576 -#define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
577 -#define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
578 -#define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
579 -#define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
580 -#define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
581 -#define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
582 -#define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
583 -#define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
584 -#define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
585 -
586 -/*
587 - * Timer register values and bit definitions
588 - */
589 -#define IXP4XX_OST_ENABLE 0x00000001
590 -#define IXP4XX_OST_ONE_SHOT 0x00000002
591 -/* Low order bits of reload value ignored */
592 -#define IXP4XX_OST_RELOAD_MASK 0x00000003
593 -#define IXP4XX_OST_DISABLED 0x00000000
594 -#define IXP4XX_OSST_TIMER_1_PEND 0x00000001
595 -#define IXP4XX_OSST_TIMER_2_PEND 0x00000002
596 -#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
597 -#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
598 -#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
599 -
600 -#define IXP4XX_WDT_KEY 0x0000482E
601 -
602 -#define IXP4XX_WDT_RESET_ENABLE 0x00000001
603 -#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
604 -#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
605 -
606 -
607 -/*
608 - * Constants to make it easy to access PCI Control/Status registers
609 - */
610 -#define PCI_NP_AD_OFFSET 0x00
611 -#define PCI_NP_CBE_OFFSET 0x04
612 -#define PCI_NP_WDATA_OFFSET 0x08
613 -#define PCI_NP_RDATA_OFFSET 0x0c
614 -#define PCI_CRP_AD_CBE_OFFSET 0x10
615 -#define PCI_CRP_WDATA_OFFSET 0x14
616 -#define PCI_CRP_RDATA_OFFSET 0x18
617 -#define PCI_CSR_OFFSET 0x1c
618 -#define PCI_ISR_OFFSET 0x20
619 -#define PCI_INTEN_OFFSET 0x24
620 -#define PCI_DMACTRL_OFFSET 0x28
621 -#define PCI_AHBMEMBASE_OFFSET 0x2c
622 -#define PCI_AHBIOBASE_OFFSET 0x30
623 -#define PCI_PCIMEMBASE_OFFSET 0x34
624 -#define PCI_AHBDOORBELL_OFFSET 0x38
625 -#define PCI_PCIDOORBELL_OFFSET 0x3C
626 -#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
627 -#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
628 -#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
629 -#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
630 -#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
631 -#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
632 -
633 -/*
634 - * PCI Control/Status Registers
635 - */
636 -#define _IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
637 -
638 -#define PCI_NP_AD _IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
639 -#define PCI_NP_CBE _IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
640 -#define PCI_NP_WDATA _IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
641 -#define PCI_NP_RDATA _IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
642 -#define PCI_CRP_AD_CBE _IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
643 -#define PCI_CRP_WDATA _IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
644 -#define PCI_CRP_RDATA _IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
645 -#define PCI_CSR _IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
646 -#define PCI_ISR _IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
647 -#define PCI_INTEN _IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
648 -#define PCI_DMACTRL _IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
649 -#define PCI_AHBMEMBASE _IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
650 -#define PCI_AHBIOBASE _IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
651 -#define PCI_PCIMEMBASE _IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
652 -#define PCI_AHBDOORBELL _IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
653 -#define PCI_PCIDOORBELL _IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
654 -#define PCI_ATPDMA0_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
655 -#define PCI_ATPDMA0_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
656 -#define PCI_ATPDMA0_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
657 -#define PCI_ATPDMA1_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
658 -#define PCI_ATPDMA1_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
659 -#define PCI_ATPDMA1_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
660 -
661 -/*
662 - * PCI register values and bit definitions
663 - */
664 -
665 -/* CSR bit definitions */
666 -#define PCI_CSR_HOST 0x00000001
667 -#define PCI_CSR_ARBEN 0x00000002
668 -#define PCI_CSR_ADS 0x00000004
669 -#define PCI_CSR_PDS 0x00000008
670 -#define PCI_CSR_ABE 0x00000010
671 -#define PCI_CSR_DBT 0x00000020
672 -#define PCI_CSR_ASE 0x00000100
673 -#define PCI_CSR_IC 0x00008000
674 -
675 -/* ISR (Interrupt status) Register bit definitions */
676 -#define PCI_ISR_PSE 0x00000001
677 -#define PCI_ISR_PFE 0x00000002
678 -#define PCI_ISR_PPE 0x00000004
679 -#define PCI_ISR_AHBE 0x00000008
680 -#define PCI_ISR_APDC 0x00000010
681 -#define PCI_ISR_PADC 0x00000020
682 -#define PCI_ISR_ADB 0x00000040
683 -#define PCI_ISR_PDB 0x00000080
684 -
685 -/* INTEN (Interrupt Enable) Register bit definitions */
686 -#define PCI_INTEN_PSE 0x00000001
687 -#define PCI_INTEN_PFE 0x00000002
688 -#define PCI_INTEN_PPE 0x00000004
689 -#define PCI_INTEN_AHBE 0x00000008
690 -#define PCI_INTEN_APDC 0x00000010
691 -#define PCI_INTEN_PADC 0x00000020
692 -#define PCI_INTEN_ADB 0x00000040
693 -#define PCI_INTEN_PDB 0x00000080
694 -
695 -/*
696 - * Shift value for byte enable on NP cmd/byte enable register
697 - */
698 -#define IXP4XX_PCI_NP_CBE_BESL 4
699 -
700 -/*
701 - * PCI commands supported by NP access unit
702 - */
703 -#define NP_CMD_IOREAD 0x2
704 -#define NP_CMD_IOWRITE 0x3
705 -#define NP_CMD_CONFIGREAD 0xa
706 -#define NP_CMD_CONFIGWRITE 0xb
707 -#define NP_CMD_MEMREAD 0x6
708 -#define NP_CMD_MEMWRITE 0x7
709 -
710 -/*
711 - * Constants for CRP access into local config space
712 - */
713 -#define CRP_AD_CBE_BESL 20
714 -#define CRP_AD_CBE_WRITE 0x00010000
715 -
716 -#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
717 -
718 -#endif
719 diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
720 deleted file mode 100644
721 index f9ec07f00be0..000000000000
722 --- a/arch/arm/mach-ixp4xx/include/mach/platform.h
723 +++ /dev/null
724 @@ -1,98 +0,0 @@
725 -/* SPDX-License-Identifier: GPL-2.0 */
726 -/*
727 - * arch/arm/mach-ixp4xx/include/mach/platform.h
728 - *
729 - * Constants and functions that are useful to IXP4xx platform-specific code
730 - * and device drivers.
731 - *
732 - * Copyright (C) 2004 MontaVista Software, Inc.
733 - */
734 -
735 -#ifndef __ASM_ARCH_HARDWARE_H__
736 -#error "Do not include this directly, instead #include <mach/hardware.h>"
737 -#endif
738 -
739 -#ifndef __ASSEMBLY__
740 -
741 -#include <linux/reboot.h>
742 -#include <linux/platform_data/eth_ixp4xx.h>
743 -
744 -#include <asm/types.h>
745 -
746 -#ifndef __ARMEB__
747 -#define REG_OFFSET 0
748 -#else
749 -#define REG_OFFSET 3
750 -#endif
751 -
752 -/*
753 - * Expansion bus memory regions
754 - */
755 -#define IXP4XX_EXP_BUS_BASE_PHYS (0x50000000)
756 -
757 -/*
758 - * The expansion bus on the IXP4xx can be configured for either 16 or
759 - * 32MB windows and the CS offset for each region changes based on the
760 - * current configuration. This means that we cannot simply hardcode
761 - * each offset. ixp4xx_sys_init() looks at the expansion bus configuration
762 - * as setup by the bootloader to determine our window size.
763 - */
764 -extern unsigned long ixp4xx_exp_bus_size;
765 -
766 -#define IXP4XX_EXP_BUS_BASE(region)\
767 - (IXP4XX_EXP_BUS_BASE_PHYS + ((region) * ixp4xx_exp_bus_size))
768 -
769 -#define IXP4XX_EXP_BUS_END(region)\
770 - (IXP4XX_EXP_BUS_BASE(region) + ixp4xx_exp_bus_size - 1)
771 -
772 -/* Those macros can be used to adjust timing and configure
773 - * other features for each region.
774 - */
775 -
776 -#define IXP4XX_EXP_BUS_RECOVERY_T(x) (((x) & 0x0f) << 16)
777 -#define IXP4XX_EXP_BUS_HOLD_T(x) (((x) & 0x03) << 20)
778 -#define IXP4XX_EXP_BUS_STROBE_T(x) (((x) & 0x0f) << 22)
779 -#define IXP4XX_EXP_BUS_SETUP_T(x) (((x) & 0x03) << 26)
780 -#define IXP4XX_EXP_BUS_ADDR_T(x) (((x) & 0x03) << 28)
781 -#define IXP4XX_EXP_BUS_SIZE(x) (((x) & 0x0f) << 10)
782 -#define IXP4XX_EXP_BUS_CYCLES(x) (((x) & 0x03) << 14)
783 -
784 -#define IXP4XX_EXP_BUS_CS_EN (1L << 31)
785 -#define IXP4XX_EXP_BUS_BYTE_RD16 (1L << 6)
786 -#define IXP4XX_EXP_BUS_HRDY_POL (1L << 5)
787 -#define IXP4XX_EXP_BUS_MUX_EN (1L << 4)
788 -#define IXP4XX_EXP_BUS_SPLT_EN (1L << 3)
789 -#define IXP4XX_EXP_BUS_WR_EN (1L << 1)
790 -#define IXP4XX_EXP_BUS_BYTE_EN (1L << 0)
791 -
792 -#define IXP4XX_EXP_BUS_CYCLES_INTEL 0x00
793 -#define IXP4XX_EXP_BUS_CYCLES_MOTOROLA 0x01
794 -#define IXP4XX_EXP_BUS_CYCLES_HPI 0x02
795 -
796 -#define IXP4XX_FLASH_WRITABLE (0x2)
797 -#define IXP4XX_FLASH_DEFAULT (0xbcd23c40)
798 -#define IXP4XX_FLASH_WRITE (0xbcd23c42)
799 -
800 -/*
801 - * Clock Speed Definitions.
802 - */
803 -#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66MHzi APB BUS */
804 -#define IXP4XX_UART_XTAL 14745600
805 -
806 -/*
807 - * Frequency of clock used for primary clocksource
808 - */
809 -extern unsigned long ixp4xx_timer_freq;
810 -
811 -/*
812 - * Functions used by platform-level setup code
813 - */
814 -extern void ixp4xx_map_io(void);
815 -extern void ixp4xx_init_early(void);
816 -extern void ixp4xx_init_irq(void);
817 -extern void ixp4xx_sys_init(void);
818 -extern void ixp4xx_timer_init(void);
819 -extern void ixp4xx_restart(enum reboot_mode, const char *);
820 -
821 -#endif // __ASSEMBLY__
822 -
823 diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
824 index 9e08b270cfc7..09e7663e6a55 100644
825 --- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
826 +++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
827 @@ -9,10 +9,12 @@
828 #ifndef _ARCH_UNCOMPRESS_H_
829 #define _ARCH_UNCOMPRESS_H_
830
831 -#include "ixp4xx-regs.h"
832 #include <asm/mach-types.h>
833 #include <linux/serial_reg.h>
834
835 +#define IXP4XX_UART1_BASE_PHYS 0xc8000000
836 +#define IXP4XX_UART2_BASE_PHYS 0xc8001000
837 +
838 #define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
839
840 volatile u32* uart_base;
841 diff --git a/arch/arm/mach-ixp4xx/irqs.h b/arch/arm/mach-ixp4xx/irqs.h
842 deleted file mode 100644
843 index a3e8d6408c56..000000000000
844 --- a/arch/arm/mach-ixp4xx/irqs.h
845 +++ /dev/null
846 @@ -1,64 +0,0 @@
847 -/* SPDX-License-Identifier: GPL-2.0-only */
848 -/*
849 - * arch/arm/mach-ixp4xx/include/mach/irqs.h
850 - *
851 - * IRQ definitions for IXP4XX based systems
852 - *
853 - * Copyright (C) 2002 Intel Corporation.
854 - * Copyright (C) 2003 MontaVista Software, Inc.
855 - */
856 -
857 -#ifndef _ARCH_IXP4XX_IRQS_H_
858 -#define _ARCH_IXP4XX_IRQS_H_
859 -
860 -#define IRQ_IXP4XX_BASE 16
861 -
862 -#define IRQ_IXP4XX_NPEA (IRQ_IXP4XX_BASE + 0)
863 -#define IRQ_IXP4XX_NPEB (IRQ_IXP4XX_BASE + 1)
864 -#define IRQ_IXP4XX_NPEC (IRQ_IXP4XX_BASE + 2)
865 -#define IRQ_IXP4XX_QM1 (IRQ_IXP4XX_BASE + 3)
866 -#define IRQ_IXP4XX_QM2 (IRQ_IXP4XX_BASE + 4)
867 -#define IRQ_IXP4XX_TIMER1 (IRQ_IXP4XX_BASE + 5)
868 -#define IRQ_IXP4XX_GPIO0 (IRQ_IXP4XX_BASE + 6)
869 -#define IRQ_IXP4XX_GPIO1 (IRQ_IXP4XX_BASE + 7)
870 -#define IRQ_IXP4XX_PCI_INT (IRQ_IXP4XX_BASE + 8)
871 -#define IRQ_IXP4XX_PCI_DMA1 (IRQ_IXP4XX_BASE + 9)
872 -#define IRQ_IXP4XX_PCI_DMA2 (IRQ_IXP4XX_BASE + 10)
873 -#define IRQ_IXP4XX_TIMER2 (IRQ_IXP4XX_BASE + 11)
874 -#define IRQ_IXP4XX_USB (IRQ_IXP4XX_BASE + 12)
875 -#define IRQ_IXP4XX_UART2 (IRQ_IXP4XX_BASE + 13)
876 -#define IRQ_IXP4XX_TIMESTAMP (IRQ_IXP4XX_BASE + 14)
877 -#define IRQ_IXP4XX_UART1 (IRQ_IXP4XX_BASE + 15)
878 -#define IRQ_IXP4XX_WDOG (IRQ_IXP4XX_BASE + 16)
879 -#define IRQ_IXP4XX_AHB_PMU (IRQ_IXP4XX_BASE + 17)
880 -#define IRQ_IXP4XX_XSCALE_PMU (IRQ_IXP4XX_BASE + 18)
881 -#define IRQ_IXP4XX_GPIO2 (IRQ_IXP4XX_BASE + 19)
882 -#define IRQ_IXP4XX_GPIO3 (IRQ_IXP4XX_BASE + 20)
883 -#define IRQ_IXP4XX_GPIO4 (IRQ_IXP4XX_BASE + 21)
884 -#define IRQ_IXP4XX_GPIO5 (IRQ_IXP4XX_BASE + 22)
885 -#define IRQ_IXP4XX_GPIO6 (IRQ_IXP4XX_BASE + 23)
886 -#define IRQ_IXP4XX_GPIO7 (IRQ_IXP4XX_BASE + 24)
887 -#define IRQ_IXP4XX_GPIO8 (IRQ_IXP4XX_BASE + 25)
888 -#define IRQ_IXP4XX_GPIO9 (IRQ_IXP4XX_BASE + 26)
889 -#define IRQ_IXP4XX_GPIO10 (IRQ_IXP4XX_BASE + 27)
890 -#define IRQ_IXP4XX_GPIO11 (IRQ_IXP4XX_BASE + 28)
891 -#define IRQ_IXP4XX_GPIO12 (IRQ_IXP4XX_BASE + 29)
892 -#define IRQ_IXP4XX_SW_INT1 (IRQ_IXP4XX_BASE + 30)
893 -#define IRQ_IXP4XX_SW_INT2 (IRQ_IXP4XX_BASE + 31)
894 -#define IRQ_IXP4XX_USB_HOST (IRQ_IXP4XX_BASE + 32)
895 -#define IRQ_IXP4XX_I2C (IRQ_IXP4XX_BASE + 33)
896 -#define IRQ_IXP4XX_SSP (IRQ_IXP4XX_BASE + 34)
897 -#define IRQ_IXP4XX_TSYNC (IRQ_IXP4XX_BASE + 35)
898 -#define IRQ_IXP4XX_EAU_DONE (IRQ_IXP4XX_BASE + 36)
899 -#define IRQ_IXP4XX_SHA_DONE (IRQ_IXP4XX_BASE + 37)
900 -#define IRQ_IXP4XX_SWCP_PE (IRQ_IXP4XX_BASE + 58)
901 -#define IRQ_IXP4XX_QM_PE (IRQ_IXP4XX_BASE + 60)
902 -#define IRQ_IXP4XX_MCU_ECC (IRQ_IXP4XX_BASE + 61)
903 -#define IRQ_IXP4XX_EXP_PE (IRQ_IXP4XX_BASE + 62)
904 -
905 -#define _IXP4XX_GPIO_IRQ(n) (IRQ_IXP4XX_GPIO ## n)
906 -#define IXP4XX_GPIO_IRQ(n) _IXP4XX_GPIO_IRQ(n)
907 -
908 -#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU)
909 -
910 -#endif
911 diff --git a/drivers/crypto/ixp4xx_crypto.c b/drivers/crypto/ixp4xx_crypto.c
912 index 98730aab287c..d39a386b31ac 100644
913 --- a/drivers/crypto/ixp4xx_crypto.c
914 +++ b/drivers/crypto/ixp4xx_crypto.c
915 @@ -33,7 +33,6 @@
916
917 /* Intermittent includes, delete this after v5.14-rc1 */
918 #include <linux/soc/ixp4xx/cpu.h>
919 -#include <mach/ixp4xx-regs.h>
920
921 #define MAX_KEYLEN 32
922
923 diff --git a/drivers/net/ethernet/xscale/ptp_ixp46x.c b/drivers/net/ethernet/xscale/ptp_ixp46x.c
924 index 39234852e01b..1f382777aa5a 100644
925 --- a/drivers/net/ethernet/xscale/ptp_ixp46x.c
926 +++ b/drivers/net/ethernet/xscale/ptp_ixp46x.c
927 @@ -16,7 +16,6 @@
928 #include <linux/ptp_clock_kernel.h>
929 #include <linux/platform_device.h>
930 #include <linux/soc/ixp4xx/cpu.h>
931 -#include <mach/ixp4xx-regs.h>
932
933 #include "ixp46x_ts.h"
934
935 --
936 2.20.1
937
Hauke Mehrtens staging tree