target/linux/ipq807x/patches-5.15/0039-v6.1-clk-qcom-apss-ipq6018-fix-apcs_alias0_clk_src.patch

   1 From 6b9d5ecd2913758780a0529f9b95392f330b721b Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Fri, 19 Aug 2022 00:06:21 +0200
   4 Subject: [PATCH] clk: qcom: apss-ipq6018: fix apcs_alias0_clk_src
   5
   6 While working on IPQ8074 APSS driver it was discovered that IPQ6018 and
   7 IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is
   8 currently broken.
   9
  10 More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux
  11 clock.
  12 However after debugging why it was always stuck at 800Mhz, it was figured
  13 out that its not regmap_mux compatible at all.
  14 It is a simple mux but it uses RCG2 register layout and control bits, so
  15 utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not
  16 having to provide a dummy frequency table.
  17
  18 While we are here, use ARRAY_SIZE for number of parents.
  19
  20 Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards.
  21
  22 Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller")
  23 Signed-off-by: Robert Marko <robimarko@gmail.com>
  24 Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
  25 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  26 Link: https://lore.kernel.org/r/20220818220628.339366-2-robimarko@gmail.com
  27 ---
  28  drivers/clk/qcom/apss-ipq6018.c | 13 ++++++-------
  29  1 file changed, 6 insertions(+), 7 deletions(-)
  30
  31 --- a/drivers/clk/qcom/apss-ipq6018.c
  32 +++ b/drivers/clk/qcom/apss-ipq6018.c
  33 @@ -16,7 +16,7 @@
  34  #include "clk-regmap.h"
  35  #include "clk-branch.h"
  36  #include "clk-alpha-pll.h"
  37 -#include "clk-regmap-mux.h"
  38 +#include "clk-rcg.h"
  39
  40  enum {
  41         P_XO,
  42 @@ -33,16 +33,15 @@ static const struct parent_map parents_a
  43         { P_APSS_PLL_EARLY, 5 },
  44  };
  45
  46 -static struct clk_regmap_mux apcs_alias0_clk_src = {
  47 -       .reg = 0x0050,
  48 -       .width = 3,
  49 -       .shift = 7,
  50 +static struct clk_rcg2 apcs_alias0_clk_src = {
  51 +       .cmd_rcgr = 0x0050,
  52 +       .hid_width = 5,
  53         .parent_map = parents_apcs_alias0_clk_src_map,
  54         .clkr.hw.init = &(struct clk_init_data){
  55                 .name = "apcs_alias0_clk_src",
  56                 .parent_data = parents_apcs_alias0_clk_src,
  57 -               .num_parents = 2,
  58 -               .ops = &clk_regmap_mux_closest_ops,
  59 +               .num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src),
  60 +               .ops = &clk_rcg2_mux_closest_ops,
  61                 .flags = CLK_SET_RATE_PARENT,
  62         },
  63  };