target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch

   1 From 22a0f55b0e505fbbbb680e451a62878bc97f7ff1 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Sun, 7 Feb 2021 17:23:38 +0100
   4 Subject: [PATCH 4/4] ipq806x: gcc: add missing clk and reset for crypto engine
   5
   6 Add missing clk and reset needed for nss additional core and crypto
   7 engine.
   8
   9 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  10 ---
  11  drivers/clk/qcom/gcc-ipq806x.c               | 250 +++++++++++++++++++
  12  include/dt-bindings/clock/qcom,gcc-ipq806x.h |   5 +-
  13  include/dt-bindings/reset/qcom,gcc-ipq806x.h |   5 +
  14  3 files changed, 259 insertions(+), 1 deletion(-)
  15
  16 diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
  17 index fbb8644c4a43..c36bcdf013d0 100644
  18 --- a/drivers/clk/qcom/gcc-ipq806x.c
  19 +++ b/drivers/clk/qcom/gcc-ipq806x.c
  20 @@ -223,7 +223,9 @@ static struct clk_regmap pll14_vote = {
  21
  22  static struct pll_freq_tbl pll18_freq_tbl[] = {
  23         NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
  24 +       NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
  25         NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
  26 +       NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
  27  };
  28
  29  static struct clk_pll pll18 = {
  30 @@ -245,6 +247,22 @@ static struct clk_pll pll18 = {
  31         },
  32  };
  33
  34 +static struct clk_pll pll11 = {
  35 +       .l_reg = 0x3184,
  36 +       .m_reg = 0x3188,
  37 +       .n_reg = 0x318c,
  38 +       .config_reg = 0x3194,
  39 +       .mode_reg = 0x3180,
  40 +       .status_reg = 0x3198,
  41 +       .status_bit = 16,
  42 +       .clkr.hw.init = &(struct clk_init_data){
  43 +               .name = "pll11",
  44 +               .parent_names = (const char *[]){ "pxo" },
  45 +               .num_parents = 1,
  46 +               .ops = &clk_pll_ops,
  47 +       },
  48 +};
  49 +
  50  enum {
  51         P_PXO,
  52         P_PLL8,
  53 @@ -253,6 +271,7 @@ enum {
  54         P_CXO,
  55         P_PLL14,
  56         P_PLL18,
  57 +       P_PLL11,
  58  };
  59
  60  static const struct parent_map gcc_pxo_pll8_map[] = {
  61 @@ -320,6 +339,42 @@ static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
  62         "pll18",
  63  };
  64
  65 +static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
  66 +       { P_PXO, 0 },
  67 +       { P_PLL8, 4 },
  68 +       { P_PLL0, 2 },
  69 +       { P_PLL14, 5 },
  70 +       { P_PLL18, 1 },
  71 +       { P_PLL11, 3 },
  72 +};
  73 +
  74 +static const char *gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
  75 +       "pxo",
  76 +       "pll8_vote",
  77 +       "pll0_vote",
  78 +       "pll14",
  79 +       "pll18",
  80 +       "pll11"
  81 +};
  82 +
  83 +static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
  84 +       { P_PXO, 0 },
  85 +       { P_PLL3, 6 },
  86 +       { P_PLL0, 2 },
  87 +       { P_PLL14, 5 },
  88 +       { P_PLL18, 1 },
  89 +       { P_PLL11, 3 },
  90 +};
  91 +
  92 +static const char *gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
  93 +       "pxo",
  94 +       "pll3",
  95 +       "pll0_vote",
  96 +       "pll14",
  97 +       "pll18",
  98 +       "pll11"
  99 +};
 100 +
 101  static struct freq_tbl clk_tbl_gsbi_uart[] = {
 102         {  1843200, P_PLL8, 2,  6, 625 },
 103         {  3686400, P_PLL8, 2, 12, 625 },
 104 @@ -1261,6 +1316,7 @@ static const struct freq_tbl clk_tbl_sdc[] = {
 105         {  20210000, P_PLL8,  1, 1,  19 },
 106         {  24000000, P_PLL8,  4, 1,   4 },
 107         {  48000000, P_PLL8,  4, 1,   2 },
 108 +       {  52000000, P_PLL8,  1, 2,  15 }, /* 51.2 Mhz */
 109         {  64000000, P_PLL8,  3, 1,   2 },
 110         {  96000000, P_PLL8,  4, 0,   0 },
 111         { 192000000, P_PLL8,  2, 0,   0 },
 112 @@ -2647,7 +2703,9 @@ static const struct freq_tbl clk_tbl_nss[] = {
 113         { 110000000, P_PLL18, 1, 1, 5 },
 114         { 275000000, P_PLL18, 2, 0, 0 },
 115         { 550000000, P_PLL18, 1, 0, 0 },
 116 +       { 600000000, P_PLL18, 1, 0, 0 },
 117         { 733000000, P_PLL18, 1, 0, 0 },
 118 +       { 800000000, P_PLL18, 1, 0, 0 },
 119         { }
 120  };
 121
 122 @@ -2759,6 +2817,186 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
 123         },
 124  };
 125
 126 +static const struct freq_tbl clk_tbl_ce5_core[] = {
 127 +       { 150000000, P_PLL3, 8, 1, 1 },
 128 +       { 213200000, P_PLL11, 5, 1, 1 },
 129 +       { }
 130 +};
 131 +
 132 +static struct clk_dyn_rcg ce5_core_src = {
 133 +       .ns_reg[0] = 0x36C4,
 134 +       .ns_reg[1] = 0x36C8,
 135 +       .bank_reg = 0x36C0,
 136 +       .s[0] = {
 137 +               .src_sel_shift = 0,
 138 +               .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
 139 +       },
 140 +       .s[1] = {
 141 +               .src_sel_shift = 0,
 142 +               .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
 143 +       },
 144 +       .p[0] = {
 145 +               .pre_div_shift = 3,
 146 +               .pre_div_width = 4,
 147 +       },
 148 +       .p[1] = {
 149 +               .pre_div_shift = 3,
 150 +               .pre_div_width = 4,
 151 +       },
 152 +       .mux_sel_bit = 0,
 153 +       .freq_tbl = clk_tbl_ce5_core,
 154 +       .clkr = {
 155 +               .enable_reg = 0x36C0,
 156 +               .enable_mask = BIT(1),
 157 +               .hw.init = &(struct clk_init_data){
 158 +                       .name = "ce5_core_src",
 159 +                       .parent_names = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
 160 +                       .num_parents = 6,
 161 +                       .ops = &clk_dyn_rcg_ops,
 162 +               },
 163 +       },
 164 +};
 165 +
 166 +static struct clk_branch ce5_core_clk = {
 167 +       .halt_reg = 0x2FDC,
 168 +       .halt_bit = 5,
 169 +       .hwcg_reg = 0x36CC,
 170 +       .hwcg_bit = 6,
 171 +       .clkr = {
 172 +               .enable_reg = 0x36CC,
 173 +               .enable_mask = BIT(4),
 174 +               .hw.init = &(struct clk_init_data){
 175 +                       .name = "ce5_core_clk",
 176 +                       .parent_names = (const char *[]){
 177 +                               "ce5_core_src",
 178 +                       },
 179 +                       .num_parents = 1,
 180 +                       .ops = &clk_branch_ops,
 181 +                       .flags = CLK_SET_RATE_PARENT,
 182 +               },
 183 +       },
 184 +};
 185 +
 186 +static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
 187 +       { 160000000, P_PLL0, 5, 1, 1 },
 188 +       { 213200000, P_PLL11, 5, 1, 1 },
 189 +       { }
 190 +};
 191 +
 192 +static struct clk_dyn_rcg ce5_a_clk_src = {
 193 +       .ns_reg[0] = 0x3d84,
 194 +       .ns_reg[1] = 0x3d88,
 195 +       .bank_reg = 0x3d80,
 196 +       .s[0] = {
 197 +               .src_sel_shift = 0,
 198 +               .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
 199 +       },
 200 +       .s[1] = {
 201 +               .src_sel_shift = 0,
 202 +               .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
 203 +       },
 204 +       .p[0] = {
 205 +               .pre_div_shift = 3,
 206 +               .pre_div_width = 4,
 207 +       },
 208 +       .p[1] = {
 209 +               .pre_div_shift = 3,
 210 +               .pre_div_width = 4,
 211 +       },
 212 +       .mux_sel_bit = 0,
 213 +       .freq_tbl = clk_tbl_ce5_a_clk,
 214 +       .clkr = {
 215 +               .enable_reg = 0x3d80,
 216 +               .enable_mask = BIT(1),
 217 +               .hw.init = &(struct clk_init_data){
 218 +                       .name = "ce5_a_clk_src",
 219 +                       .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
 220 +                       .num_parents = 6,
 221 +                       .ops = &clk_dyn_rcg_ops,
 222 +               },
 223 +       },
 224 +};
 225 +
 226 +static struct clk_branch ce5_a_clk = {
 227 +       .halt_reg = 0x3c20,
 228 +       .halt_bit = 12,
 229 +       .hwcg_reg = 0x3d8c,
 230 +       .hwcg_bit = 6,
 231 +       .clkr = {
 232 +               .enable_reg = 0x3d8c,
 233 +               .enable_mask = BIT(4),
 234 +               .hw.init = &(struct clk_init_data){
 235 +                       .name = "ce5_a_clk",
 236 +                       .parent_names = (const char *[]){
 237 +                               "ce5_a_clk_src",
 238 +                       },
 239 +                       .num_parents = 1,
 240 +                       .ops = &clk_branch_ops,
 241 +                       .flags = CLK_SET_RATE_PARENT,
 242 +               },
 243 +       },
 244 +};
 245 +
 246 +static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
 247 +       { 160000000, P_PLL0, 5, 1, 1 },
 248 +       { 213200000, P_PLL11, 5, 1, 1 },
 249 +       { }
 250 +};
 251 +
 252 +static struct clk_dyn_rcg ce5_h_clk_src = {
 253 +       .ns_reg[0] = 0x3c64,
 254 +       .ns_reg[1] = 0x3c68,
 255 +       .bank_reg = 0x3c60,
 256 +       .s[0] = {
 257 +               .src_sel_shift = 0,
 258 +               .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
 259 +       },
 260 +       .s[1] = {
 261 +               .src_sel_shift = 0,
 262 +               .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
 263 +       },
 264 +       .p[0] = {
 265 +               .pre_div_shift = 3,
 266 +               .pre_div_width = 4,
 267 +       },
 268 +       .p[1] = {
 269 +               .pre_div_shift = 3,
 270 +               .pre_div_width = 4,
 271 +       },
 272 +       .mux_sel_bit = 0,
 273 +       .freq_tbl = clk_tbl_ce5_h_clk,
 274 +       .clkr = {
 275 +               .enable_reg = 0x3c60,
 276 +               .enable_mask = BIT(1),
 277 +               .hw.init = &(struct clk_init_data){
 278 +                       .name = "ce5_h_clk_src",
 279 +                       .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
 280 +                       .num_parents = 6,
 281 +                       .ops = &clk_dyn_rcg_ops,
 282 +               },
 283 +       },
 284 +};
 285 +
 286 +static struct clk_branch ce5_h_clk = {
 287 +       .halt_reg = 0x3c20,
 288 +       .halt_bit = 11,
 289 +       .hwcg_reg = 0x3c6c,
 290 +       .hwcg_bit = 6,
 291 +       .clkr = {
 292 +               .enable_reg = 0x3c6c,
 293 +               .enable_mask = BIT(4),
 294 +               .hw.init = &(struct clk_init_data){
 295 +                       .name = "ce5_h_clk",
 296 +                       .parent_names = (const char *[]){
 297 +                               "ce5_h_clk_src",
 298 +                       },
 299 +                       .num_parents = 1,
 300 +                       .ops = &clk_branch_ops,
 301 +                       .flags = CLK_SET_RATE_PARENT,
 302 +               },
 303 +       },
 304 +};
 305 +
 306  static struct clk_regmap *gcc_ipq806x_clks[] = {
 307         [PLL0] = &pll0.clkr,
 308         [PLL0_VOTE] = &pll0_vote,
 309 @@ -2766,6 +3004,7 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
 310         [PLL4_VOTE] = &pll4_vote,
 311         [PLL8] = &pll8.clkr,
 312         [PLL8_VOTE] = &pll8_vote,
 313 +       [PLL11] = &pll11.clkr,
 314         [PLL14] = &pll14.clkr,
 315         [PLL14_VOTE] = &pll14_vote,
 316         [PLL18] = &pll18.clkr,
 317 @@ -2880,6 +3119,12 @@ static struct clk_regmap *gcc_ipq806x_clks[] = {
 318         [PLL9] = &hfpll0.clkr,
 319         [PLL10] = &hfpll1.clkr,
 320         [PLL12] = &hfpll_l2.clkr,
 321 +       [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
 322 +       [CE5_A_CLK] = &ce5_a_clk.clkr,
 323 +       [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
 324 +       [CE5_H_CLK] = &ce5_h_clk.clkr,
 325 +       [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
 326 +       [CE5_CORE_CLK] = &ce5_core_clk.clkr,
 327  };
 328
 329  static const struct qcom_reset_map gcc_ipq806x_resets[] = {
 330 @@ -3011,6 +3256,11 @@ static const struct qcom_reset_map gcc_ipq806x_resets[] = {
 331         [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
 332         [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
 333         [GMAC_AHB_RESET] = { 0x3e24, 0 },
 334 +       [CRYPTO_ENG1_RESET] = { 0x3e00, 0},
 335 +       [CRYPTO_ENG2_RESET] = { 0x3e04, 0},
 336 +       [CRYPTO_ENG3_RESET] = { 0x3e08, 0},
 337 +       [CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
 338 +       [CRYPTO_AHB_RESET] = { 0x3e10, 0},
 339         [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
 340         [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
 341         [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
 342 diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
 343 index 7deec14a6dee..02262d2ac899 100644
 344 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
 345 +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
 346 @@ -240,7 +240,7 @@
 347  #define PLL14                                  232
 348  #define PLL14_VOTE                             233
 349  #define PLL18                                  234
 350 -#define CE5_SRC                                        235
 351 +#define CE5_A_CLK                              235
 352  #define CE5_H_CLK                              236
 353  #define CE5_CORE_CLK                           237
 354  #define CE3_SLEEP_CLK                          238
 355 @@ -283,5 +283,8 @@
 356  #define EBI2_AON_CLK                           281
 357  #define NSSTCM_CLK_SRC                         282
 358  #define NSSTCM_CLK                             283
 359 +#define CE5_A_CLK_SRC                          285
 360 +#define CE5_H_CLK_SRC                          286
 361 +#define CE5_CORE_CLK_SRC                       287
 362
 363  #endif
 364 diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
 365 index 26b6f9200620..020c9cf18751 100644
 366 --- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
 367 +++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
 368 @@ -163,5 +163,10 @@
 369  #define NSS_CAL_PRBS_RST_N_RESET                       154
 370  #define NSS_LCKDT_RST_N_RESET                          155
 371  #define NSS_SRDS_N_RESET                               156
 372 +#define CRYPTO_ENG1_RESET                              157
 373 +#define CRYPTO_ENG2_RESET                              158
 374 +#define CRYPTO_ENG3_RESET                              159
 375 +#define CRYPTO_ENG4_RESET                              160
 376 +#define CRYPTO_AHB_RESET                               161
 377
 378  #endif
 379 --
 380 2.29.2
 381