target/linux/ipq806x/patches-4.9/0039-clk-qcom-Add-HFPLL-driver.patch

   1 From 23f680d03e5894f494572a5162d21328bd86890c Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Fri, 20 Mar 2015 23:45:25 -0700
   4 Subject: [PATCH 39/69] clk: qcom: Add HFPLL driver
   5
   6 On some devices (MSM8974 for example), the HFPLLs are
   7 instantiated within the Krait processor subsystem as separate
   8 register regions. Add a driver for these PLLs so that we can
   9 provide HFPLL clocks for use by the system.
  10
  11 Cc: <devicetree@vger.kernel.org>
  12 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  13 Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
  14 ---
  15  .../devicetree/bindings/clock/qcom,hfpll.txt       |  40 ++++++++
  16  drivers/clk/qcom/Kconfig                           |   8 ++
  17  drivers/clk/qcom/Makefile                          |   1 +
  18  drivers/clk/qcom/hfpll.c                           | 106 +++++++++++++++++++++
  19  4 files changed, 155 insertions(+)
  20  create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
  21  create mode 100644 drivers/clk/qcom/hfpll.c
  22
  23 diff --git a/Documentation/devicetree/bindings/clock/qcom,hfpll.txt b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
  24 new file mode 100644
  25 index 000000000000..fee92bb30344
  26 --- /dev/null
  27 +++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
  28 @@ -0,0 +1,40 @@
  29 +High-Frequency PLL (HFPLL)
  30 +
  31 +PROPERTIES
  32 +
  33 +- compatible:
  34 +       Usage: required
  35 +       Value type: <string>
  36 +       Definition: must be "qcom,hfpll"
  37 +
  38 +- reg:
  39 +       Usage: required
  40 +       Value type: <prop-encoded-array>
  41 +       Definition: address and size of HPLL registers. An optional second
  42 +                   element specifies the address and size of the alias
  43 +                   register region.
  44 +
  45 +- clock-output-names:
  46 +       Usage: required
  47 +       Value type: <string>
  48 +       Definition: Name of the PLL. Typically hfpllX where X is a CPU number
  49 +                   starting at 0. Otherwise hfpll_Y where Y is more specific
  50 +                   such as "l2".
  51 +
  52 +Example:
  53 +
  54 +1) An HFPLL for the L2 cache.
  55 +
  56 +       clock-controller@f9016000 {
  57 +               compatible = "qcom,hfpll";
  58 +               reg = <0xf9016000 0x30>;
  59 +               clock-output-names = "hfpll_l2";
  60 +       };
  61 +
  62 +2) An HFPLL for CPU0. This HFPLL has the alias register region.
  63 +
  64 +       clock-controller@f908a000 {
  65 +               compatible = "qcom,hfpll";
  66 +               reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
  67 +               clock-output-names = "hfpll0";
  68 +       };
  69 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
  70 index cfb051f66f01..e7ccc7fd7c47 100644
  71 --- a/drivers/clk/qcom/Kconfig
  72 +++ b/drivers/clk/qcom/Kconfig
  73 @@ -179,3 +179,11 @@ config MSM_MMCC_8996
  74           Support for the multimedia clock controller on msm8996 devices.
  75           Say Y if you want to support multimedia devices such as display,
  76           graphics, video encode/decode, camera, etc.
  77 +
  78 +config QCOM_HFPLL
  79 +       tristate "High-Frequency PLL (HFPLL) Clock Controller"
  80 +       depends on COMMON_CLK_QCOM
  81 +       help
  82 +         Support for the high-frequency PLLs present on Qualcomm devices.
  83 +         Say Y if you want to support CPU frequency scaling on devices
  84 +         such as MSM8974, APQ8084, etc.
  85 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
  86 index e9b89750c111..52a8777657aa 100644
  87 --- a/drivers/clk/qcom/Makefile
  88 +++ b/drivers/clk/qcom/Makefile
  89 @@ -32,3 +32,4 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
  90  obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
  91  obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
  92  obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
  93 +obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
  94 diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
  95 new file mode 100644
  96 index 000000000000..9eed519cf1c7
  97 --- /dev/null
  98 +++ b/drivers/clk/qcom/hfpll.c
  99 @@ -0,0 +1,106 @@
 100 +/*
 101 + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
 102 + *
 103 + * This program is free software; you can redistribute it and/or modify
 104 + * it under the terms of the GNU General Public License version 2 and
 105 + * only version 2 as published by the Free Software Foundation.
 106 + *
 107 + * This program is distributed in the hope that it will be useful,
 108 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 109 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 110 + * GNU General Public License for more details.
 111 + */
 112 +
 113 +#include <linux/kernel.h>
 114 +#include <linux/init.h>
 115 +#include <linux/module.h>
 116 +#include <linux/platform_device.h>
 117 +#include <linux/of.h>
 118 +#include <linux/clk.h>
 119 +#include <linux/clk-provider.h>
 120 +#include <linux/regmap.h>
 121 +
 122 +#include "clk-regmap.h"
 123 +#include "clk-hfpll.h"
 124 +
 125 +static const struct hfpll_data hdata = {
 126 +       .mode_reg = 0x00,
 127 +       .l_reg = 0x04,
 128 +       .m_reg = 0x08,
 129 +       .n_reg = 0x0c,
 130 +       .user_reg = 0x10,
 131 +       .config_reg = 0x14,
 132 +       .config_val = 0x430405d,
 133 +       .status_reg = 0x1c,
 134 +       .lock_bit = 16,
 135 +
 136 +       .user_val = 0x8,
 137 +       .user_vco_mask = 0x100000,
 138 +       .low_vco_max_rate = 1248000000,
 139 +       .min_rate = 537600000UL,
 140 +       .max_rate = 2900000000UL,
 141 +};
 142 +
 143 +static const struct of_device_id qcom_hfpll_match_table[] = {
 144 +       { .compatible = "qcom,hfpll" },
 145 +       { }
 146 +};
 147 +MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
 148 +
 149 +static const struct regmap_config hfpll_regmap_config = {
 150 +       .reg_bits       = 32,
 151 +       .reg_stride     = 4,
 152 +       .val_bits       = 32,
 153 +       .max_register   = 0x30,
 154 +       .fast_io        = true,
 155 +};
 156 +
 157 +static int qcom_hfpll_probe(struct platform_device *pdev)
 158 +{
 159 +       struct resource *res;
 160 +       struct device *dev = &pdev->dev;
 161 +       void __iomem *base;
 162 +       struct regmap *regmap;
 163 +       struct clk_hfpll *h;
 164 +       struct clk_init_data init = {
 165 +               .parent_names = (const char *[]){ "xo" },
 166 +               .num_parents = 1,
 167 +               .ops = &clk_ops_hfpll,
 168 +       };
 169 +
 170 +       h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
 171 +       if (!h)
 172 +               return -ENOMEM;
 173 +
 174 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 175 +       base = devm_ioremap_resource(dev, res);
 176 +       if (IS_ERR(base))
 177 +               return PTR_ERR(base);
 178 +
 179 +       regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
 180 +       if (IS_ERR(regmap))
 181 +               return PTR_ERR(regmap);
 182 +
 183 +       if (of_property_read_string_index(dev->of_node, "clock-output-names",
 184 +                                                 0, &init.name))
 185 +               return -ENODEV;
 186 +
 187 +       h->d = &hdata;
 188 +       h->clkr.hw.init = &init;
 189 +       spin_lock_init(&h->lock);
 190 +
 191 +       return devm_clk_register_regmap(&pdev->dev, &h->clkr);
 192 +}
 193 +
 194 +static struct platform_driver qcom_hfpll_driver = {
 195 +       .probe          = qcom_hfpll_probe,
 196 +       .driver         = {
 197 +               .name   = "qcom-hfpll",
 198 +               .of_match_table = qcom_hfpll_match_table,
 199 +       },
 200 +};
 201 +module_platform_driver(qcom_hfpll_driver);
 202 +
 203 +MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
 204 +MODULE_LICENSE("GPL v2");
 205 +MODULE_ALIAS("platform:qcom-hfpll");
 206 --
 207 2.11.0
 208