1 From 41ee71bae788e1858c0a387d010c342e6bb3f4b0 Mon Sep 17 00:00:00 2001
2 From: Georgi Djakov <georgi.djakov@linaro.org>
3 Date: Wed, 2 Nov 2016 17:56:56 +0200
4 Subject: [PATCH 27/69] clk: qcom: Add support for SMD-RPM Clocks
6 This adds initial support for clocks controlled by the Resource
7 Power Manager (RPM) processor on some Qualcomm SoCs, which use
8 the qcom_smd_rpm driver to communicate with RPM.
9 Such platforms are msm8916, apq8084 and msm8974.
11 The RPM is a dedicated hardware engine for managing the shared
12 SoC resources in order to keep the lowest power profile. It
13 communicates with other hardware subsystems via shared memory
14 and accepts clock requests, aggregates the requests and turns
15 the clocks on/off or scales them on demand.
17 This driver is based on the codeaurora.org driver:
18 https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c
20 Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
22 .../devicetree/bindings/clock/qcom,rpmcc.txt | 36 ++
23 drivers/clk/qcom/Kconfig | 16 +
24 drivers/clk/qcom/Makefile | 1 +
25 drivers/clk/qcom/clk-smd-rpm.c | 571 +++++++++++++++++++++
26 include/dt-bindings/clock/qcom,rpmcc.h | 45 ++
27 5 files changed, 669 insertions(+)
28 create mode 100644 Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
29 create mode 100644 drivers/clk/qcom/clk-smd-rpm.c
30 create mode 100644 include/dt-bindings/clock/qcom,rpmcc.h
32 diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
34 index 000000000000..e3e13226d798
36 +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
38 +Qualcomm RPM Clock Controller Binding
39 +------------------------------------------------
40 +The RPM is a dedicated hardware engine for managing the shared
41 +SoC resources in order to keep the lowest power profile. It
42 +communicates with other hardware subsystems via shared memory
43 +and accepts clock requests, aggregates the requests and turns
44 +the clocks on/off or scales them on demand.
46 +Required properties :
47 +- compatible : shall contain only one of the following. The generic
48 + compatible "qcom,rpmcc" should be also included.
50 + "qcom,rpmcc-msm8916", "qcom,rpmcc"
52 +- #clock-cells : shall contain 1
56 + compatible = "qcom,smd";
59 + interrupts = <0 168 1>;
60 + qcom,ipc = <&apcs 8 0>;
61 + qcom,smd-edge = <15>;
64 + compatible = "qcom,rpm-msm8916";
65 + qcom,smd-channels = "rpm_requests";
67 + rpmcc: clock-controller {
68 + compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
74 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
75 index 0146d3c2547f..b537c59dcfe6 100644
76 --- a/drivers/clk/qcom/Kconfig
77 +++ b/drivers/clk/qcom/Kconfig
78 @@ -2,6 +2,9 @@ config QCOM_GDSC
80 select PM_GENERIC_DOMAINS if PM
85 config COMMON_CLK_QCOM
86 tristate "Support for Qualcomm's clock controllers"
88 @@ -9,6 +12,19 @@ config COMMON_CLK_QCOM
90 select RESET_CONTROLLER
92 +config QCOM_CLK_SMD_RPM
93 + tristate "RPM over SMD based Clock Controller"
94 + depends on COMMON_CLK_QCOM && QCOM_SMD_RPM
97 + The RPM (Resource Power Manager) is a dedicated hardware engine for
98 + managing the shared SoC resources in order to keep the lowest power
99 + profile. It communicates with other hardware subsystems via shared
100 + memory and accepts clock requests, aggregates the requests and turns
101 + the clocks on/off or scales them on demand.
102 + Say Y if you want to support the clocks exposed by the RPM on
103 + platforms such as apq8016, apq8084, msm8974 etc.
106 tristate "APQ8084 Global Clock Controller"
108 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
109 index 1fb1f5476cb0..0dd72e56b7e4 100644
110 --- a/drivers/clk/qcom/Makefile
111 +++ b/drivers/clk/qcom/Makefile
112 @@ -29,3 +29,4 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
113 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
114 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
115 obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
116 +obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
117 diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
119 index 000000000000..8aba9ab2ccfd
121 +++ b/drivers/clk/qcom/clk-smd-rpm.c
124 + * Copyright (c) 2016, Linaro Limited
125 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
127 + * This software is licensed under the terms of the GNU General Public
128 + * License version 2, as published by the Free Software Foundation, and
129 + * may be copied, distributed, and modified under those terms.
131 + * This program is distributed in the hope that it will be useful,
132 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
133 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
134 + * GNU General Public License for more details.
137 +#include <linux/clk-provider.h>
138 +#include <linux/err.h>
139 +#include <linux/export.h>
140 +#include <linux/init.h>
141 +#include <linux/kernel.h>
142 +#include <linux/module.h>
143 +#include <linux/mutex.h>
144 +#include <linux/of.h>
145 +#include <linux/of_device.h>
146 +#include <linux/platform_device.h>
147 +#include <linux/soc/qcom/smd-rpm.h>
149 +#include <dt-bindings/clock/qcom,rpmcc.h>
150 +#include <dt-bindings/mfd/qcom-rpm.h>
152 +#define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773
153 +#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370
154 +#define QCOM_RPM_SMD_KEY_RATE 0x007a484b
155 +#define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45
156 +#define QCOM_RPM_SMD_KEY_STATE 0x54415453
157 +#define QCOM_RPM_SCALING_ENABLE_ID 0x2
159 +#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id, \
161 + static struct clk_smd_rpm _platform##_##_active; \
162 + static struct clk_smd_rpm _platform##_##_name = { \
163 + .rpm_res_type = (type), \
164 + .rpm_clk_id = (r_id), \
165 + .rpm_status_id = (stat_id), \
166 + .rpm_key = (key), \
167 + .peer = &_platform##_##_active, \
169 + .hw.init = &(struct clk_init_data){ \
170 + .ops = &clk_smd_rpm_ops, \
172 + .parent_names = (const char *[]){ "xo_board" }, \
173 + .num_parents = 1, \
176 + static struct clk_smd_rpm _platform##_##_active = { \
177 + .rpm_res_type = (type), \
178 + .rpm_clk_id = (r_id), \
179 + .rpm_status_id = (stat_id), \
180 + .active_only = true, \
181 + .rpm_key = (key), \
182 + .peer = &_platform##_##_name, \
184 + .hw.init = &(struct clk_init_data){ \
185 + .ops = &clk_smd_rpm_ops, \
186 + .name = #_active, \
187 + .parent_names = (const char *[]){ "xo_board" }, \
188 + .num_parents = 1, \
192 +#define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \
194 + static struct clk_smd_rpm _platform##_##_active; \
195 + static struct clk_smd_rpm _platform##_##_name = { \
196 + .rpm_res_type = (type), \
197 + .rpm_clk_id = (r_id), \
198 + .rpm_status_id = (stat_id), \
199 + .rpm_key = (key), \
201 + .peer = &_platform##_##_active, \
203 + .hw.init = &(struct clk_init_data){ \
204 + .ops = &clk_smd_rpm_branch_ops, \
206 + .parent_names = (const char *[]){ "xo_board" }, \
207 + .num_parents = 1, \
210 + static struct clk_smd_rpm _platform##_##_active = { \
211 + .rpm_res_type = (type), \
212 + .rpm_clk_id = (r_id), \
213 + .rpm_status_id = (stat_id), \
214 + .active_only = true, \
215 + .rpm_key = (key), \
217 + .peer = &_platform##_##_name, \
219 + .hw.init = &(struct clk_init_data){ \
220 + .ops = &clk_smd_rpm_branch_ops, \
221 + .name = #_active, \
222 + .parent_names = (const char *[]){ "xo_board" }, \
223 + .num_parents = 1, \
227 +#define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id) \
228 + __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \
229 + 0, QCOM_RPM_SMD_KEY_RATE)
231 +#define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r) \
232 + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, \
233 + r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE)
235 +#define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id) \
236 + __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \
237 + 0, QCOM_RPM_SMD_KEY_STATE)
239 +#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id) \
240 + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \
241 + QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
242 + QCOM_RPM_KEY_SOFTWARE_ENABLE)
244 +#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, r_id) \
245 + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \
246 + QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
247 + QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
249 +#define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
251 +struct clk_smd_rpm {
252 + const int rpm_res_type;
254 + const int rpm_clk_id;
255 + const int rpm_status_id;
256 + const bool active_only;
259 + struct clk_smd_rpm *peer;
261 + unsigned long rate;
262 + struct qcom_smd_rpm *rpm;
265 +struct clk_smd_rpm_req {
272 + struct qcom_rpm *rpm;
273 + struct clk_hw_onecell_data data;
274 + struct clk_hw *hws[];
277 +struct rpm_smd_clk_desc {
278 + struct clk_smd_rpm **clks;
282 +static DEFINE_MUTEX(rpm_smd_clk_lock);
284 +static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)
287 + struct clk_smd_rpm_req req = {
288 + .key = cpu_to_le32(r->rpm_key),
289 + .nbytes = cpu_to_le32(sizeof(u32)),
290 + .value = cpu_to_le32(INT_MAX),
293 + ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
294 + r->rpm_res_type, r->rpm_clk_id, &req,
298 + ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
299 + r->rpm_res_type, r->rpm_clk_id, &req,
307 +static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
308 + unsigned long rate)
310 + struct clk_smd_rpm_req req = {
311 + .key = cpu_to_le32(r->rpm_key),
312 + .nbytes = cpu_to_le32(sizeof(u32)),
313 + .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
316 + return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
317 + r->rpm_res_type, r->rpm_clk_id, &req,
321 +static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
322 + unsigned long rate)
324 + struct clk_smd_rpm_req req = {
325 + .key = cpu_to_le32(r->rpm_key),
326 + .nbytes = cpu_to_le32(sizeof(u32)),
327 + .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
330 + return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
331 + r->rpm_res_type, r->rpm_clk_id, &req,
335 +static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
336 + unsigned long *active, unsigned long *sleep)
341 + * Active-only clocks don't care what the rate is during sleep. So,
342 + * they vote for zero.
344 + if (r->active_only)
350 +static int clk_smd_rpm_prepare(struct clk_hw *hw)
352 + struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
353 + struct clk_smd_rpm *peer = r->peer;
354 + unsigned long this_rate = 0, this_sleep_rate = 0;
355 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
356 + unsigned long active_rate, sleep_rate;
359 + mutex_lock(&rpm_smd_clk_lock);
361 + /* Don't send requests to the RPM if the rate has not been set. */
365 + to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
367 + /* Take peer clock's rate into account only if it's enabled. */
369 + to_active_sleep(peer, peer->rate,
370 + &peer_rate, &peer_sleep_rate);
372 + active_rate = max(this_rate, peer_rate);
375 + active_rate = !!active_rate;
377 + ret = clk_smd_rpm_set_rate_active(r, active_rate);
381 + sleep_rate = max(this_sleep_rate, peer_sleep_rate);
383 + sleep_rate = !!sleep_rate;
385 + ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
387 + /* Undo the active set vote and restore it */
388 + ret = clk_smd_rpm_set_rate_active(r, peer_rate);
394 + mutex_unlock(&rpm_smd_clk_lock);
399 +static void clk_smd_rpm_unprepare(struct clk_hw *hw)
401 + struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
402 + struct clk_smd_rpm *peer = r->peer;
403 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
404 + unsigned long active_rate, sleep_rate;
407 + mutex_lock(&rpm_smd_clk_lock);
412 + /* Take peer clock's rate into account only if it's enabled. */
414 + to_active_sleep(peer, peer->rate, &peer_rate,
417 + active_rate = r->branch ? !!peer_rate : peer_rate;
418 + ret = clk_smd_rpm_set_rate_active(r, active_rate);
422 + sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
423 + ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
427 + r->enabled = false;
430 + mutex_unlock(&rpm_smd_clk_lock);
433 +static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
434 + unsigned long parent_rate)
436 + struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
437 + struct clk_smd_rpm *peer = r->peer;
438 + unsigned long active_rate, sleep_rate;
439 + unsigned long this_rate = 0, this_sleep_rate = 0;
440 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
443 + mutex_lock(&rpm_smd_clk_lock);
448 + to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
450 + /* Take peer clock's rate into account only if it's enabled. */
452 + to_active_sleep(peer, peer->rate,
453 + &peer_rate, &peer_sleep_rate);
455 + active_rate = max(this_rate, peer_rate);
456 + ret = clk_smd_rpm_set_rate_active(r, active_rate);
460 + sleep_rate = max(this_sleep_rate, peer_sleep_rate);
461 + ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
468 + mutex_unlock(&rpm_smd_clk_lock);
473 +static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
474 + unsigned long *parent_rate)
477 + * RPM handles rate rounding and we don't have a way to
478 + * know what the rate will be, so just return whatever
479 + * rate is requested.
484 +static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
485 + unsigned long parent_rate)
487 + struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
490 + * RPM handles rate rounding and we don't have a way to
491 + * know what the rate will be, so just return whatever
497 +static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
500 + struct clk_smd_rpm_req req = {
501 + .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
502 + .nbytes = cpu_to_le32(sizeof(u32)),
503 + .value = cpu_to_le32(1),
506 + ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
507 + QCOM_SMD_RPM_MISC_CLK,
508 + QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
510 + pr_err("RPM clock scaling (sleep set) not enabled!\n");
514 + ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
515 + QCOM_SMD_RPM_MISC_CLK,
516 + QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
518 + pr_err("RPM clock scaling (active set) not enabled!\n");
522 + pr_debug("%s: RPM clock scaling is enabled\n", __func__);
526 +static const struct clk_ops clk_smd_rpm_ops = {
527 + .prepare = clk_smd_rpm_prepare,
528 + .unprepare = clk_smd_rpm_unprepare,
529 + .set_rate = clk_smd_rpm_set_rate,
530 + .round_rate = clk_smd_rpm_round_rate,
531 + .recalc_rate = clk_smd_rpm_recalc_rate,
534 +static const struct clk_ops clk_smd_rpm_branch_ops = {
535 + .prepare = clk_smd_rpm_prepare,
536 + .unprepare = clk_smd_rpm_unprepare,
537 + .round_rate = clk_smd_rpm_round_rate,
538 + .recalc_rate = clk_smd_rpm_recalc_rate,
542 +DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
543 +DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
544 +DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
545 +DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
546 +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1);
547 +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2);
548 +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4);
549 +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5);
550 +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1);
551 +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2);
552 +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4);
553 +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5);
555 +static struct clk_smd_rpm *msm8916_clks[] = {
556 + [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
557 + [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
558 + [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
559 + [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
560 + [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
561 + [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
562 + [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
563 + [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
564 + [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
565 + [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
566 + [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
567 + [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
568 + [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
569 + [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
570 + [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
571 + [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
572 + [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
573 + [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
574 + [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
575 + [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
576 + [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
577 + [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
578 + [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
579 + [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
582 +static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
583 + .clks = msm8916_clks,
584 + .num_clks = ARRAY_SIZE(msm8916_clks),
587 +static const struct of_device_id rpm_smd_clk_match_table[] = {
588 + { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
591 +MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
593 +static int rpm_smd_clk_probe(struct platform_device *pdev)
595 + struct clk_hw **hws;
596 + struct rpm_cc *rcc;
597 + struct clk_hw_onecell_data *data;
599 + size_t num_clks, i;
600 + struct qcom_smd_rpm *rpm;
601 + struct clk_smd_rpm **rpm_smd_clks;
602 + const struct rpm_smd_clk_desc *desc;
604 + rpm = dev_get_drvdata(pdev->dev.parent);
606 + dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
610 + desc = of_device_get_match_data(&pdev->dev);
614 + rpm_smd_clks = desc->clks;
615 + num_clks = desc->num_clks;
617 + rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*hws) * num_clks,
624 + data->num = num_clks;
626 + for (i = 0; i < num_clks; i++) {
627 + if (!rpm_smd_clks[i]) {
631 + rpm_smd_clks[i]->rpm = rpm;
633 + ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
638 + ret = clk_smd_rpm_enable_scaling(rpm);
642 + for (i = 0; i < num_clks; i++) {
643 + if (!rpm_smd_clks[i]) {
644 + data->hws[i] = ERR_PTR(-ENOENT);
648 + ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
653 + ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
660 + dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
664 +static int rpm_smd_clk_remove(struct platform_device *pdev)
666 + of_clk_del_provider(pdev->dev.of_node);
670 +static struct platform_driver rpm_smd_clk_driver = {
672 + .name = "qcom-clk-smd-rpm",
673 + .of_match_table = rpm_smd_clk_match_table,
675 + .probe = rpm_smd_clk_probe,
676 + .remove = rpm_smd_clk_remove,
679 +static int __init rpm_smd_clk_init(void)
681 + return platform_driver_register(&rpm_smd_clk_driver);
683 +core_initcall(rpm_smd_clk_init);
685 +static void __exit rpm_smd_clk_exit(void)
687 + platform_driver_unregister(&rpm_smd_clk_driver);
689 +module_exit(rpm_smd_clk_exit);
691 +MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
692 +MODULE_LICENSE("GPL v2");
693 +MODULE_ALIAS("platform:qcom-clk-smd-rpm");
694 diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
696 index 000000000000..9fae52dfe35a
698 +++ b/include/dt-bindings/clock/qcom,rpmcc.h
701 + * Copyright 2015 Linaro Limited
703 + * This software is licensed under the terms of the GNU General Public
704 + * License version 2, as published by the Free Software Foundation, and
705 + * may be copied, distributed, and modified under those terms.
707 + * This program is distributed in the hope that it will be useful,
708 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
709 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
710 + * GNU General Public License for more details.
713 +#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
714 +#define _DT_BINDINGS_CLK_MSM_RPMCC_H
717 +#define RPM_SMD_XO_CLK_SRC 0
718 +#define RPM_SMD_XO_A_CLK_SRC 1
719 +#define RPM_SMD_PCNOC_CLK 2
720 +#define RPM_SMD_PCNOC_A_CLK 3
721 +#define RPM_SMD_SNOC_CLK 4
722 +#define RPM_SMD_SNOC_A_CLK 5
723 +#define RPM_SMD_BIMC_CLK 6
724 +#define RPM_SMD_BIMC_A_CLK 7
725 +#define RPM_SMD_QDSS_CLK 8
726 +#define RPM_SMD_QDSS_A_CLK 9
727 +#define RPM_SMD_BB_CLK1 10
728 +#define RPM_SMD_BB_CLK1_A 11
729 +#define RPM_SMD_BB_CLK2 12
730 +#define RPM_SMD_BB_CLK2_A 13
731 +#define RPM_SMD_RF_CLK1 14
732 +#define RPM_SMD_RF_CLK1_A 15
733 +#define RPM_SMD_RF_CLK2 16
734 +#define RPM_SMD_RF_CLK2_A 17
735 +#define RPM_SMD_BB_CLK1_PIN 18
736 +#define RPM_SMD_BB_CLK1_A_PIN 19
737 +#define RPM_SMD_BB_CLK2_PIN 20
738 +#define RPM_SMD_BB_CLK2_A_PIN 21
739 +#define RPM_SMD_RF_CLK1_PIN 22
740 +#define RPM_SMD_RF_CLK1_A_PIN 23
741 +#define RPM_SMD_RF_CLK2_PIN 24
742 +#define RPM_SMD_RF_CLK2_A_PIN 25