target/linux/ipq806x/patches-4.9/0021-qcom-ipq4019-use-v2-of-the-kpss-bringup-mechanism.patch

   1 From 644ad7209637b02a0ca6d72f0715a9f52532fc70 Mon Sep 17 00:00:00 2001
   2 From: Matthew McClintock <mmcclint@codeaurora.org>
   3 Date: Fri, 8 Apr 2016 15:26:10 -0500
   4 Subject: [PATCH 21/69] qcom: ipq4019: use v2 of the kpss bringup mechanism
   5
   6 v1 was the incorrect choice here and sometimes the board would not come
   7 up properly
   8
   9 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
  10 ---
  11  arch/arm/boot/dts/qcom-ipq4019.dtsi | 32 ++++++++++++++++++++++++--------
  12  1 file changed, 24 insertions(+), 8 deletions(-)
  13
  14 diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  15 index f7a3b6fe7c1e..7b41c6883bfe 100644
  16 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  17 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  18 @@ -34,7 +34,8 @@
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a7";
  22 -                       enable-method = "qcom,kpss-acc-v1";
  23 +                       enable-method = "qcom,kpss-acc-v2";
  24 +                       next-level-cache = <&L2>;
  25                         qcom,acc = <&acc0>;
  26                         qcom,saw = <&saw0>;
  27                         reg = <0x0>;
  28 @@ -46,7 +47,8 @@
  29                 cpu@1 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a7";
  32 -                       enable-method = "qcom,kpss-acc-v1";
  33 +                       enable-method = "qcom,kpss-acc-v2";
  34 +                       next-level-cache = <&L2>;
  35                         qcom,acc = <&acc1>;
  36                         qcom,saw = <&saw1>;
  37                         reg = <0x1>;
  38 @@ -58,7 +60,8 @@
  39                 cpu@2 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a7";
  42 -                       enable-method = "qcom,kpss-acc-v1";
  43 +                       enable-method = "qcom,kpss-acc-v2";
  44 +                       next-level-cache = <&L2>;
  45                         qcom,acc = <&acc2>;
  46                         qcom,saw = <&saw2>;
  47                         reg = <0x2>;
  48 @@ -70,7 +73,8 @@
  49                 cpu@3 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a7";
  52 -                       enable-method = "qcom,kpss-acc-v1";
  53 +                       enable-method = "qcom,kpss-acc-v2";
  54 +                       next-level-cache = <&L2>;
  55                         qcom,acc = <&acc3>;
  56                         qcom,saw = <&saw3>;
  57                         reg = <0x3>;
  58 @@ -100,6 +104,12 @@
  59                         opp-hz = /bits/ 64 <666000000>;
  60                         clock-latency-ns = <256000>;
  61                 };
  62 +
  63 +               L2: l2-cache {
  64 +                       compatible = "qcom,arch-cache";
  65 +                       cache-level = <2>;
  66 +                       qcom,saw = <&saw_l2>;
  67 +               };
  68         };
  69
  70         pmu {
  71 @@ -212,22 +222,22 @@
  72                 };
  73
  74                  acc0: clock-controller@b088000 {
  75 -                        compatible = "qcom,kpss-acc-v1";
  76 +                        compatible = "qcom,kpss-acc-v2";
  77                          reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
  78                  };
  79
  80                  acc1: clock-controller@b098000 {
  81 -                        compatible = "qcom,kpss-acc-v1";
  82 +                        compatible = "qcom,kpss-acc-v2";
  83                          reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
  84                  };
  85
  86                  acc2: clock-controller@b0a8000 {
  87 -                        compatible = "qcom,kpss-acc-v1";
  88 +                        compatible = "qcom,kpss-acc-v2";
  89                          reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
  90                  };
  91
  92                  acc3: clock-controller@b0b8000 {
  93 -                        compatible = "qcom,kpss-acc-v1";
  94 +                        compatible = "qcom,kpss-acc-v2";
  95                          reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
  96                  };
  97
  98 @@ -255,6 +265,12 @@
  99                          regulator;
 100                  };
 101
 102 +               saw_l2: regulator@b012000 {
 103 +                       compatible = "qcom,saw2";
 104 +                       reg = <0xb012000 0x1000>;
 105 +                       regulator;
 106 +               };
 107 +
 108                 serial@78af000 {
 109                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 110                         reg = <0x78af000 0x200>;
 111 --
 112 2.11.0
 113