target/linux/ipq806x/patches-4.9/0002-dmaengine-Add-ADM-driver.patch

   1 From 563fa24db4e529c5a3311928d73a8a90531ee527 Mon Sep 17 00:00:00 2001
   2 From: Thomas Pedersen <twp@codeaurora.org>
   3 Date: Mon, 16 May 2016 17:58:51 -0700
   4 Subject: [PATCH 02/69] dmaengine: Add ADM driver
   5
   6 Original patch by Andy Gross.
   7
   8 Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA
   9 controller found in the MSM8x60 and IPQ/APQ8064 platforms.
  10
  11 The ADM supports both memory to memory transactions and memory
  12 to/from peripheral device transactions.  The controller also provides flow
  13 control capabilities for transactions to/from peripheral devices.
  14
  15 The initial release of this driver supports slave transfers to/from peripherals
  16 and also incorporates CRCI (client rate control interface) flow control.
  17
  18 Signed-off-by: Andy Gross <agross@codeaurora.org>
  19 Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
  20 ---
  21  drivers/dma/qcom/Kconfig    |  10 +
  22  drivers/dma/qcom/Makefile   |   1 +
  23  drivers/dma/qcom/qcom_adm.c | 900 ++++++++++++++++++++++++++++++++++++++++++++
  24  3 files changed, 911 insertions(+)
  25  create mode 100644 drivers/dma/qcom/qcom_adm.c
  26
  27 diff --git a/drivers/dma/qcom/Kconfig b/drivers/dma/qcom/Kconfig
  28 index a7761c4025f4..a88769ec9223 100644
  29 --- a/drivers/dma/qcom/Kconfig
  30 +++ b/drivers/dma/qcom/Kconfig
  31 @@ -27,3 +27,13 @@ config QCOM_HIDMA
  32           (user to kernel, kernel to kernel, etc.).  It only supports
  33           memcpy interface. The core is not intended for general
  34           purpose slave DMA.
  35 +
  36 +config QCOM_ADM
  37 +       tristate "Qualcomm ADM support"
  38 +       depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM)
  39 +       select DMA_ENGINE
  40 +       select DMA_VIRTUAL_CHANNELS
  41 +       ---help---
  42 +         Enable support for the Qualcomm ADM DMA controller.  This controller
  43 +         provides DMA capabilities for both general purpose and on-chip
  44 +         peripheral devices.
  45 diff --git a/drivers/dma/qcom/Makefile b/drivers/dma/qcom/Makefile
  46 index 4bfc38b45220..b55776993a99 100644
  47 --- a/drivers/dma/qcom/Makefile
  48 +++ b/drivers/dma/qcom/Makefile
  49 @@ -3,3 +3,4 @@ obj-$(CONFIG_QCOM_HIDMA_MGMT) += hdma_mgmt.o
  50  hdma_mgmt-objs  := hidma_mgmt.o hidma_mgmt_sys.o
  51  obj-$(CONFIG_QCOM_HIDMA) +=  hdma.o
  52  hdma-objs        := hidma_ll.o hidma.o hidma_dbg.o
  53 +obj-$(CONFIG_QCOM_ADM) += qcom_adm.o
  54 diff --git a/drivers/dma/qcom/qcom_adm.c b/drivers/dma/qcom/qcom_adm.c
  55 new file mode 100644
  56 index 000000000000..e4485f312f45
  57 --- /dev/null
  58 +++ b/drivers/dma/qcom/qcom_adm.c
  59 @@ -0,0 +1,900 @@
  60 +/*
  61 + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
  62 + *
  63 + * This program is free software; you can redistribute it and/or modify
  64 + * it under the terms of the GNU General Public License version 2 and
  65 + * only version 2 as published by the Free Software Foundation.
  66 + *
  67 + * This program is distributed in the hope that it will be useful,
  68 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  69 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  70 + * GNU General Public License for more details.
  71 + *
  72 + */
  73 +
  74 +#include <linux/kernel.h>
  75 +#include <linux/io.h>
  76 +#include <linux/init.h>
  77 +#include <linux/slab.h>
  78 +#include <linux/module.h>
  79 +#include <linux/interrupt.h>
  80 +#include <linux/dma-mapping.h>
  81 +#include <linux/scatterlist.h>
  82 +#include <linux/device.h>
  83 +#include <linux/platform_device.h>
  84 +#include <linux/of.h>
  85 +#include <linux/of_address.h>
  86 +#include <linux/of_irq.h>
  87 +#include <linux/of_dma.h>
  88 +#include <linux/reset.h>
  89 +#include <linux/clk.h>
  90 +#include <linux/dmaengine.h>
  91 +
  92 +#include "../dmaengine.h"
  93 +#include "../virt-dma.h"
  94 +
  95 +/* ADM registers - calculated from channel number and security domain */
  96 +#define ADM_CHAN_MULTI                 0x4
  97 +#define ADM_CI_MULTI                   0x4
  98 +#define ADM_CRCI_MULTI                 0x4
  99 +#define ADM_EE_MULTI                   0x800
 100 +#define ADM_CHAN_OFFS(chan)            (ADM_CHAN_MULTI * chan)
 101 +#define ADM_EE_OFFS(ee)                        (ADM_EE_MULTI * ee)
 102 +#define ADM_CHAN_EE_OFFS(chan, ee)     (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee))
 103 +#define ADM_CHAN_OFFS(chan)            (ADM_CHAN_MULTI * chan)
 104 +#define ADM_CI_OFFS(ci)                        (ADM_CHAN_OFF(ci))
 105 +#define ADM_CH_CMD_PTR(chan, ee)       (ADM_CHAN_EE_OFFS(chan, ee))
 106 +#define ADM_CH_RSLT(chan, ee)          (0x40 + ADM_CHAN_EE_OFFS(chan, ee))
 107 +#define ADM_CH_FLUSH_STATE0(chan, ee)  (0x80 + ADM_CHAN_EE_OFFS(chan, ee))
 108 +#define ADM_CH_STATUS_SD(chan, ee)     (0x200 + ADM_CHAN_EE_OFFS(chan, ee))
 109 +#define ADM_CH_CONF(chan)              (0x240 + ADM_CHAN_OFFS(chan))
 110 +#define ADM_CH_RSLT_CONF(chan, ee)     (0x300 + ADM_CHAN_EE_OFFS(chan, ee))
 111 +#define ADM_SEC_DOMAIN_IRQ_STATUS(ee)  (0x380 + ADM_EE_OFFS(ee))
 112 +#define ADM_CI_CONF(ci)                        (0x390 + ci * ADM_CI_MULTI)
 113 +#define ADM_GP_CTL                     0x3d8
 114 +#define ADM_CRCI_CTL(crci, ee)         (0x400 + crci * ADM_CRCI_MULTI + \
 115 +                                               ADM_EE_OFFS(ee))
 116 +
 117 +/* channel status */
 118 +#define ADM_CH_STATUS_VALID    BIT(1)
 119 +
 120 +/* channel result */
 121 +#define ADM_CH_RSLT_VALID      BIT(31)
 122 +#define ADM_CH_RSLT_ERR                BIT(3)
 123 +#define ADM_CH_RSLT_FLUSH      BIT(2)
 124 +#define ADM_CH_RSLT_TPD                BIT(1)
 125 +
 126 +/* channel conf */
 127 +#define ADM_CH_CONF_SHADOW_EN          BIT(12)
 128 +#define ADM_CH_CONF_MPU_DISABLE                BIT(11)
 129 +#define ADM_CH_CONF_PERM_MPU_CONF      BIT(9)
 130 +#define ADM_CH_CONF_FORCE_RSLT_EN      BIT(7)
 131 +#define ADM_CH_CONF_SEC_DOMAIN(ee)     (((ee & 0x3) << 4) | ((ee & 0x4) << 11))
 132 +
 133 +/* channel result conf */
 134 +#define ADM_CH_RSLT_CONF_FLUSH_EN      BIT(1)
 135 +#define ADM_CH_RSLT_CONF_IRQ_EN                BIT(0)
 136 +
 137 +/* CRCI CTL */
 138 +#define ADM_CRCI_CTL_MUX_SEL   BIT(18)
 139 +#define ADM_CRCI_CTL_RST       BIT(17)
 140 +
 141 +/* CI configuration */
 142 +#define ADM_CI_RANGE_END(x)    (x << 24)
 143 +#define ADM_CI_RANGE_START(x)  (x << 16)
 144 +#define ADM_CI_BURST_4_WORDS   BIT(2)
 145 +#define ADM_CI_BURST_8_WORDS   BIT(3)
 146 +
 147 +/* GP CTL */
 148 +#define ADM_GP_CTL_LP_EN       BIT(12)
 149 +#define ADM_GP_CTL_LP_CNT(x)   (x << 8)
 150 +
 151 +/* Command pointer list entry */
 152 +#define ADM_CPLE_LP            BIT(31)
 153 +#define ADM_CPLE_CMD_PTR_LIST  BIT(29)
 154 +
 155 +/* Command list entry */
 156 +#define ADM_CMD_LC             BIT(31)
 157 +#define ADM_CMD_DST_CRCI(n)    (((n) & 0xf) << 7)
 158 +#define ADM_CMD_SRC_CRCI(n)    (((n) & 0xf) << 3)
 159 +
 160 +#define ADM_CMD_TYPE_SINGLE    0x0
 161 +#define ADM_CMD_TYPE_BOX       0x3
 162 +
 163 +#define ADM_CRCI_MUX_SEL       BIT(4)
 164 +#define ADM_DESC_ALIGN         8
 165 +#define ADM_MAX_XFER           (SZ_64K-1)
 166 +#define ADM_MAX_ROWS           (SZ_64K-1)
 167 +#define ADM_MAX_CHANNELS       16
 168 +
 169 +struct adm_desc_hw_box {
 170 +       u32 cmd;
 171 +       u32 src_addr;
 172 +       u32 dst_addr;
 173 +       u32 row_len;
 174 +       u32 num_rows;
 175 +       u32 row_offset;
 176 +};
 177 +
 178 +struct adm_desc_hw_single {
 179 +       u32 cmd;
 180 +       u32 src_addr;
 181 +       u32 dst_addr;
 182 +       u32 len;
 183 +};
 184 +
 185 +struct adm_async_desc {
 186 +       struct virt_dma_desc vd;
 187 +       struct adm_device *adev;
 188 +
 189 +       size_t length;
 190 +       enum dma_transfer_direction dir;
 191 +       dma_addr_t dma_addr;
 192 +       size_t dma_len;
 193 +
 194 +       void *cpl;
 195 +       dma_addr_t cp_addr;
 196 +       u32 crci;
 197 +       u32 mux;
 198 +       u32 blk_size;
 199 +};
 200 +
 201 +struct adm_chan {
 202 +       struct virt_dma_chan vc;
 203 +       struct adm_device *adev;
 204 +
 205 +       /* parsed from DT */
 206 +       u32 id;                 /* channel id */
 207 +
 208 +       struct adm_async_desc *curr_txd;
 209 +       struct dma_slave_config slave;
 210 +       struct list_head node;
 211 +
 212 +       int error;
 213 +       int initialized;
 214 +};
 215 +
 216 +static inline struct adm_chan *to_adm_chan(struct dma_chan *common)
 217 +{
 218 +       return container_of(common, struct adm_chan, vc.chan);
 219 +}
 220 +
 221 +struct adm_device {
 222 +       void __iomem *regs;
 223 +       struct device *dev;
 224 +       struct dma_device common;
 225 +       struct device_dma_parameters dma_parms;
 226 +       struct adm_chan *channels;
 227 +
 228 +       u32 ee;
 229 +
 230 +       struct clk *core_clk;
 231 +       struct clk *iface_clk;
 232 +
 233 +       struct reset_control *clk_reset;
 234 +       struct reset_control *c0_reset;
 235 +       struct reset_control *c1_reset;
 236 +       struct reset_control *c2_reset;
 237 +       int irq;
 238 +};
 239 +
 240 +/**
 241 + * adm_free_chan - Frees dma resources associated with the specific channel
 242 + *
 243 + * Free all allocated descriptors associated with this channel
 244 + *
 245 + */
 246 +static void adm_free_chan(struct dma_chan *chan)
 247 +{
 248 +       /* free all queued descriptors */
 249 +       vchan_free_chan_resources(to_virt_chan(chan));
 250 +}
 251 +
 252 +/**
 253 + * adm_get_blksize - Get block size from burst value
 254 + *
 255 + */
 256 +static int adm_get_blksize(unsigned int burst)
 257 +{
 258 +       int ret;
 259 +
 260 +       switch (burst) {
 261 +       case 16:
 262 +       case 32:
 263 +       case 64:
 264 +       case 128:
 265 +               ret = ffs(burst>>4) - 1;
 266 +               break;
 267 +       case 192:
 268 +               ret = 4;
 269 +               break;
 270 +       case 256:
 271 +               ret = 5;
 272 +               break;
 273 +       default:
 274 +               ret = -EINVAL;
 275 +               break;
 276 +       }
 277 +
 278 +       return ret;
 279 +}
 280 +
 281 +/**
 282 + * adm_process_fc_descriptors - Process descriptors for flow controlled xfers
 283 + *
 284 + * @achan: ADM channel
 285 + * @desc: Descriptor memory pointer
 286 + * @sg: Scatterlist entry
 287 + * @crci: CRCI value
 288 + * @burst: Burst size of transaction
 289 + * @direction: DMA transfer direction
 290 + */
 291 +static void *adm_process_fc_descriptors(struct adm_chan *achan,
 292 +       void *desc, struct scatterlist *sg, u32 crci, u32 burst,
 293 +       enum dma_transfer_direction direction)
 294 +{
 295 +       struct adm_desc_hw_box *box_desc = NULL;
 296 +       struct adm_desc_hw_single *single_desc;
 297 +       u32 remainder = sg_dma_len(sg);
 298 +       u32 rows, row_offset, crci_cmd;
 299 +       u32 mem_addr = sg_dma_address(sg);
 300 +       u32 *incr_addr = &mem_addr;
 301 +       u32 *src, *dst;
 302 +
 303 +       if (direction == DMA_DEV_TO_MEM) {
 304 +               crci_cmd = ADM_CMD_SRC_CRCI(crci);
 305 +               row_offset = burst;
 306 +               src = &achan->slave.src_addr;
 307 +               dst = &mem_addr;
 308 +       } else {
 309 +               crci_cmd = ADM_CMD_DST_CRCI(crci);
 310 +               row_offset = burst << 16;
 311 +               src = &mem_addr;
 312 +               dst = &achan->slave.dst_addr;
 313 +       }
 314 +
 315 +       while (remainder >= burst) {
 316 +               box_desc = desc;
 317 +               box_desc->cmd = ADM_CMD_TYPE_BOX | crci_cmd;
 318 +               box_desc->row_offset = row_offset;
 319 +               box_desc->src_addr = *src;
 320 +               box_desc->dst_addr = *dst;
 321 +
 322 +               rows = remainder / burst;
 323 +               rows = min_t(u32, rows, ADM_MAX_ROWS);
 324 +               box_desc->num_rows = rows << 16 | rows;
 325 +               box_desc->row_len = burst << 16 | burst;
 326 +
 327 +               *incr_addr += burst * rows;
 328 +               remainder -= burst * rows;
 329 +               desc += sizeof(*box_desc);
 330 +       }
 331 +
 332 +       /* if leftover bytes, do one single descriptor */
 333 +       if (remainder) {
 334 +               single_desc = desc;
 335 +               single_desc->cmd = ADM_CMD_TYPE_SINGLE | crci_cmd;
 336 +               single_desc->len = remainder;
 337 +               single_desc->src_addr = *src;
 338 +               single_desc->dst_addr = *dst;
 339 +               desc += sizeof(*single_desc);
 340 +
 341 +               if (sg_is_last(sg))
 342 +                       single_desc->cmd |= ADM_CMD_LC;
 343 +       } else {
 344 +               if (box_desc && sg_is_last(sg))
 345 +                       box_desc->cmd |= ADM_CMD_LC;
 346 +       }
 347 +
 348 +       return desc;
 349 +}
 350 +
 351 +/**
 352 + * adm_process_non_fc_descriptors - Process descriptors for non-fc xfers
 353 + *
 354 + * @achan: ADM channel
 355 + * @desc: Descriptor memory pointer
 356 + * @sg: Scatterlist entry
 357 + * @direction: DMA transfer direction
 358 + */
 359 +static void *adm_process_non_fc_descriptors(struct adm_chan *achan,
 360 +       void *desc, struct scatterlist *sg,
 361 +       enum dma_transfer_direction direction)
 362 +{
 363 +       struct adm_desc_hw_single *single_desc;
 364 +       u32 remainder = sg_dma_len(sg);
 365 +       u32 mem_addr = sg_dma_address(sg);
 366 +       u32 *incr_addr = &mem_addr;
 367 +       u32 *src, *dst;
 368 +
 369 +       if (direction == DMA_DEV_TO_MEM) {
 370 +               src = &achan->slave.src_addr;
 371 +               dst = &mem_addr;
 372 +       } else {
 373 +               src = &mem_addr;
 374 +               dst = &achan->slave.dst_addr;
 375 +       }
 376 +
 377 +       do {
 378 +               single_desc = desc;
 379 +               single_desc->cmd = ADM_CMD_TYPE_SINGLE;
 380 +               single_desc->src_addr = *src;
 381 +               single_desc->dst_addr = *dst;
 382 +               single_desc->len = (remainder > ADM_MAX_XFER) ?
 383 +                               ADM_MAX_XFER : remainder;
 384 +
 385 +               remainder -= single_desc->len;
 386 +               *incr_addr += single_desc->len;
 387 +               desc += sizeof(*single_desc);
 388 +       } while (remainder);
 389 +
 390 +       /* set last command if this is the end of the whole transaction */
 391 +       if (sg_is_last(sg))
 392 +               single_desc->cmd |= ADM_CMD_LC;
 393 +
 394 +       return desc;
 395 +}
 396 +
 397 +/**
 398 + * adm_prep_slave_sg - Prep slave sg transaction
 399 + *
 400 + * @chan: dma channel
 401 + * @sgl: scatter gather list
 402 + * @sg_len: length of sg
 403 + * @direction: DMA transfer direction
 404 + * @flags: DMA flags
 405 + * @context: transfer context (unused)
 406 + */
 407 +static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan,
 408 +       struct scatterlist *sgl, unsigned int sg_len,
 409 +       enum dma_transfer_direction direction, unsigned long flags,
 410 +       void *context)
 411 +{
 412 +       struct adm_chan *achan = to_adm_chan(chan);
 413 +       struct adm_device *adev = achan->adev;
 414 +       struct adm_async_desc *async_desc;
 415 +       struct scatterlist *sg;
 416 +       u32 i, burst;
 417 +       u32 single_count = 0, box_count = 0, crci = 0;
 418 +       void *desc;
 419 +       u32 *cple;
 420 +       int blk_size = 0;
 421 +
 422 +       if (!is_slave_direction(direction)) {
 423 +               dev_err(adev->dev, "invalid dma direction\n");
 424 +               return NULL;
 425 +       }
 426 +
 427 +       /*
 428 +        * get burst value from slave configuration
 429 +        */
 430 +       burst = (direction == DMA_MEM_TO_DEV) ?
 431 +               achan->slave.dst_maxburst :
 432 +               achan->slave.src_maxburst;
 433 +
 434 +       /* if using flow control, validate burst and crci values */
 435 +       if (achan->slave.device_fc) {
 436 +
 437 +               blk_size = adm_get_blksize(burst);
 438 +               if (blk_size < 0) {
 439 +                       dev_err(adev->dev, "invalid burst value: %d\n",
 440 +                               burst);
 441 +                       return ERR_PTR(-EINVAL);
 442 +               }
 443 +
 444 +               crci = achan->slave.slave_id & 0xf;
 445 +               if (!crci || achan->slave.slave_id > 0x1f) {
 446 +                       dev_err(adev->dev, "invalid crci value\n");
 447 +                       return ERR_PTR(-EINVAL);
 448 +               }
 449 +       }
 450 +
 451 +       /* iterate through sgs and compute allocation size of structures */
 452 +       for_each_sg(sgl, sg, sg_len, i) {
 453 +               if (achan->slave.device_fc) {
 454 +                       box_count += DIV_ROUND_UP(sg_dma_len(sg) / burst,
 455 +                                                 ADM_MAX_ROWS);
 456 +                       if (sg_dma_len(sg) % burst)
 457 +                               single_count++;
 458 +               } else {
 459 +                       single_count += DIV_ROUND_UP(sg_dma_len(sg),
 460 +                                                    ADM_MAX_XFER);
 461 +               }
 462 +       }
 463 +
 464 +       async_desc = kzalloc(sizeof(*async_desc), GFP_NOWAIT);
 465 +       if (!async_desc)
 466 +               return ERR_PTR(-ENOMEM);
 467 +
 468 +       if (crci)
 469 +               async_desc->mux = achan->slave.slave_id & ADM_CRCI_MUX_SEL ?
 470 +                                       ADM_CRCI_CTL_MUX_SEL : 0;
 471 +       async_desc->crci = crci;
 472 +       async_desc->blk_size = blk_size;
 473 +       async_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) +
 474 +                               box_count * sizeof(struct adm_desc_hw_box) +
 475 +                               sizeof(*cple) + 2 * ADM_DESC_ALIGN;
 476 +
 477 +       async_desc->cpl = dma_alloc_writecombine(adev->dev, async_desc->dma_len,
 478 +                               &async_desc->dma_addr, GFP_NOWAIT);
 479 +
 480 +       if (!async_desc->cpl) {
 481 +               kfree(async_desc);
 482 +               return ERR_PTR(-ENOMEM);
 483 +       }
 484 +
 485 +       async_desc->adev = adev;
 486 +
 487 +       /* both command list entry and descriptors must be 8 byte aligned */
 488 +       cple = PTR_ALIGN(async_desc->cpl, ADM_DESC_ALIGN);
 489 +       desc = PTR_ALIGN(cple + 1, ADM_DESC_ALIGN);
 490 +
 491 +       /* init cmd list */
 492 +       *cple = ADM_CPLE_LP;
 493 +       *cple |= (desc - async_desc->cpl + async_desc->dma_addr) >> 3;
 494 +
 495 +       for_each_sg(sgl, sg, sg_len, i) {
 496 +               async_desc->length += sg_dma_len(sg);
 497 +
 498 +               if (achan->slave.device_fc)
 499 +                       desc = adm_process_fc_descriptors(achan, desc, sg, crci,
 500 +                                                       burst, direction);
 501 +               else
 502 +                       desc = adm_process_non_fc_descriptors(achan, desc, sg,
 503 +                                                          direction);
 504 +       }
 505 +
 506 +       return vchan_tx_prep(&achan->vc, &async_desc->vd, flags);
 507 +}
 508 +
 509 +/**
 510 + * adm_terminate_all - terminate all transactions on a channel
 511 + * @achan: adm dma channel
 512 + *
 513 + * Dequeues and frees all transactions, aborts current transaction
 514 + * No callbacks are done
 515 + *
 516 + */
 517 +static int adm_terminate_all(struct dma_chan *chan)
 518 +{
 519 +       struct adm_chan *achan = to_adm_chan(chan);
 520 +       struct adm_device *adev = achan->adev;
 521 +       unsigned long flags;
 522 +       LIST_HEAD(head);
 523 +
 524 +       spin_lock_irqsave(&achan->vc.lock, flags);
 525 +       vchan_get_all_descriptors(&achan->vc, &head);
 526 +
 527 +       /* send flush command to terminate current transaction */
 528 +       writel_relaxed(0x0,
 529 +               adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee));
 530 +
 531 +       spin_unlock_irqrestore(&achan->vc.lock, flags);
 532 +
 533 +       vchan_dma_desc_free_list(&achan->vc, &head);
 534 +
 535 +       return 0;
 536 +}
 537 +
 538 +static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg)
 539 +{
 540 +       struct adm_chan *achan = to_adm_chan(chan);
 541 +       unsigned long flag;
 542 +
 543 +       spin_lock_irqsave(&achan->vc.lock, flag);
 544 +       memcpy(&achan->slave, cfg, sizeof(struct dma_slave_config));
 545 +       spin_unlock_irqrestore(&achan->vc.lock, flag);
 546 +
 547 +       return 0;
 548 +}
 549 +
 550 +/**
 551 + * adm_start_dma - start next transaction
 552 + * @achan - ADM dma channel
 553 + */
 554 +static void adm_start_dma(struct adm_chan *achan)
 555 +{
 556 +       struct virt_dma_desc *vd = vchan_next_desc(&achan->vc);
 557 +       struct adm_device *adev = achan->adev;
 558 +       struct adm_async_desc *async_desc;
 559 +
 560 +       lockdep_assert_held(&achan->vc.lock);
 561 +
 562 +       if (!vd)
 563 +               return;
 564 +
 565 +       list_del(&vd->node);
 566 +
 567 +       /* write next command list out to the CMD FIFO */
 568 +       async_desc = container_of(vd, struct adm_async_desc, vd);
 569 +       achan->curr_txd = async_desc;
 570 +
 571 +       /* reset channel error */
 572 +       achan->error = 0;
 573 +
 574 +       if (!achan->initialized) {
 575 +               /* enable interrupts */
 576 +               writel(ADM_CH_CONF_SHADOW_EN |
 577 +                      ADM_CH_CONF_PERM_MPU_CONF |
 578 +                      ADM_CH_CONF_MPU_DISABLE |
 579 +                      ADM_CH_CONF_SEC_DOMAIN(adev->ee),
 580 +                      adev->regs + ADM_CH_CONF(achan->id));
 581 +
 582 +               writel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN,
 583 +                       adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
 584 +
 585 +               achan->initialized = 1;
 586 +       }
 587 +
 588 +       /* set the crci block size if this transaction requires CRCI */
 589 +       if (async_desc->crci) {
 590 +               writel(async_desc->mux | async_desc->blk_size,
 591 +                       adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee));
 592 +       }
 593 +
 594 +       /* make sure IRQ enable doesn't get reordered */
 595 +       wmb();
 596 +
 597 +       /* write next command list out to the CMD FIFO */
 598 +       writel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3,
 599 +               adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee));
 600 +}
 601 +
 602 +/**
 603 + * adm_dma_irq - irq handler for ADM controller
 604 + * @irq: IRQ of interrupt
 605 + * @data: callback data
 606 + *
 607 + * IRQ handler for the bam controller
 608 + */
 609 +static irqreturn_t adm_dma_irq(int irq, void *data)
 610 +{
 611 +       struct adm_device *adev = data;
 612 +       u32 srcs, i;
 613 +       struct adm_async_desc *async_desc;
 614 +       unsigned long flags;
 615 +
 616 +       srcs = readl_relaxed(adev->regs +
 617 +                       ADM_SEC_DOMAIN_IRQ_STATUS(adev->ee));
 618 +
 619 +       for (i = 0; i < ADM_MAX_CHANNELS; i++) {
 620 +               struct adm_chan *achan = &adev->channels[i];
 621 +               u32 status, result;
 622 +
 623 +               if (srcs & BIT(i)) {
 624 +                       status = readl_relaxed(adev->regs +
 625 +                               ADM_CH_STATUS_SD(i, adev->ee));
 626 +
 627 +                       /* if no result present, skip */
 628 +                       if (!(status & ADM_CH_STATUS_VALID))
 629 +                               continue;
 630 +
 631 +                       result = readl_relaxed(adev->regs +
 632 +                               ADM_CH_RSLT(i, adev->ee));
 633 +
 634 +                       /* no valid results, skip */
 635 +                       if (!(result & ADM_CH_RSLT_VALID))
 636 +                               continue;
 637 +
 638 +                       /* flag error if transaction was flushed or failed */
 639 +                       if (result & (ADM_CH_RSLT_ERR | ADM_CH_RSLT_FLUSH))
 640 +                               achan->error = 1;
 641 +
 642 +                       spin_lock_irqsave(&achan->vc.lock, flags);
 643 +                       async_desc = achan->curr_txd;
 644 +
 645 +                       achan->curr_txd = NULL;
 646 +
 647 +                       if (async_desc) {
 648 +                               vchan_cookie_complete(&async_desc->vd);
 649 +
 650 +                               /* kick off next DMA */
 651 +                               adm_start_dma(achan);
 652 +                       }
 653 +
 654 +                       spin_unlock_irqrestore(&achan->vc.lock, flags);
 655 +               }
 656 +       }
 657 +
 658 +       return IRQ_HANDLED;
 659 +}
 660 +
 661 +/**
 662 + * adm_tx_status - returns status of transaction
 663 + * @chan: dma channel
 664 + * @cookie: transaction cookie
 665 + * @txstate: DMA transaction state
 666 + *
 667 + * Return status of dma transaction
 668 + */
 669 +static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
 670 +       struct dma_tx_state *txstate)
 671 +{
 672 +       struct adm_chan *achan = to_adm_chan(chan);
 673 +       struct virt_dma_desc *vd;
 674 +       enum dma_status ret;
 675 +       unsigned long flags;
 676 +       size_t residue = 0;
 677 +
 678 +       ret = dma_cookie_status(chan, cookie, txstate);
 679 +       if (ret == DMA_COMPLETE || !txstate)
 680 +               return ret;
 681 +
 682 +       spin_lock_irqsave(&achan->vc.lock, flags);
 683 +
 684 +       vd = vchan_find_desc(&achan->vc, cookie);
 685 +       if (vd)
 686 +               residue = container_of(vd, struct adm_async_desc, vd)->length;
 687 +
 688 +       spin_unlock_irqrestore(&achan->vc.lock, flags);
 689 +
 690 +       /*
 691 +        * residue is either the full length if it is in the issued list, or 0
 692 +        * if it is in progress.  We have no reliable way of determining
 693 +        * anything inbetween
 694 +       */
 695 +       dma_set_residue(txstate, residue);
 696 +
 697 +       if (achan->error)
 698 +               return DMA_ERROR;
 699 +
 700 +       return ret;
 701 +}
 702 +
 703 +/**
 704 + * adm_issue_pending - starts pending transactions
 705 + * @chan: dma channel
 706 + *
 707 + * Issues all pending transactions and starts DMA
 708 + */
 709 +static void adm_issue_pending(struct dma_chan *chan)
 710 +{
 711 +       struct adm_chan *achan = to_adm_chan(chan);
 712 +       unsigned long flags;
 713 +
 714 +       spin_lock_irqsave(&achan->vc.lock, flags);
 715 +
 716 +       if (vchan_issue_pending(&achan->vc) && !achan->curr_txd)
 717 +               adm_start_dma(achan);
 718 +       spin_unlock_irqrestore(&achan->vc.lock, flags);
 719 +}
 720 +
 721 +/**
 722 + * adm_dma_free_desc - free descriptor memory
 723 + * @vd: virtual descriptor
 724 + *
 725 + */
 726 +static void adm_dma_free_desc(struct virt_dma_desc *vd)
 727 +{
 728 +       struct adm_async_desc *async_desc = container_of(vd,
 729 +                       struct adm_async_desc, vd);
 730 +
 731 +       dma_free_writecombine(async_desc->adev->dev, async_desc->dma_len,
 732 +               async_desc->cpl, async_desc->dma_addr);
 733 +       kfree(async_desc);
 734 +}
 735 +
 736 +static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan,
 737 +       u32 index)
 738 +{
 739 +       achan->id = index;
 740 +       achan->adev = adev;
 741 +
 742 +       vchan_init(&achan->vc, &adev->common);
 743 +       achan->vc.desc_free = adm_dma_free_desc;
 744 +}
 745 +
 746 +static int adm_dma_probe(struct platform_device *pdev)
 747 +{
 748 +       struct adm_device *adev;
 749 +       struct resource *iores;
 750 +       int ret;
 751 +       u32 i;
 752 +
 753 +       adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
 754 +       if (!adev)
 755 +               return -ENOMEM;
 756 +
 757 +       adev->dev = &pdev->dev;
 758 +
 759 +       iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 760 +       adev->regs = devm_ioremap_resource(&pdev->dev, iores);
 761 +       if (IS_ERR(adev->regs))
 762 +               return PTR_ERR(adev->regs);
 763 +
 764 +       adev->irq = platform_get_irq(pdev, 0);
 765 +       if (adev->irq < 0)
 766 +               return adev->irq;
 767 +
 768 +       ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &adev->ee);
 769 +       if (ret) {
 770 +               dev_err(adev->dev, "Execution environment unspecified\n");
 771 +               return ret;
 772 +       }
 773 +
 774 +       adev->core_clk = devm_clk_get(adev->dev, "core");
 775 +       if (IS_ERR(adev->core_clk))
 776 +               return PTR_ERR(adev->core_clk);
 777 +
 778 +       ret = clk_prepare_enable(adev->core_clk);
 779 +       if (ret) {
 780 +               dev_err(adev->dev, "failed to prepare/enable core clock\n");
 781 +               return ret;
 782 +       }
 783 +
 784 +       adev->iface_clk = devm_clk_get(adev->dev, "iface");
 785 +       if (IS_ERR(adev->iface_clk)) {
 786 +               ret = PTR_ERR(adev->iface_clk);
 787 +               goto err_disable_core_clk;
 788 +       }
 789 +
 790 +       ret = clk_prepare_enable(adev->iface_clk);
 791 +       if (ret) {
 792 +               dev_err(adev->dev, "failed to prepare/enable iface clock\n");
 793 +               goto err_disable_core_clk;
 794 +       }
 795 +
 796 +       adev->clk_reset = devm_reset_control_get(&pdev->dev, "clk");
 797 +       if (IS_ERR(adev->clk_reset)) {
 798 +               dev_err(adev->dev, "failed to get ADM0 reset\n");
 799 +               ret = PTR_ERR(adev->clk_reset);
 800 +               goto err_disable_clks;
 801 +       }
 802 +
 803 +       adev->c0_reset = devm_reset_control_get(&pdev->dev, "c0");
 804 +       if (IS_ERR(adev->c0_reset)) {
 805 +               dev_err(adev->dev, "failed to get ADM0 C0 reset\n");
 806 +               ret = PTR_ERR(adev->c0_reset);
 807 +               goto err_disable_clks;
 808 +       }
 809 +
 810 +       adev->c1_reset = devm_reset_control_get(&pdev->dev, "c1");
 811 +       if (IS_ERR(adev->c1_reset)) {
 812 +               dev_err(adev->dev, "failed to get ADM0 C1 reset\n");
 813 +               ret = PTR_ERR(adev->c1_reset);
 814 +               goto err_disable_clks;
 815 +       }
 816 +
 817 +       adev->c2_reset = devm_reset_control_get(&pdev->dev, "c2");
 818 +       if (IS_ERR(adev->c2_reset)) {
 819 +               dev_err(adev->dev, "failed to get ADM0 C2 reset\n");
 820 +               ret = PTR_ERR(adev->c2_reset);
 821 +               goto err_disable_clks;
 822 +       }
 823 +
 824 +       reset_control_assert(adev->clk_reset);
 825 +       reset_control_assert(adev->c0_reset);
 826 +       reset_control_assert(adev->c1_reset);
 827 +       reset_control_assert(adev->c2_reset);
 828 +
 829 +       reset_control_deassert(adev->clk_reset);
 830 +       reset_control_deassert(adev->c0_reset);
 831 +       reset_control_deassert(adev->c1_reset);
 832 +       reset_control_deassert(adev->c2_reset);
 833 +
 834 +       adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS,
 835 +                               sizeof(*adev->channels), GFP_KERNEL);
 836 +
 837 +       if (!adev->channels) {
 838 +               ret = -ENOMEM;
 839 +               goto err_disable_clks;
 840 +       }
 841 +
 842 +       /* allocate and initialize channels */
 843 +       INIT_LIST_HEAD(&adev->common.channels);
 844 +
 845 +       for (i = 0; i < ADM_MAX_CHANNELS; i++)
 846 +               adm_channel_init(adev, &adev->channels[i], i);
 847 +
 848 +       /* reset CRCIs */
 849 +       for (i = 0; i < 16; i++)
 850 +               writel(ADM_CRCI_CTL_RST, adev->regs +
 851 +                       ADM_CRCI_CTL(i, adev->ee));
 852 +
 853 +       /* configure client interfaces */
 854 +       writel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) |
 855 +               ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0));
 856 +       writel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) |
 857 +               ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1));
 858 +       writel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) |
 859 +               ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2));
 860 +       writel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf),
 861 +               adev->regs + ADM_GP_CTL);
 862 +
 863 +       ret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq,
 864 +                       0, "adm_dma", adev);
 865 +       if (ret)
 866 +               goto err_disable_clks;
 867 +
 868 +       platform_set_drvdata(pdev, adev);
 869 +
 870 +       adev->common.dev = adev->dev;
 871 +       adev->common.dev->dma_parms = &adev->dma_parms;
 872 +
 873 +       /* set capabilities */
 874 +       dma_cap_zero(adev->common.cap_mask);
 875 +       dma_cap_set(DMA_SLAVE, adev->common.cap_mask);
 876 +       dma_cap_set(DMA_PRIVATE, adev->common.cap_mask);
 877 +
 878 +       /* initialize dmaengine apis */
 879 +       adev->common.directions = BIT(DMA_DEV_TO_MEM | DMA_MEM_TO_DEV);
 880 +       adev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
 881 +       adev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
 882 +       adev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
 883 +       adev->common.device_free_chan_resources = adm_free_chan;
 884 +       adev->common.device_prep_slave_sg = adm_prep_slave_sg;
 885 +       adev->common.device_issue_pending = adm_issue_pending;
 886 +       adev->common.device_tx_status = adm_tx_status;
 887 +       adev->common.device_terminate_all = adm_terminate_all;
 888 +       adev->common.device_config = adm_slave_config;
 889 +
 890 +       ret = dma_async_device_register(&adev->common);
 891 +       if (ret) {
 892 +               dev_err(adev->dev, "failed to register dma async device\n");
 893 +               goto err_disable_clks;
 894 +       }
 895 +
 896 +       ret = of_dma_controller_register(pdev->dev.of_node,
 897 +                                        of_dma_xlate_by_chan_id,
 898 +                                        &adev->common);
 899 +       if (ret)
 900 +               goto err_unregister_dma;
 901 +
 902 +       return 0;
 903 +
 904 +err_unregister_dma:
 905 +       dma_async_device_unregister(&adev->common);
 906 +err_disable_clks:
 907 +       clk_disable_unprepare(adev->iface_clk);
 908 +err_disable_core_clk:
 909 +       clk_disable_unprepare(adev->core_clk);
 910 +
 911 +       return ret;
 912 +}
 913 +
 914 +static int adm_dma_remove(struct platform_device *pdev)
 915 +{
 916 +       struct adm_device *adev = platform_get_drvdata(pdev);
 917 +       struct adm_chan *achan;
 918 +       u32 i;
 919 +
 920 +       of_dma_controller_free(pdev->dev.of_node);
 921 +       dma_async_device_unregister(&adev->common);
 922 +
 923 +       for (i = 0; i < ADM_MAX_CHANNELS; i++) {
 924 +               achan = &adev->channels[i];
 925 +
 926 +               /* mask IRQs for this channel/EE pair */
 927 +               writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
 928 +
 929 +               adm_terminate_all(&adev->channels[i].vc.chan);
 930 +       }
 931 +
 932 +       devm_free_irq(adev->dev, adev->irq, adev);
 933 +
 934 +       clk_disable_unprepare(adev->core_clk);
 935 +       clk_disable_unprepare(adev->iface_clk);
 936 +
 937 +       return 0;
 938 +}
 939 +
 940 +static const struct of_device_id adm_of_match[] = {
 941 +       { .compatible = "qcom,adm", },
 942 +       {}
 943 +};
 944 +MODULE_DEVICE_TABLE(of, adm_of_match);
 945 +
 946 +static struct platform_driver adm_dma_driver = {
 947 +       .probe = adm_dma_probe,
 948 +       .remove = adm_dma_remove,
 949 +       .driver = {
 950 +               .name = "adm-dma-engine",
 951 +               .of_match_table = adm_of_match,
 952 +       },
 953 +};
 954 +
 955 +module_platform_driver(adm_dma_driver);
 956 +
 957 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
 958 +MODULE_DESCRIPTION("QCOM ADM DMA engine driver");
 959 +MODULE_LICENSE("GPL v2");
 960 --
 961 2.11.0
 962