target/linux/ipq806x/patches/0136-ARM-ipq8064-ap148-Add-i2c-pinctrl-nodes.patch

   1 From e93b9480667cbd0e3a4276e8749279693fe239f4 Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Wed, 14 May 2014 22:49:03 -0500
   4 Subject: [PATCH 136/182] ARM: ipq8064-ap148: Add i2c pinctrl nodes
   5
   6 Signed-off-by: Andy Gross <agross@codeaurora.org>
   7 ---
   8  arch/arm/boot/dts/qcom-ipq8064-ap148.dts |   17 +++++++++++++++++
   9  arch/arm/boot/dts/qcom-ipq8064.dtsi      |   27 +++++++++++++++++++++++++++
  10  2 files changed, 44 insertions(+)
  11
  12 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  13 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  14 @@ -14,12 +14,29 @@
  15         };
  16
  17         soc {
  18 +               pinmux@800000 {
  19 +                       i2c4_pins: i2c4_pinmux {
  20 +                               pins = "gpio12", "gpio13";
  21 +                               function = "gsbi4";
  22 +                               bias-disable;
  23 +                       };
  24 +               };
  25 +
  26                 gsbi@16300000 {
  27                         qcom,mode = <GSBI_PROT_I2C_UART>;
  28                         status = "ok";
  29                         serial@16340000 {
  30                                 status = "ok";
  31                         };
  32 +
  33 +                       i2c4: i2c@16380000 {
  34 +                               status = "ok";
  35 +
  36 +                               clock-frequency = <200000>;
  37 +
  38 +                               pinctrl-0 = <&i2c4_pins>;
  39 +                               pinctrl-names = "default";
  40 +                       };
  41                 };
  42         };
  43  };
  44 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  45 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  46 @@ -137,6 +137,20 @@
  47                                 clock-names = "core", "iface";
  48                                 status = "disabled";
  49                         };
  50 +
  51 +                       i2c@124a0000 {
  52 +                               compatible = "qcom,i2c-qup-v1.1.1";
  53 +                               reg = <0x124a0000 0x1000>;
  54 +                               interrupts = <0 196 0>;
  55 +
  56 +                               clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
  57 +                               clock-names = "core", "iface";
  58 +                               status = "disabled";
  59 +
  60 +                               #address-cells = <1>;
  61 +                               #size-cells = <0>;
  62 +                       };
  63 +
  64                 };
  65
  66                 gsbi4: gsbi@16300000 {
  67 @@ -158,6 +172,19 @@
  68                                 clock-names = "core", "iface";
  69                                 status = "disabled";
  70                         };
  71 +
  72 +                       i2c@16380000 {
  73 +                               compatible = "qcom,i2c-qup-v1.1.1";
  74 +                               reg = <0x16380000 0x1000>;
  75 +                               interrupts = <0 153 0>;
  76 +
  77 +                               clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
  78 +                               clock-names = "core", "iface";
  79 +                               status = "disabled";
  80 +
  81 +                               #address-cells = <1>;
  82 +                               #size-cells = <0>;
  83 +                       };
  84                 };
  85
  86                 qcom,ssbi@500000 {