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kernel: update 3.14 to 3.14.18
[openwrt/staging/luka.git] / target / linux / ipq806x / patches / 0125-clk-qcom-Add-support-for-IPQ8064-s-global-clock-cont.patch
1 From 2e6dfaa714ba4bd70fa5dda07c525b6c15e44552 Mon Sep 17 00:00:00 2001
2 From: Kumar Gala <galak@codeaurora.org>
3 Date: Thu, 3 Apr 2014 13:47:07 -0500
4 Subject: [PATCH 125/182] clk: qcom: Add support for IPQ8064's global clock
5 controller (GCC)
6
7 Add a driver for the global clock controller found on IPQ8064 based
8 platforms. This should allow most non-multimedia device drivers to probe
9 and control their clocks.
10
11 This is currently missing clocks for USB HSIC and networking devices.
12
13 Signed-off-by: Kumar Gala <galak@codeaurora.org>
14 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
15 ---
16 .../devicetree/bindings/clock/qcom,gcc.txt | 1 +
17 drivers/clk/qcom/Kconfig | 8 +
18 drivers/clk/qcom/Makefile | 1 +
19 drivers/clk/qcom/gcc-ipq806x.c | 2424 ++++++++++++++++++++
20 include/dt-bindings/clock/qcom,gcc-ipq806x.h | 293 +++
21 include/dt-bindings/reset/qcom,gcc-ipq806x.h | 132 ++
22 6 files changed, 2859 insertions(+)
23 create mode 100644 drivers/clk/qcom/gcc-ipq806x.c
24 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq806x.h
25 create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq806x.h
26
27 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
28 +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
29 @@ -5,6 +5,7 @@ Required properties :
30 - compatible : shall contain only one of the following:
31
32 "qcom,gcc-apq8064"
33 + "qcom,gcc-ipq8064"
34 "qcom,gcc-msm8660"
35 "qcom,gcc-msm8960"
36 "qcom,gcc-msm8974"
37 --- a/drivers/clk/qcom/Kconfig
38 +++ b/drivers/clk/qcom/Kconfig
39 @@ -4,6 +4,14 @@ config COMMON_CLK_QCOM
40 select REGMAP_MMIO
41 select RESET_CONTROLLER
42
43 +config IPQ_GCC_806X
44 + tristate "IPQ806x Global Clock Controller"
45 + depends on COMMON_CLK_QCOM
46 + help
47 + Support for the global clock controller on ipq806x devices.
48 + Say Y if you want to use peripheral devices such as UART, SPI,
49 + i2c, USB, SD/eMMC, etc.
50 +
51 config MSM_GCC_8660
52 tristate "MSM8660 Global Clock Controller"
53 depends on COMMON_CLK_QCOM
54 --- a/drivers/clk/qcom/Makefile
55 +++ b/drivers/clk/qcom/Makefile
56 @@ -8,6 +8,7 @@ clk-qcom-y += clk-rcg2.o
57 clk-qcom-y += clk-branch.o
58 clk-qcom-y += reset.o
59
60 +obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
61 obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
62 obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
63 obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
64 --- /dev/null
65 +++ b/drivers/clk/qcom/gcc-ipq806x.c
66 @@ -0,0 +1,2424 @@
67 +/*
68 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
69 + *
70 + * This software is licensed under the terms of the GNU General Public
71 + * License version 2, as published by the Free Software Foundation, and
72 + * may be copied, distributed, and modified under those terms.
73 + *
74 + * This program is distributed in the hope that it will be useful,
75 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
76 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
77 + * GNU General Public License for more details.
78 + */
79 +
80 +#include <linux/kernel.h>
81 +#include <linux/bitops.h>
82 +#include <linux/err.h>
83 +#include <linux/platform_device.h>
84 +#include <linux/module.h>
85 +#include <linux/of.h>
86 +#include <linux/of_device.h>
87 +#include <linux/clk-provider.h>
88 +#include <linux/regmap.h>
89 +#include <linux/reset-controller.h>
90 +
91 +#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
92 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
93 +
94 +#include "common.h"
95 +#include "clk-regmap.h"
96 +#include "clk-pll.h"
97 +#include "clk-rcg.h"
98 +#include "clk-branch.h"
99 +#include "reset.h"
100 +
101 +static struct clk_pll pll3 = {
102 + .l_reg = 0x3164,
103 + .m_reg = 0x3168,
104 + .n_reg = 0x316c,
105 + .config_reg = 0x3174,
106 + .mode_reg = 0x3160,
107 + .status_reg = 0x3178,
108 + .status_bit = 16,
109 + .clkr.hw.init = &(struct clk_init_data){
110 + .name = "pll3",
111 + .parent_names = (const char *[]){ "pxo" },
112 + .num_parents = 1,
113 + .ops = &clk_pll_ops,
114 + },
115 +};
116 +
117 +static struct clk_pll pll8 = {
118 + .l_reg = 0x3144,
119 + .m_reg = 0x3148,
120 + .n_reg = 0x314c,
121 + .config_reg = 0x3154,
122 + .mode_reg = 0x3140,
123 + .status_reg = 0x3158,
124 + .status_bit = 16,
125 + .clkr.hw.init = &(struct clk_init_data){
126 + .name = "pll8",
127 + .parent_names = (const char *[]){ "pxo" },
128 + .num_parents = 1,
129 + .ops = &clk_pll_ops,
130 + },
131 +};
132 +
133 +static struct clk_regmap pll8_vote = {
134 + .enable_reg = 0x34c0,
135 + .enable_mask = BIT(8),
136 + .hw.init = &(struct clk_init_data){
137 + .name = "pll8_vote",
138 + .parent_names = (const char *[]){ "pll8" },
139 + .num_parents = 1,
140 + .ops = &clk_pll_vote_ops,
141 + },
142 +};
143 +
144 +static struct clk_pll pll14 = {
145 + .l_reg = 0x31c4,
146 + .m_reg = 0x31c8,
147 + .n_reg = 0x31cc,
148 + .config_reg = 0x31d4,
149 + .mode_reg = 0x31c0,
150 + .status_reg = 0x31d8,
151 + .status_bit = 16,
152 + .clkr.hw.init = &(struct clk_init_data){
153 + .name = "pll14",
154 + .parent_names = (const char *[]){ "pxo" },
155 + .num_parents = 1,
156 + .ops = &clk_pll_ops,
157 + },
158 +};
159 +
160 +static struct clk_regmap pll14_vote = {
161 + .enable_reg = 0x34c0,
162 + .enable_mask = BIT(14),
163 + .hw.init = &(struct clk_init_data){
164 + .name = "pll14_vote",
165 + .parent_names = (const char *[]){ "pll14" },
166 + .num_parents = 1,
167 + .ops = &clk_pll_vote_ops,
168 + },
169 +};
170 +
171 +#define P_PXO 0
172 +#define P_PLL8 1
173 +#define P_PLL3 1
174 +#define P_PLL0 2
175 +#define P_CXO 2
176 +
177 +static const u8 gcc_pxo_pll8_map[] = {
178 + [P_PXO] = 0,
179 + [P_PLL8] = 3,
180 +};
181 +
182 +static const char *gcc_pxo_pll8[] = {
183 + "pxo",
184 + "pll8_vote",
185 +};
186 +
187 +static const u8 gcc_pxo_pll8_cxo_map[] = {
188 + [P_PXO] = 0,
189 + [P_PLL8] = 3,
190 + [P_CXO] = 5,
191 +};
192 +
193 +static const char *gcc_pxo_pll8_cxo[] = {
194 + "pxo",
195 + "pll8_vote",
196 + "cxo",
197 +};
198 +
199 +static const u8 gcc_pxo_pll3_map[] = {
200 + [P_PXO] = 0,
201 + [P_PLL3] = 1,
202 +};
203 +
204 +static const u8 gcc_pxo_pll3_sata_map[] = {
205 + [P_PXO] = 0,
206 + [P_PLL3] = 6,
207 +};
208 +
209 +static const char *gcc_pxo_pll3[] = {
210 + "pxo",
211 + "pll3",
212 +};
213 +
214 +static const u8 gcc_pxo_pll8_pll0[] = {
215 + [P_PXO] = 0,
216 + [P_PLL8] = 3,
217 + [P_PLL0] = 2,
218 +};
219 +
220 +static const char *gcc_pxo_pll8_pll0_map[] = {
221 + "pxo",
222 + "pll8_vote",
223 + "pll0",
224 +};
225 +
226 +static struct freq_tbl clk_tbl_gsbi_uart[] = {
227 + { 1843200, P_PLL8, 2, 6, 625 },
228 + { 3686400, P_PLL8, 2, 12, 625 },
229 + { 7372800, P_PLL8, 2, 24, 625 },
230 + { 14745600, P_PLL8, 2, 48, 625 },
231 + { 16000000, P_PLL8, 4, 1, 6 },
232 + { 24000000, P_PLL8, 4, 1, 4 },
233 + { 32000000, P_PLL8, 4, 1, 3 },
234 + { 40000000, P_PLL8, 1, 5, 48 },
235 + { 46400000, P_PLL8, 1, 29, 240 },
236 + { 48000000, P_PLL8, 4, 1, 2 },
237 + { 51200000, P_PLL8, 1, 2, 15 },
238 + { 56000000, P_PLL8, 1, 7, 48 },
239 + { 58982400, P_PLL8, 1, 96, 625 },
240 + { 64000000, P_PLL8, 2, 1, 3 },
241 + { }
242 +};
243 +
244 +static struct clk_rcg gsbi1_uart_src = {
245 + .ns_reg = 0x29d4,
246 + .md_reg = 0x29d0,
247 + .mn = {
248 + .mnctr_en_bit = 8,
249 + .mnctr_reset_bit = 7,
250 + .mnctr_mode_shift = 5,
251 + .n_val_shift = 16,
252 + .m_val_shift = 16,
253 + .width = 16,
254 + },
255 + .p = {
256 + .pre_div_shift = 3,
257 + .pre_div_width = 2,
258 + },
259 + .s = {
260 + .src_sel_shift = 0,
261 + .parent_map = gcc_pxo_pll8_map,
262 + },
263 + .freq_tbl = clk_tbl_gsbi_uart,
264 + .clkr = {
265 + .enable_reg = 0x29d4,
266 + .enable_mask = BIT(11),
267 + .hw.init = &(struct clk_init_data){
268 + .name = "gsbi1_uart_src",
269 + .parent_names = gcc_pxo_pll8,
270 + .num_parents = 2,
271 + .ops = &clk_rcg_ops,
272 + .flags = CLK_SET_PARENT_GATE,
273 + },
274 + },
275 +};
276 +
277 +static struct clk_branch gsbi1_uart_clk = {
278 + .halt_reg = 0x2fcc,
279 + .halt_bit = 12,
280 + .clkr = {
281 + .enable_reg = 0x29d4,
282 + .enable_mask = BIT(9),
283 + .hw.init = &(struct clk_init_data){
284 + .name = "gsbi1_uart_clk",
285 + .parent_names = (const char *[]){
286 + "gsbi1_uart_src",
287 + },
288 + .num_parents = 1,
289 + .ops = &clk_branch_ops,
290 + .flags = CLK_SET_RATE_PARENT,
291 + },
292 + },
293 +};
294 +
295 +static struct clk_rcg gsbi2_uart_src = {
296 + .ns_reg = 0x29f4,
297 + .md_reg = 0x29f0,
298 + .mn = {
299 + .mnctr_en_bit = 8,
300 + .mnctr_reset_bit = 7,
301 + .mnctr_mode_shift = 5,
302 + .n_val_shift = 16,
303 + .m_val_shift = 16,
304 + .width = 16,
305 + },
306 + .p = {
307 + .pre_div_shift = 3,
308 + .pre_div_width = 2,
309 + },
310 + .s = {
311 + .src_sel_shift = 0,
312 + .parent_map = gcc_pxo_pll8_map,
313 + },
314 + .freq_tbl = clk_tbl_gsbi_uart,
315 + .clkr = {
316 + .enable_reg = 0x29f4,
317 + .enable_mask = BIT(11),
318 + .hw.init = &(struct clk_init_data){
319 + .name = "gsbi2_uart_src",
320 + .parent_names = gcc_pxo_pll8,
321 + .num_parents = 2,
322 + .ops = &clk_rcg_ops,
323 + .flags = CLK_SET_PARENT_GATE,
324 + },
325 + },
326 +};
327 +
328 +static struct clk_branch gsbi2_uart_clk = {
329 + .halt_reg = 0x2fcc,
330 + .halt_bit = 8,
331 + .clkr = {
332 + .enable_reg = 0x29f4,
333 + .enable_mask = BIT(9),
334 + .hw.init = &(struct clk_init_data){
335 + .name = "gsbi2_uart_clk",
336 + .parent_names = (const char *[]){
337 + "gsbi2_uart_src",
338 + },
339 + .num_parents = 1,
340 + .ops = &clk_branch_ops,
341 + .flags = CLK_SET_RATE_PARENT,
342 + },
343 + },
344 +};
345 +
346 +static struct clk_rcg gsbi4_uart_src = {
347 + .ns_reg = 0x2a34,
348 + .md_reg = 0x2a30,
349 + .mn = {
350 + .mnctr_en_bit = 8,
351 + .mnctr_reset_bit = 7,
352 + .mnctr_mode_shift = 5,
353 + .n_val_shift = 16,
354 + .m_val_shift = 16,
355 + .width = 16,
356 + },
357 + .p = {
358 + .pre_div_shift = 3,
359 + .pre_div_width = 2,
360 + },
361 + .s = {
362 + .src_sel_shift = 0,
363 + .parent_map = gcc_pxo_pll8_map,
364 + },
365 + .freq_tbl = clk_tbl_gsbi_uart,
366 + .clkr = {
367 + .enable_reg = 0x2a34,
368 + .enable_mask = BIT(11),
369 + .hw.init = &(struct clk_init_data){
370 + .name = "gsbi4_uart_src",
371 + .parent_names = gcc_pxo_pll8,
372 + .num_parents = 2,
373 + .ops = &clk_rcg_ops,
374 + .flags = CLK_SET_PARENT_GATE,
375 + },
376 + },
377 +};
378 +
379 +static struct clk_branch gsbi4_uart_clk = {
380 + .halt_reg = 0x2fd0,
381 + .halt_bit = 26,
382 + .clkr = {
383 + .enable_reg = 0x2a34,
384 + .enable_mask = BIT(9),
385 + .hw.init = &(struct clk_init_data){
386 + .name = "gsbi4_uart_clk",
387 + .parent_names = (const char *[]){
388 + "gsbi4_uart_src",
389 + },
390 + .num_parents = 1,
391 + .ops = &clk_branch_ops,
392 + .flags = CLK_SET_RATE_PARENT,
393 + },
394 + },
395 +};
396 +
397 +static struct clk_rcg gsbi5_uart_src = {
398 + .ns_reg = 0x2a54,
399 + .md_reg = 0x2a50,
400 + .mn = {
401 + .mnctr_en_bit = 8,
402 + .mnctr_reset_bit = 7,
403 + .mnctr_mode_shift = 5,
404 + .n_val_shift = 16,
405 + .m_val_shift = 16,
406 + .width = 16,
407 + },
408 + .p = {
409 + .pre_div_shift = 3,
410 + .pre_div_width = 2,
411 + },
412 + .s = {
413 + .src_sel_shift = 0,
414 + .parent_map = gcc_pxo_pll8_map,
415 + },
416 + .freq_tbl = clk_tbl_gsbi_uart,
417 + .clkr = {
418 + .enable_reg = 0x2a54,
419 + .enable_mask = BIT(11),
420 + .hw.init = &(struct clk_init_data){
421 + .name = "gsbi5_uart_src",
422 + .parent_names = gcc_pxo_pll8,
423 + .num_parents = 2,
424 + .ops = &clk_rcg_ops,
425 + .flags = CLK_SET_PARENT_GATE,
426 + },
427 + },
428 +};
429 +
430 +static struct clk_branch gsbi5_uart_clk = {
431 + .halt_reg = 0x2fd0,
432 + .halt_bit = 22,
433 + .clkr = {
434 + .enable_reg = 0x2a54,
435 + .enable_mask = BIT(9),
436 + .hw.init = &(struct clk_init_data){
437 + .name = "gsbi5_uart_clk",
438 + .parent_names = (const char *[]){
439 + "gsbi5_uart_src",
440 + },
441 + .num_parents = 1,
442 + .ops = &clk_branch_ops,
443 + .flags = CLK_SET_RATE_PARENT,
444 + },
445 + },
446 +};
447 +
448 +static struct clk_rcg gsbi6_uart_src = {
449 + .ns_reg = 0x2a74,
450 + .md_reg = 0x2a70,
451 + .mn = {
452 + .mnctr_en_bit = 8,
453 + .mnctr_reset_bit = 7,
454 + .mnctr_mode_shift = 5,
455 + .n_val_shift = 16,
456 + .m_val_shift = 16,
457 + .width = 16,
458 + },
459 + .p = {
460 + .pre_div_shift = 3,
461 + .pre_div_width = 2,
462 + },
463 + .s = {
464 + .src_sel_shift = 0,
465 + .parent_map = gcc_pxo_pll8_map,
466 + },
467 + .freq_tbl = clk_tbl_gsbi_uart,
468 + .clkr = {
469 + .enable_reg = 0x2a74,
470 + .enable_mask = BIT(11),
471 + .hw.init = &(struct clk_init_data){
472 + .name = "gsbi6_uart_src",
473 + .parent_names = gcc_pxo_pll8,
474 + .num_parents = 2,
475 + .ops = &clk_rcg_ops,
476 + .flags = CLK_SET_PARENT_GATE,
477 + },
478 + },
479 +};
480 +
481 +static struct clk_branch gsbi6_uart_clk = {
482 + .halt_reg = 0x2fd0,
483 + .halt_bit = 18,
484 + .clkr = {
485 + .enable_reg = 0x2a74,
486 + .enable_mask = BIT(9),
487 + .hw.init = &(struct clk_init_data){
488 + .name = "gsbi6_uart_clk",
489 + .parent_names = (const char *[]){
490 + "gsbi6_uart_src",
491 + },
492 + .num_parents = 1,
493 + .ops = &clk_branch_ops,
494 + .flags = CLK_SET_RATE_PARENT,
495 + },
496 + },
497 +};
498 +
499 +static struct clk_rcg gsbi7_uart_src = {
500 + .ns_reg = 0x2a94,
501 + .md_reg = 0x2a90,
502 + .mn = {
503 + .mnctr_en_bit = 8,
504 + .mnctr_reset_bit = 7,
505 + .mnctr_mode_shift = 5,
506 + .n_val_shift = 16,
507 + .m_val_shift = 16,
508 + .width = 16,
509 + },
510 + .p = {
511 + .pre_div_shift = 3,
512 + .pre_div_width = 2,
513 + },
514 + .s = {
515 + .src_sel_shift = 0,
516 + .parent_map = gcc_pxo_pll8_map,
517 + },
518 + .freq_tbl = clk_tbl_gsbi_uart,
519 + .clkr = {
520 + .enable_reg = 0x2a94,
521 + .enable_mask = BIT(11),
522 + .hw.init = &(struct clk_init_data){
523 + .name = "gsbi7_uart_src",
524 + .parent_names = gcc_pxo_pll8,
525 + .num_parents = 2,
526 + .ops = &clk_rcg_ops,
527 + .flags = CLK_SET_PARENT_GATE,
528 + },
529 + },
530 +};
531 +
532 +static struct clk_branch gsbi7_uart_clk = {
533 + .halt_reg = 0x2fd0,
534 + .halt_bit = 14,
535 + .clkr = {
536 + .enable_reg = 0x2a94,
537 + .enable_mask = BIT(9),
538 + .hw.init = &(struct clk_init_data){
539 + .name = "gsbi7_uart_clk",
540 + .parent_names = (const char *[]){
541 + "gsbi7_uart_src",
542 + },
543 + .num_parents = 1,
544 + .ops = &clk_branch_ops,
545 + .flags = CLK_SET_RATE_PARENT,
546 + },
547 + },
548 +};
549 +
550 +static struct freq_tbl clk_tbl_gsbi_qup[] = {
551 + { 1100000, P_PXO, 1, 2, 49 },
552 + { 5400000, P_PXO, 1, 1, 5 },
553 + { 10800000, P_PXO, 1, 2, 5 },
554 + { 15060000, P_PLL8, 1, 2, 51 },
555 + { 24000000, P_PLL8, 4, 1, 4 },
556 + { 25600000, P_PLL8, 1, 1, 15 },
557 + { 27000000, P_PXO, 1, 0, 0 },
558 + { 48000000, P_PLL8, 4, 1, 2 },
559 + { 51200000, P_PLL8, 1, 2, 15 },
560 + { }
561 +};
562 +
563 +static struct clk_rcg gsbi1_qup_src = {
564 + .ns_reg = 0x29cc,
565 + .md_reg = 0x29c8,
566 + .mn = {
567 + .mnctr_en_bit = 8,
568 + .mnctr_reset_bit = 7,
569 + .mnctr_mode_shift = 5,
570 + .n_val_shift = 16,
571 + .m_val_shift = 16,
572 + .width = 8,
573 + },
574 + .p = {
575 + .pre_div_shift = 3,
576 + .pre_div_width = 2,
577 + },
578 + .s = {
579 + .src_sel_shift = 0,
580 + .parent_map = gcc_pxo_pll8_map,
581 + },
582 + .freq_tbl = clk_tbl_gsbi_qup,
583 + .clkr = {
584 + .enable_reg = 0x29cc,
585 + .enable_mask = BIT(11),
586 + .hw.init = &(struct clk_init_data){
587 + .name = "gsbi1_qup_src",
588 + .parent_names = gcc_pxo_pll8,
589 + .num_parents = 2,
590 + .ops = &clk_rcg_ops,
591 + .flags = CLK_SET_PARENT_GATE,
592 + },
593 + },
594 +};
595 +
596 +static struct clk_branch gsbi1_qup_clk = {
597 + .halt_reg = 0x2fcc,
598 + .halt_bit = 11,
599 + .clkr = {
600 + .enable_reg = 0x29cc,
601 + .enable_mask = BIT(9),
602 + .hw.init = &(struct clk_init_data){
603 + .name = "gsbi1_qup_clk",
604 + .parent_names = (const char *[]){ "gsbi1_qup_src" },
605 + .num_parents = 1,
606 + .ops = &clk_branch_ops,
607 + .flags = CLK_SET_RATE_PARENT,
608 + },
609 + },
610 +};
611 +
612 +static struct clk_rcg gsbi2_qup_src = {
613 + .ns_reg = 0x29ec,
614 + .md_reg = 0x29e8,
615 + .mn = {
616 + .mnctr_en_bit = 8,
617 + .mnctr_reset_bit = 7,
618 + .mnctr_mode_shift = 5,
619 + .n_val_shift = 16,
620 + .m_val_shift = 16,
621 + .width = 8,
622 + },
623 + .p = {
624 + .pre_div_shift = 3,
625 + .pre_div_width = 2,
626 + },
627 + .s = {
628 + .src_sel_shift = 0,
629 + .parent_map = gcc_pxo_pll8_map,
630 + },
631 + .freq_tbl = clk_tbl_gsbi_qup,
632 + .clkr = {
633 + .enable_reg = 0x29ec,
634 + .enable_mask = BIT(11),
635 + .hw.init = &(struct clk_init_data){
636 + .name = "gsbi2_qup_src",
637 + .parent_names = gcc_pxo_pll8,
638 + .num_parents = 2,
639 + .ops = &clk_rcg_ops,
640 + .flags = CLK_SET_PARENT_GATE,
641 + },
642 + },
643 +};
644 +
645 +static struct clk_branch gsbi2_qup_clk = {
646 + .halt_reg = 0x2fcc,
647 + .halt_bit = 6,
648 + .clkr = {
649 + .enable_reg = 0x29ec,
650 + .enable_mask = BIT(9),
651 + .hw.init = &(struct clk_init_data){
652 + .name = "gsbi2_qup_clk",
653 + .parent_names = (const char *[]){ "gsbi2_qup_src" },
654 + .num_parents = 1,
655 + .ops = &clk_branch_ops,
656 + .flags = CLK_SET_RATE_PARENT,
657 + },
658 + },
659 +};
660 +
661 +static struct clk_rcg gsbi4_qup_src = {
662 + .ns_reg = 0x2a2c,
663 + .md_reg = 0x2a28,
664 + .mn = {
665 + .mnctr_en_bit = 8,
666 + .mnctr_reset_bit = 7,
667 + .mnctr_mode_shift = 5,
668 + .n_val_shift = 16,
669 + .m_val_shift = 16,
670 + .width = 8,
671 + },
672 + .p = {
673 + .pre_div_shift = 3,
674 + .pre_div_width = 2,
675 + },
676 + .s = {
677 + .src_sel_shift = 0,
678 + .parent_map = gcc_pxo_pll8_map,
679 + },
680 + .freq_tbl = clk_tbl_gsbi_qup,
681 + .clkr = {
682 + .enable_reg = 0x2a2c,
683 + .enable_mask = BIT(11),
684 + .hw.init = &(struct clk_init_data){
685 + .name = "gsbi4_qup_src",
686 + .parent_names = gcc_pxo_pll8,
687 + .num_parents = 2,
688 + .ops = &clk_rcg_ops,
689 + .flags = CLK_SET_PARENT_GATE,
690 + },
691 + },
692 +};
693 +
694 +static struct clk_branch gsbi4_qup_clk = {
695 + .halt_reg = 0x2fd0,
696 + .halt_bit = 24,
697 + .clkr = {
698 + .enable_reg = 0x2a2c,
699 + .enable_mask = BIT(9),
700 + .hw.init = &(struct clk_init_data){
701 + .name = "gsbi4_qup_clk",
702 + .parent_names = (const char *[]){ "gsbi4_qup_src" },
703 + .num_parents = 1,
704 + .ops = &clk_branch_ops,
705 + .flags = CLK_SET_RATE_PARENT,
706 + },
707 + },
708 +};
709 +
710 +static struct clk_rcg gsbi5_qup_src = {
711 + .ns_reg = 0x2a4c,
712 + .md_reg = 0x2a48,
713 + .mn = {
714 + .mnctr_en_bit = 8,
715 + .mnctr_reset_bit = 7,
716 + .mnctr_mode_shift = 5,
717 + .n_val_shift = 16,
718 + .m_val_shift = 16,
719 + .width = 8,
720 + },
721 + .p = {
722 + .pre_div_shift = 3,
723 + .pre_div_width = 2,
724 + },
725 + .s = {
726 + .src_sel_shift = 0,
727 + .parent_map = gcc_pxo_pll8_map,
728 + },
729 + .freq_tbl = clk_tbl_gsbi_qup,
730 + .clkr = {
731 + .enable_reg = 0x2a4c,
732 + .enable_mask = BIT(11),
733 + .hw.init = &(struct clk_init_data){
734 + .name = "gsbi5_qup_src",
735 + .parent_names = gcc_pxo_pll8,
736 + .num_parents = 2,
737 + .ops = &clk_rcg_ops,
738 + .flags = CLK_SET_PARENT_GATE,
739 + },
740 + },
741 +};
742 +
743 +static struct clk_branch gsbi5_qup_clk = {
744 + .halt_reg = 0x2fd0,
745 + .halt_bit = 20,
746 + .clkr = {
747 + .enable_reg = 0x2a4c,
748 + .enable_mask = BIT(9),
749 + .hw.init = &(struct clk_init_data){
750 + .name = "gsbi5_qup_clk",
751 + .parent_names = (const char *[]){ "gsbi5_qup_src" },
752 + .num_parents = 1,
753 + .ops = &clk_branch_ops,
754 + .flags = CLK_SET_RATE_PARENT,
755 + },
756 + },
757 +};
758 +
759 +static struct clk_rcg gsbi6_qup_src = {
760 + .ns_reg = 0x2a6c,
761 + .md_reg = 0x2a68,
762 + .mn = {
763 + .mnctr_en_bit = 8,
764 + .mnctr_reset_bit = 7,
765 + .mnctr_mode_shift = 5,
766 + .n_val_shift = 16,
767 + .m_val_shift = 16,
768 + .width = 8,
769 + },
770 + .p = {
771 + .pre_div_shift = 3,
772 + .pre_div_width = 2,
773 + },
774 + .s = {
775 + .src_sel_shift = 0,
776 + .parent_map = gcc_pxo_pll8_map,
777 + },
778 + .freq_tbl = clk_tbl_gsbi_qup,
779 + .clkr = {
780 + .enable_reg = 0x2a6c,
781 + .enable_mask = BIT(11),
782 + .hw.init = &(struct clk_init_data){
783 + .name = "gsbi6_qup_src",
784 + .parent_names = gcc_pxo_pll8,
785 + .num_parents = 2,
786 + .ops = &clk_rcg_ops,
787 + .flags = CLK_SET_PARENT_GATE,
788 + },
789 + },
790 +};
791 +
792 +static struct clk_branch gsbi6_qup_clk = {
793 + .halt_reg = 0x2fd0,
794 + .halt_bit = 16,
795 + .clkr = {
796 + .enable_reg = 0x2a6c,
797 + .enable_mask = BIT(9),
798 + .hw.init = &(struct clk_init_data){
799 + .name = "gsbi6_qup_clk",
800 + .parent_names = (const char *[]){ "gsbi6_qup_src" },
801 + .num_parents = 1,
802 + .ops = &clk_branch_ops,
803 + .flags = CLK_SET_RATE_PARENT,
804 + },
805 + },
806 +};
807 +
808 +static struct clk_rcg gsbi7_qup_src = {
809 + .ns_reg = 0x2a8c,
810 + .md_reg = 0x2a88,
811 + .mn = {
812 + .mnctr_en_bit = 8,
813 + .mnctr_reset_bit = 7,
814 + .mnctr_mode_shift = 5,
815 + .n_val_shift = 16,
816 + .m_val_shift = 16,
817 + .width = 8,
818 + },
819 + .p = {
820 + .pre_div_shift = 3,
821 + .pre_div_width = 2,
822 + },
823 + .s = {
824 + .src_sel_shift = 0,
825 + .parent_map = gcc_pxo_pll8_map,
826 + },
827 + .freq_tbl = clk_tbl_gsbi_qup,
828 + .clkr = {
829 + .enable_reg = 0x2a8c,
830 + .enable_mask = BIT(11),
831 + .hw.init = &(struct clk_init_data){
832 + .name = "gsbi7_qup_src",
833 + .parent_names = gcc_pxo_pll8,
834 + .num_parents = 2,
835 + .ops = &clk_rcg_ops,
836 + .flags = CLK_SET_PARENT_GATE,
837 + },
838 + },
839 +};
840 +
841 +static struct clk_branch gsbi7_qup_clk = {
842 + .halt_reg = 0x2fd0,
843 + .halt_bit = 12,
844 + .clkr = {
845 + .enable_reg = 0x2a8c,
846 + .enable_mask = BIT(9),
847 + .hw.init = &(struct clk_init_data){
848 + .name = "gsbi7_qup_clk",
849 + .parent_names = (const char *[]){ "gsbi7_qup_src" },
850 + .num_parents = 1,
851 + .ops = &clk_branch_ops,
852 + .flags = CLK_SET_RATE_PARENT,
853 + },
854 + },
855 +};
856 +
857 +static struct clk_branch gsbi1_h_clk = {
858 + .hwcg_reg = 0x29c0,
859 + .hwcg_bit = 6,
860 + .halt_reg = 0x2fcc,
861 + .halt_bit = 13,
862 + .clkr = {
863 + .enable_reg = 0x29c0,
864 + .enable_mask = BIT(4),
865 + .hw.init = &(struct clk_init_data){
866 + .name = "gsbi1_h_clk",
867 + .ops = &clk_branch_ops,
868 + .flags = CLK_IS_ROOT,
869 + },
870 + },
871 +};
872 +
873 +static struct clk_branch gsbi2_h_clk = {
874 + .hwcg_reg = 0x29e0,
875 + .hwcg_bit = 6,
876 + .halt_reg = 0x2fcc,
877 + .halt_bit = 9,
878 + .clkr = {
879 + .enable_reg = 0x29e0,
880 + .enable_mask = BIT(4),
881 + .hw.init = &(struct clk_init_data){
882 + .name = "gsbi2_h_clk",
883 + .ops = &clk_branch_ops,
884 + .flags = CLK_IS_ROOT,
885 + },
886 + },
887 +};
888 +
889 +static struct clk_branch gsbi4_h_clk = {
890 + .hwcg_reg = 0x2a20,
891 + .hwcg_bit = 6,
892 + .halt_reg = 0x2fd0,
893 + .halt_bit = 27,
894 + .clkr = {
895 + .enable_reg = 0x2a20,
896 + .enable_mask = BIT(4),
897 + .hw.init = &(struct clk_init_data){
898 + .name = "gsbi4_h_clk",
899 + .ops = &clk_branch_ops,
900 + .flags = CLK_IS_ROOT,
901 + },
902 + },
903 +};
904 +
905 +static struct clk_branch gsbi5_h_clk = {
906 + .hwcg_reg = 0x2a40,
907 + .hwcg_bit = 6,
908 + .halt_reg = 0x2fd0,
909 + .halt_bit = 23,
910 + .clkr = {
911 + .enable_reg = 0x2a40,
912 + .enable_mask = BIT(4),
913 + .hw.init = &(struct clk_init_data){
914 + .name = "gsbi5_h_clk",
915 + .ops = &clk_branch_ops,
916 + .flags = CLK_IS_ROOT,
917 + },
918 + },
919 +};
920 +
921 +static struct clk_branch gsbi6_h_clk = {
922 + .hwcg_reg = 0x2a60,
923 + .hwcg_bit = 6,
924 + .halt_reg = 0x2fd0,
925 + .halt_bit = 19,
926 + .clkr = {
927 + .enable_reg = 0x2a60,
928 + .enable_mask = BIT(4),
929 + .hw.init = &(struct clk_init_data){
930 + .name = "gsbi6_h_clk",
931 + .ops = &clk_branch_ops,
932 + .flags = CLK_IS_ROOT,
933 + },
934 + },
935 +};
936 +
937 +static struct clk_branch gsbi7_h_clk = {
938 + .hwcg_reg = 0x2a80,
939 + .hwcg_bit = 6,
940 + .halt_reg = 0x2fd0,
941 + .halt_bit = 15,
942 + .clkr = {
943 + .enable_reg = 0x2a80,
944 + .enable_mask = BIT(4),
945 + .hw.init = &(struct clk_init_data){
946 + .name = "gsbi7_h_clk",
947 + .ops = &clk_branch_ops,
948 + .flags = CLK_IS_ROOT,
949 + },
950 + },
951 +};
952 +
953 +static const struct freq_tbl clk_tbl_gp[] = {
954 + { 12500000, P_PXO, 2, 0, 0 },
955 + { 25000000, P_PXO, 1, 0, 0 },
956 + { 64000000, P_PLL8, 2, 1, 3 },
957 + { 76800000, P_PLL8, 1, 1, 5 },
958 + { 96000000, P_PLL8, 4, 0, 0 },
959 + { 128000000, P_PLL8, 3, 0, 0 },
960 + { 192000000, P_PLL8, 2, 0, 0 },
961 + { }
962 +};
963 +
964 +static struct clk_rcg gp0_src = {
965 + .ns_reg = 0x2d24,
966 + .md_reg = 0x2d00,
967 + .mn = {
968 + .mnctr_en_bit = 8,
969 + .mnctr_reset_bit = 7,
970 + .mnctr_mode_shift = 5,
971 + .n_val_shift = 16,
972 + .m_val_shift = 16,
973 + .width = 8,
974 + },
975 + .p = {
976 + .pre_div_shift = 3,
977 + .pre_div_width = 2,
978 + },
979 + .s = {
980 + .src_sel_shift = 0,
981 + .parent_map = gcc_pxo_pll8_cxo_map,
982 + },
983 + .freq_tbl = clk_tbl_gp,
984 + .clkr = {
985 + .enable_reg = 0x2d24,
986 + .enable_mask = BIT(11),
987 + .hw.init = &(struct clk_init_data){
988 + .name = "gp0_src",
989 + .parent_names = gcc_pxo_pll8_cxo,
990 + .num_parents = 3,
991 + .ops = &clk_rcg_ops,
992 + .flags = CLK_SET_PARENT_GATE,
993 + },
994 + }
995 +};
996 +
997 +static struct clk_branch gp0_clk = {
998 + .halt_reg = 0x2fd8,
999 + .halt_bit = 7,
1000 + .clkr = {
1001 + .enable_reg = 0x2d24,
1002 + .enable_mask = BIT(9),
1003 + .hw.init = &(struct clk_init_data){
1004 + .name = "gp0_clk",
1005 + .parent_names = (const char *[]){ "gp0_src" },
1006 + .num_parents = 1,
1007 + .ops = &clk_branch_ops,
1008 + .flags = CLK_SET_RATE_PARENT,
1009 + },
1010 + },
1011 +};
1012 +
1013 +static struct clk_rcg gp1_src = {
1014 + .ns_reg = 0x2d44,
1015 + .md_reg = 0x2d40,
1016 + .mn = {
1017 + .mnctr_en_bit = 8,
1018 + .mnctr_reset_bit = 7,
1019 + .mnctr_mode_shift = 5,
1020 + .n_val_shift = 16,
1021 + .m_val_shift = 16,
1022 + .width = 8,
1023 + },
1024 + .p = {
1025 + .pre_div_shift = 3,
1026 + .pre_div_width = 2,
1027 + },
1028 + .s = {
1029 + .src_sel_shift = 0,
1030 + .parent_map = gcc_pxo_pll8_cxo_map,
1031 + },
1032 + .freq_tbl = clk_tbl_gp,
1033 + .clkr = {
1034 + .enable_reg = 0x2d44,
1035 + .enable_mask = BIT(11),
1036 + .hw.init = &(struct clk_init_data){
1037 + .name = "gp1_src",
1038 + .parent_names = gcc_pxo_pll8_cxo,
1039 + .num_parents = 3,
1040 + .ops = &clk_rcg_ops,
1041 + .flags = CLK_SET_RATE_GATE,
1042 + },
1043 + }
1044 +};
1045 +
1046 +static struct clk_branch gp1_clk = {
1047 + .halt_reg = 0x2fd8,
1048 + .halt_bit = 6,
1049 + .clkr = {
1050 + .enable_reg = 0x2d44,
1051 + .enable_mask = BIT(9),
1052 + .hw.init = &(struct clk_init_data){
1053 + .name = "gp1_clk",
1054 + .parent_names = (const char *[]){ "gp1_src" },
1055 + .num_parents = 1,
1056 + .ops = &clk_branch_ops,
1057 + .flags = CLK_SET_RATE_PARENT,
1058 + },
1059 + },
1060 +};
1061 +
1062 +static struct clk_rcg gp2_src = {
1063 + .ns_reg = 0x2d64,
1064 + .md_reg = 0x2d60,
1065 + .mn = {
1066 + .mnctr_en_bit = 8,
1067 + .mnctr_reset_bit = 7,
1068 + .mnctr_mode_shift = 5,
1069 + .n_val_shift = 16,
1070 + .m_val_shift = 16,
1071 + .width = 8,
1072 + },
1073 + .p = {
1074 + .pre_div_shift = 3,
1075 + .pre_div_width = 2,
1076 + },
1077 + .s = {
1078 + .src_sel_shift = 0,
1079 + .parent_map = gcc_pxo_pll8_cxo_map,
1080 + },
1081 + .freq_tbl = clk_tbl_gp,
1082 + .clkr = {
1083 + .enable_reg = 0x2d64,
1084 + .enable_mask = BIT(11),
1085 + .hw.init = &(struct clk_init_data){
1086 + .name = "gp2_src",
1087 + .parent_names = gcc_pxo_pll8_cxo,
1088 + .num_parents = 3,
1089 + .ops = &clk_rcg_ops,
1090 + .flags = CLK_SET_RATE_GATE,
1091 + },
1092 + }
1093 +};
1094 +
1095 +static struct clk_branch gp2_clk = {
1096 + .halt_reg = 0x2fd8,
1097 + .halt_bit = 5,
1098 + .clkr = {
1099 + .enable_reg = 0x2d64,
1100 + .enable_mask = BIT(9),
1101 + .hw.init = &(struct clk_init_data){
1102 + .name = "gp2_clk",
1103 + .parent_names = (const char *[]){ "gp2_src" },
1104 + .num_parents = 1,
1105 + .ops = &clk_branch_ops,
1106 + .flags = CLK_SET_RATE_PARENT,
1107 + },
1108 + },
1109 +};
1110 +
1111 +static struct clk_branch pmem_clk = {
1112 + .hwcg_reg = 0x25a0,
1113 + .hwcg_bit = 6,
1114 + .halt_reg = 0x2fc8,
1115 + .halt_bit = 20,
1116 + .clkr = {
1117 + .enable_reg = 0x25a0,
1118 + .enable_mask = BIT(4),
1119 + .hw.init = &(struct clk_init_data){
1120 + .name = "pmem_clk",
1121 + .ops = &clk_branch_ops,
1122 + .flags = CLK_IS_ROOT,
1123 + },
1124 + },
1125 +};
1126 +
1127 +static struct clk_rcg prng_src = {
1128 + .ns_reg = 0x2e80,
1129 + .p = {
1130 + .pre_div_shift = 3,
1131 + .pre_div_width = 4,
1132 + },
1133 + .s = {
1134 + .src_sel_shift = 0,
1135 + .parent_map = gcc_pxo_pll8_map,
1136 + },
1137 + .clkr = {
1138 + .hw.init = &(struct clk_init_data){
1139 + .name = "prng_src",
1140 + .parent_names = gcc_pxo_pll8,
1141 + .num_parents = 2,
1142 + .ops = &clk_rcg_ops,
1143 + },
1144 + },
1145 +};
1146 +
1147 +static struct clk_branch prng_clk = {
1148 + .halt_reg = 0x2fd8,
1149 + .halt_check = BRANCH_HALT_VOTED,
1150 + .halt_bit = 10,
1151 + .clkr = {
1152 + .enable_reg = 0x3080,
1153 + .enable_mask = BIT(10),
1154 + .hw.init = &(struct clk_init_data){
1155 + .name = "prng_clk",
1156 + .parent_names = (const char *[]){ "prng_src" },
1157 + .num_parents = 1,
1158 + .ops = &clk_branch_ops,
1159 + },
1160 + },
1161 +};
1162 +
1163 +static const struct freq_tbl clk_tbl_sdc[] = {
1164 + { 144000, P_PXO, 5, 18,625 },
1165 + { 400000, P_PLL8, 4, 1, 240 },
1166 + { 16000000, P_PLL8, 4, 1, 6 },
1167 + { 17070000, P_PLL8, 1, 2, 45 },
1168 + { 20210000, P_PLL8, 1, 1, 19 },
1169 + { 24000000, P_PLL8, 4, 1, 4 },
1170 + { 48000000, P_PLL8, 4, 1, 2 },
1171 + { 64000000, P_PLL8, 3, 1, 2 },
1172 + { 96000000, P_PLL8, 4, 0, 0 },
1173 + { 192000000, P_PLL8, 2, 0, 0 },
1174 + { }
1175 +};
1176 +
1177 +static struct clk_rcg sdc1_src = {
1178 + .ns_reg = 0x282c,
1179 + .md_reg = 0x2828,
1180 + .mn = {
1181 + .mnctr_en_bit = 8,
1182 + .mnctr_reset_bit = 7,
1183 + .mnctr_mode_shift = 5,
1184 + .n_val_shift = 16,
1185 + .m_val_shift = 16,
1186 + .width = 8,
1187 + },
1188 + .p = {
1189 + .pre_div_shift = 3,
1190 + .pre_div_width = 2,
1191 + },
1192 + .s = {
1193 + .src_sel_shift = 0,
1194 + .parent_map = gcc_pxo_pll8_map,
1195 + },
1196 + .freq_tbl = clk_tbl_sdc,
1197 + .clkr = {
1198 + .enable_reg = 0x282c,
1199 + .enable_mask = BIT(11),
1200 + .hw.init = &(struct clk_init_data){
1201 + .name = "sdc1_src",
1202 + .parent_names = gcc_pxo_pll8,
1203 + .num_parents = 2,
1204 + .ops = &clk_rcg_ops,
1205 + .flags = CLK_SET_RATE_GATE,
1206 + },
1207 + }
1208 +};
1209 +
1210 +static struct clk_branch sdc1_clk = {
1211 + .halt_reg = 0x2fc8,
1212 + .halt_bit = 6,
1213 + .clkr = {
1214 + .enable_reg = 0x282c,
1215 + .enable_mask = BIT(9),
1216 + .hw.init = &(struct clk_init_data){
1217 + .name = "sdc1_clk",
1218 + .parent_names = (const char *[]){ "sdc1_src" },
1219 + .num_parents = 1,
1220 + .ops = &clk_branch_ops,
1221 + .flags = CLK_SET_RATE_PARENT,
1222 + },
1223 + },
1224 +};
1225 +
1226 +static struct clk_rcg sdc3_src = {
1227 + .ns_reg = 0x286c,
1228 + .md_reg = 0x2868,
1229 + .mn = {
1230 + .mnctr_en_bit = 8,
1231 + .mnctr_reset_bit = 7,
1232 + .mnctr_mode_shift = 5,
1233 + .n_val_shift = 16,
1234 + .m_val_shift = 16,
1235 + .width = 8,
1236 + },
1237 + .p = {
1238 + .pre_div_shift = 3,
1239 + .pre_div_width = 2,
1240 + },
1241 + .s = {
1242 + .src_sel_shift = 0,
1243 + .parent_map = gcc_pxo_pll8_map,
1244 + },
1245 + .freq_tbl = clk_tbl_sdc,
1246 + .clkr = {
1247 + .enable_reg = 0x286c,
1248 + .enable_mask = BIT(11),
1249 + .hw.init = &(struct clk_init_data){
1250 + .name = "sdc3_src",
1251 + .parent_names = gcc_pxo_pll8,
1252 + .num_parents = 2,
1253 + .ops = &clk_rcg_ops,
1254 + .flags = CLK_SET_RATE_GATE,
1255 + },
1256 + }
1257 +};
1258 +
1259 +static struct clk_branch sdc3_clk = {
1260 + .halt_reg = 0x2fc8,
1261 + .halt_bit = 4,
1262 + .clkr = {
1263 + .enable_reg = 0x286c,
1264 + .enable_mask = BIT(9),
1265 + .hw.init = &(struct clk_init_data){
1266 + .name = "sdc3_clk",
1267 + .parent_names = (const char *[]){ "sdc3_src" },
1268 + .num_parents = 1,
1269 + .ops = &clk_branch_ops,
1270 + .flags = CLK_SET_RATE_PARENT,
1271 + },
1272 + },
1273 +};
1274 +
1275 +static struct clk_branch sdc1_h_clk = {
1276 + .hwcg_reg = 0x2820,
1277 + .hwcg_bit = 6,
1278 + .halt_reg = 0x2fc8,
1279 + .halt_bit = 11,
1280 + .clkr = {
1281 + .enable_reg = 0x2820,
1282 + .enable_mask = BIT(4),
1283 + .hw.init = &(struct clk_init_data){
1284 + .name = "sdc1_h_clk",
1285 + .ops = &clk_branch_ops,
1286 + .flags = CLK_IS_ROOT,
1287 + },
1288 + },
1289 +};
1290 +
1291 +static struct clk_branch sdc3_h_clk = {
1292 + .hwcg_reg = 0x2860,
1293 + .hwcg_bit = 6,
1294 + .halt_reg = 0x2fc8,
1295 + .halt_bit = 9,
1296 + .clkr = {
1297 + .enable_reg = 0x2860,
1298 + .enable_mask = BIT(4),
1299 + .hw.init = &(struct clk_init_data){
1300 + .name = "sdc3_h_clk",
1301 + .ops = &clk_branch_ops,
1302 + .flags = CLK_IS_ROOT,
1303 + },
1304 + },
1305 +};
1306 +
1307 +static const struct freq_tbl clk_tbl_tsif_ref[] = {
1308 + { 105000, P_PXO, 1, 1, 256 },
1309 + { }
1310 +};
1311 +
1312 +static struct clk_rcg tsif_ref_src = {
1313 + .ns_reg = 0x2710,
1314 + .md_reg = 0x270c,
1315 + .mn = {
1316 + .mnctr_en_bit = 8,
1317 + .mnctr_reset_bit = 7,
1318 + .mnctr_mode_shift = 5,
1319 + .n_val_shift = 16,
1320 + .m_val_shift = 16,
1321 + .width = 16,
1322 + },
1323 + .p = {
1324 + .pre_div_shift = 3,
1325 + .pre_div_width = 2,
1326 + },
1327 + .s = {
1328 + .src_sel_shift = 0,
1329 + .parent_map = gcc_pxo_pll8_map,
1330 + },
1331 + .freq_tbl = clk_tbl_tsif_ref,
1332 + .clkr = {
1333 + .enable_reg = 0x2710,
1334 + .enable_mask = BIT(11),
1335 + .hw.init = &(struct clk_init_data){
1336 + .name = "tsif_ref_src",
1337 + .parent_names = gcc_pxo_pll8,
1338 + .num_parents = 2,
1339 + .ops = &clk_rcg_ops,
1340 + .flags = CLK_SET_RATE_GATE,
1341 + },
1342 + }
1343 +};
1344 +
1345 +static struct clk_branch tsif_ref_clk = {
1346 + .halt_reg = 0x2fd4,
1347 + .halt_bit = 5,
1348 + .clkr = {
1349 + .enable_reg = 0x2710,
1350 + .enable_mask = BIT(9),
1351 + .hw.init = &(struct clk_init_data){
1352 + .name = "tsif_ref_clk",
1353 + .parent_names = (const char *[]){ "tsif_ref_src" },
1354 + .num_parents = 1,
1355 + .ops = &clk_branch_ops,
1356 + .flags = CLK_SET_RATE_PARENT,
1357 + },
1358 + },
1359 +};
1360 +
1361 +static struct clk_branch tsif_h_clk = {
1362 + .hwcg_reg = 0x2700,
1363 + .hwcg_bit = 6,
1364 + .halt_reg = 0x2fd4,
1365 + .halt_bit = 7,
1366 + .clkr = {
1367 + .enable_reg = 0x2700,
1368 + .enable_mask = BIT(4),
1369 + .hw.init = &(struct clk_init_data){
1370 + .name = "tsif_h_clk",
1371 + .ops = &clk_branch_ops,
1372 + .flags = CLK_IS_ROOT,
1373 + },
1374 + },
1375 +};
1376 +
1377 +static struct clk_branch dma_bam_h_clk = {
1378 + .hwcg_reg = 0x25c0,
1379 + .hwcg_bit = 6,
1380 + .halt_reg = 0x2fc8,
1381 + .halt_bit = 12,
1382 + .clkr = {
1383 + .enable_reg = 0x25c0,
1384 + .enable_mask = BIT(4),
1385 + .hw.init = &(struct clk_init_data){
1386 + .name = "dma_bam_h_clk",
1387 + .ops = &clk_branch_ops,
1388 + .flags = CLK_IS_ROOT,
1389 + },
1390 + },
1391 +};
1392 +
1393 +static struct clk_branch adm0_clk = {
1394 + .halt_reg = 0x2fdc,
1395 + .halt_check = BRANCH_HALT_VOTED,
1396 + .halt_bit = 12,
1397 + .clkr = {
1398 + .enable_reg = 0x3080,
1399 + .enable_mask = BIT(2),
1400 + .hw.init = &(struct clk_init_data){
1401 + .name = "adm0_clk",
1402 + .ops = &clk_branch_ops,
1403 + .flags = CLK_IS_ROOT,
1404 + },
1405 + },
1406 +};
1407 +
1408 +static struct clk_branch adm0_pbus_clk = {
1409 + .hwcg_reg = 0x2208,
1410 + .hwcg_bit = 6,
1411 + .halt_reg = 0x2fdc,
1412 + .halt_check = BRANCH_HALT_VOTED,
1413 + .halt_bit = 11,
1414 + .clkr = {
1415 + .enable_reg = 0x3080,
1416 + .enable_mask = BIT(3),
1417 + .hw.init = &(struct clk_init_data){
1418 + .name = "adm0_pbus_clk",
1419 + .ops = &clk_branch_ops,
1420 + .flags = CLK_IS_ROOT,
1421 + },
1422 + },
1423 +};
1424 +
1425 +static struct clk_branch pmic_arb0_h_clk = {
1426 + .halt_reg = 0x2fd8,
1427 + .halt_check = BRANCH_HALT_VOTED,
1428 + .halt_bit = 22,
1429 + .clkr = {
1430 + .enable_reg = 0x3080,
1431 + .enable_mask = BIT(8),
1432 + .hw.init = &(struct clk_init_data){
1433 + .name = "pmic_arb0_h_clk",
1434 + .ops = &clk_branch_ops,
1435 + .flags = CLK_IS_ROOT,
1436 + },
1437 + },
1438 +};
1439 +
1440 +static struct clk_branch pmic_arb1_h_clk = {
1441 + .halt_reg = 0x2fd8,
1442 + .halt_check = BRANCH_HALT_VOTED,
1443 + .halt_bit = 21,
1444 + .clkr = {
1445 + .enable_reg = 0x3080,
1446 + .enable_mask = BIT(9),
1447 + .hw.init = &(struct clk_init_data){
1448 + .name = "pmic_arb1_h_clk",
1449 + .ops = &clk_branch_ops,
1450 + .flags = CLK_IS_ROOT,
1451 + },
1452 + },
1453 +};
1454 +
1455 +static struct clk_branch pmic_ssbi2_clk = {
1456 + .halt_reg = 0x2fd8,
1457 + .halt_check = BRANCH_HALT_VOTED,
1458 + .halt_bit = 23,
1459 + .clkr = {
1460 + .enable_reg = 0x3080,
1461 + .enable_mask = BIT(7),
1462 + .hw.init = &(struct clk_init_data){
1463 + .name = "pmic_ssbi2_clk",
1464 + .ops = &clk_branch_ops,
1465 + .flags = CLK_IS_ROOT,
1466 + },
1467 + },
1468 +};
1469 +
1470 +static struct clk_branch rpm_msg_ram_h_clk = {
1471 + .hwcg_reg = 0x27e0,
1472 + .hwcg_bit = 6,
1473 + .halt_reg = 0x2fd8,
1474 + .halt_check = BRANCH_HALT_VOTED,
1475 + .halt_bit = 12,
1476 + .clkr = {
1477 + .enable_reg = 0x3080,
1478 + .enable_mask = BIT(6),
1479 + .hw.init = &(struct clk_init_data){
1480 + .name = "rpm_msg_ram_h_clk",
1481 + .ops = &clk_branch_ops,
1482 + .flags = CLK_IS_ROOT,
1483 + },
1484 + },
1485 +};
1486 +
1487 +static const struct freq_tbl clk_tbl_pcie_ref[] = {
1488 + { 100000000, P_PLL3, 12, 0, 0 },
1489 + { }
1490 +};
1491 +
1492 +static struct clk_rcg pcie_ref_src = {
1493 + .ns_reg = 0x3860,
1494 + .p = {
1495 + .pre_div_shift = 3,
1496 + .pre_div_width = 4,
1497 + },
1498 + .s = {
1499 + .src_sel_shift = 0,
1500 + .parent_map = gcc_pxo_pll3_map,
1501 + },
1502 + .freq_tbl = clk_tbl_pcie_ref,
1503 + .clkr = {
1504 + .enable_reg = 0x3860,
1505 + .enable_mask = BIT(11),
1506 + .hw.init = &(struct clk_init_data){
1507 + .name = "pcie_ref_src",
1508 + .parent_names = gcc_pxo_pll3,
1509 + .num_parents = 2,
1510 + .ops = &clk_rcg_ops,
1511 + .flags = CLK_SET_RATE_GATE,
1512 + },
1513 + },
1514 +};
1515 +
1516 +static struct clk_branch pcie_ref_src_clk = {
1517 + .halt_reg = 0x2fdc,
1518 + .halt_bit = 30,
1519 + .clkr = {
1520 + .enable_reg = 0x3860,
1521 + .enable_mask = BIT(9),
1522 + .hw.init = &(struct clk_init_data){
1523 + .name = "pcie_ref_src_clk",
1524 + .parent_names = (const char *[]){ "pcie_ref_src" },
1525 + .num_parents = 1,
1526 + .ops = &clk_branch_ops,
1527 + .flags = CLK_SET_RATE_PARENT,
1528 + },
1529 + },
1530 +};
1531 +
1532 +static struct clk_branch pcie_a_clk = {
1533 + .halt_reg = 0x2fc0,
1534 + .halt_bit = 13,
1535 + .clkr = {
1536 + .enable_reg = 0x22c0,
1537 + .enable_mask = BIT(4),
1538 + .hw.init = &(struct clk_init_data){
1539 + .name = "pcie_a_clk",
1540 + .ops = &clk_branch_ops,
1541 + .flags = CLK_IS_ROOT,
1542 + },
1543 + },
1544 +};
1545 +
1546 +static struct clk_branch pcie_aux_clk = {
1547 + .halt_reg = 0x2fdc,
1548 + .halt_bit = 31,
1549 + .clkr = {
1550 + .enable_reg = 0x22c8,
1551 + .enable_mask = BIT(4),
1552 + .hw.init = &(struct clk_init_data){
1553 + .name = "pcie_aux_clk",
1554 + .ops = &clk_branch_ops,
1555 + .flags = CLK_IS_ROOT,
1556 + },
1557 + },
1558 +};
1559 +
1560 +static struct clk_branch pcie_h_clk = {
1561 + .halt_reg = 0x2fd4,
1562 + .halt_bit = 8,
1563 + .clkr = {
1564 + .enable_reg = 0x22cc,
1565 + .enable_mask = BIT(4),
1566 + .hw.init = &(struct clk_init_data){
1567 + .name = "pcie_h_clk",
1568 + .ops = &clk_branch_ops,
1569 + .flags = CLK_IS_ROOT,
1570 + },
1571 + },
1572 +};
1573 +
1574 +static struct clk_branch pcie_phy_clk = {
1575 + .halt_reg = 0x2fdc,
1576 + .halt_bit = 29,
1577 + .clkr = {
1578 + .enable_reg = 0x22d0,
1579 + .enable_mask = BIT(4),
1580 + .hw.init = &(struct clk_init_data){
1581 + .name = "pcie_phy_clk",
1582 + .ops = &clk_branch_ops,
1583 + .flags = CLK_IS_ROOT,
1584 + },
1585 + },
1586 +};
1587 +
1588 +static struct clk_rcg pcie1_ref_src = {
1589 + .ns_reg = 0x3aa0,
1590 + .p = {
1591 + .pre_div_shift = 3,
1592 + .pre_div_width = 4,
1593 + },
1594 + .s = {
1595 + .src_sel_shift = 0,
1596 + .parent_map = gcc_pxo_pll3_map,
1597 + },
1598 + .freq_tbl = clk_tbl_pcie_ref,
1599 + .clkr = {
1600 + .enable_reg = 0x3aa0,
1601 + .enable_mask = BIT(11),
1602 + .hw.init = &(struct clk_init_data){
1603 + .name = "pcie1_ref_src",
1604 + .parent_names = gcc_pxo_pll3,
1605 + .num_parents = 2,
1606 + .ops = &clk_rcg_ops,
1607 + .flags = CLK_SET_RATE_GATE,
1608 + },
1609 + },
1610 +};
1611 +
1612 +static struct clk_branch pcie1_ref_src_clk = {
1613 + .halt_reg = 0x2fdc,
1614 + .halt_bit = 27,
1615 + .clkr = {
1616 + .enable_reg = 0x3aa0,
1617 + .enable_mask = BIT(9),
1618 + .hw.init = &(struct clk_init_data){
1619 + .name = "pcie1_ref_src_clk",
1620 + .parent_names = (const char *[]){ "pcie1_ref_src" },
1621 + .num_parents = 1,
1622 + .ops = &clk_branch_ops,
1623 + .flags = CLK_SET_RATE_PARENT,
1624 + },
1625 + },
1626 +};
1627 +
1628 +static struct clk_branch pcie1_a_clk = {
1629 + .halt_reg = 0x2fc0,
1630 + .halt_bit = 10,
1631 + .clkr = {
1632 + .enable_reg = 0x3a80,
1633 + .enable_mask = BIT(4),
1634 + .hw.init = &(struct clk_init_data){
1635 + .name = "pcie1_a_clk",
1636 + .ops = &clk_branch_ops,
1637 + .flags = CLK_IS_ROOT,
1638 + },
1639 + },
1640 +};
1641 +
1642 +static struct clk_branch pcie1_aux_clk = {
1643 + .halt_reg = 0x2fdc,
1644 + .halt_bit = 28,
1645 + .clkr = {
1646 + .enable_reg = 0x3a88,
1647 + .enable_mask = BIT(4),
1648 + .hw.init = &(struct clk_init_data){
1649 + .name = "pcie1_aux_clk",
1650 + .ops = &clk_branch_ops,
1651 + .flags = CLK_IS_ROOT,
1652 + },
1653 + },
1654 +};
1655 +
1656 +static struct clk_branch pcie1_h_clk = {
1657 + .halt_reg = 0x2fd4,
1658 + .halt_bit = 9,
1659 + .clkr = {
1660 + .enable_reg = 0x3a8c,
1661 + .enable_mask = BIT(4),
1662 + .hw.init = &(struct clk_init_data){
1663 + .name = "pcie1_h_clk",
1664 + .ops = &clk_branch_ops,
1665 + .flags = CLK_IS_ROOT,
1666 + },
1667 + },
1668 +};
1669 +
1670 +static struct clk_branch pcie1_phy_clk = {
1671 + .halt_reg = 0x2fdc,
1672 + .halt_bit = 26,
1673 + .clkr = {
1674 + .enable_reg = 0x3a90,
1675 + .enable_mask = BIT(4),
1676 + .hw.init = &(struct clk_init_data){
1677 + .name = "pcie1_phy_clk",
1678 + .ops = &clk_branch_ops,
1679 + .flags = CLK_IS_ROOT,
1680 + },
1681 + },
1682 +};
1683 +
1684 +static struct clk_rcg pcie2_ref_src = {
1685 + .ns_reg = 0x3ae0,
1686 + .p = {
1687 + .pre_div_shift = 3,
1688 + .pre_div_width = 4,
1689 + },
1690 + .s = {
1691 + .src_sel_shift = 0,
1692 + .parent_map = gcc_pxo_pll3_map,
1693 + },
1694 + .freq_tbl = clk_tbl_pcie_ref,
1695 + .clkr = {
1696 + .enable_reg = 0x3ae0,
1697 + .enable_mask = BIT(11),
1698 + .hw.init = &(struct clk_init_data){
1699 + .name = "pcie2_ref_src",
1700 + .parent_names = gcc_pxo_pll3,
1701 + .num_parents = 2,
1702 + .ops = &clk_rcg_ops,
1703 + .flags = CLK_SET_RATE_GATE,
1704 + },
1705 + },
1706 +};
1707 +
1708 +static struct clk_branch pcie2_ref_src_clk = {
1709 + .halt_reg = 0x2fdc,
1710 + .halt_bit = 24,
1711 + .clkr = {
1712 + .enable_reg = 0x3ae0,
1713 + .enable_mask = BIT(9),
1714 + .hw.init = &(struct clk_init_data){
1715 + .name = "pcie2_ref_src_clk",
1716 + .parent_names = (const char *[]){ "pcie2_ref_src" },
1717 + .num_parents = 1,
1718 + .ops = &clk_branch_ops,
1719 + .flags = CLK_SET_RATE_PARENT,
1720 + },
1721 + },
1722 +};
1723 +
1724 +static struct clk_branch pcie2_a_clk = {
1725 + .halt_reg = 0x2fc0,
1726 + .halt_bit = 9,
1727 + .clkr = {
1728 + .enable_reg = 0x3ac0,
1729 + .enable_mask = BIT(4),
1730 + .hw.init = &(struct clk_init_data){
1731 + .name = "pcie2_a_clk",
1732 + .ops = &clk_branch_ops,
1733 + .flags = CLK_IS_ROOT,
1734 + },
1735 + },
1736 +};
1737 +
1738 +static struct clk_branch pcie2_aux_clk = {
1739 + .halt_reg = 0x2fdc,
1740 + .halt_bit = 25,
1741 + .clkr = {
1742 + .enable_reg = 0x3ac8,
1743 + .enable_mask = BIT(4),
1744 + .hw.init = &(struct clk_init_data){
1745 + .name = "pcie2_aux_clk",
1746 + .ops = &clk_branch_ops,
1747 + .flags = CLK_IS_ROOT,
1748 + },
1749 + },
1750 +};
1751 +
1752 +static struct clk_branch pcie2_h_clk = {
1753 + .halt_reg = 0x2fd4,
1754 + .halt_bit = 10,
1755 + .clkr = {
1756 + .enable_reg = 0x3acc,
1757 + .enable_mask = BIT(4),
1758 + .hw.init = &(struct clk_init_data){
1759 + .name = "pcie2_h_clk",
1760 + .ops = &clk_branch_ops,
1761 + .flags = CLK_IS_ROOT,
1762 + },
1763 + },
1764 +};
1765 +
1766 +static struct clk_branch pcie2_phy_clk = {
1767 + .halt_reg = 0x2fdc,
1768 + .halt_bit = 23,
1769 + .clkr = {
1770 + .enable_reg = 0x3ad0,
1771 + .enable_mask = BIT(4),
1772 + .hw.init = &(struct clk_init_data){
1773 + .name = "pcie2_phy_clk",
1774 + .ops = &clk_branch_ops,
1775 + .flags = CLK_IS_ROOT,
1776 + },
1777 + },
1778 +};
1779 +
1780 +static const struct freq_tbl clk_tbl_sata_ref[] = {
1781 + { 100000000, P_PLL3, 12, 0, 0 },
1782 + { }
1783 +};
1784 +
1785 +static struct clk_rcg sata_ref_src = {
1786 + .ns_reg = 0x2c08,
1787 + .p = {
1788 + .pre_div_shift = 3,
1789 + .pre_div_width = 4,
1790 + },
1791 + .s = {
1792 + .src_sel_shift = 0,
1793 + .parent_map = gcc_pxo_pll3_sata_map,
1794 + },
1795 + .freq_tbl = clk_tbl_sata_ref,
1796 + .clkr = {
1797 + .enable_reg = 0x2c08,
1798 + .enable_mask = BIT(7),
1799 + .hw.init = &(struct clk_init_data){
1800 + .name = "sata_ref_src",
1801 + .parent_names = gcc_pxo_pll3,
1802 + .num_parents = 2,
1803 + .ops = &clk_rcg_ops,
1804 + .flags = CLK_SET_RATE_GATE,
1805 + },
1806 + },
1807 +};
1808 +
1809 +static struct clk_branch sata_rxoob_clk = {
1810 + .halt_reg = 0x2fdc,
1811 + .halt_bit = 20,
1812 + .clkr = {
1813 + .enable_reg = 0x2c0c,
1814 + .enable_mask = BIT(4),
1815 + .hw.init = &(struct clk_init_data){
1816 + .name = "sata_rxoob_clk",
1817 + .parent_names = (const char *[]){ "sata_ref_src" },
1818 + .num_parents = 1,
1819 + .ops = &clk_branch_ops,
1820 + .flags = CLK_SET_RATE_PARENT,
1821 + },
1822 + },
1823 +};
1824 +
1825 +static struct clk_branch sata_pmalive_clk = {
1826 + .halt_reg = 0x2fdc,
1827 + .halt_bit = 19,
1828 + .clkr = {
1829 + .enable_reg = 0x2c10,
1830 + .enable_mask = BIT(4),
1831 + .hw.init = &(struct clk_init_data){
1832 + .name = "sata_pmalive_clk",
1833 + .parent_names = (const char *[]){ "sata_ref_src" },
1834 + .num_parents = 1,
1835 + .ops = &clk_branch_ops,
1836 + .flags = CLK_SET_RATE_PARENT,
1837 + },
1838 + },
1839 +};
1840 +
1841 +static struct clk_branch sata_phy_ref_clk = {
1842 + .halt_reg = 0x2fdc,
1843 + .halt_bit = 18,
1844 + .clkr = {
1845 + .enable_reg = 0x2c14,
1846 + .enable_mask = BIT(4),
1847 + .hw.init = &(struct clk_init_data){
1848 + .name = "sata_phy_ref_clk",
1849 + .parent_names = (const char *[]){ "pxo" },
1850 + .num_parents = 1,
1851 + .ops = &clk_branch_ops,
1852 + },
1853 + },
1854 +};
1855 +
1856 +static struct clk_branch sata_a_clk = {
1857 + .halt_reg = 0x2fc0,
1858 + .halt_bit = 12,
1859 + .clkr = {
1860 + .enable_reg = 0x2c20,
1861 + .enable_mask = BIT(4),
1862 + .hw.init = &(struct clk_init_data){
1863 + .name = "sata_a_clk",
1864 + .ops = &clk_branch_ops,
1865 + .flags = CLK_IS_ROOT,
1866 + },
1867 + },
1868 +};
1869 +
1870 +static struct clk_branch sata_h_clk = {
1871 + .halt_reg = 0x2fdc,
1872 + .halt_bit = 21,
1873 + .clkr = {
1874 + .enable_reg = 0x2c00,
1875 + .enable_mask = BIT(4),
1876 + .hw.init = &(struct clk_init_data){
1877 + .name = "sata_h_clk",
1878 + .ops = &clk_branch_ops,
1879 + .flags = CLK_IS_ROOT,
1880 + },
1881 + },
1882 +};
1883 +
1884 +static struct clk_branch sfab_sata_s_h_clk = {
1885 + .halt_reg = 0x2fc4,
1886 + .halt_bit = 14,
1887 + .clkr = {
1888 + .enable_reg = 0x2480,
1889 + .enable_mask = BIT(4),
1890 + .hw.init = &(struct clk_init_data){
1891 + .name = "sfab_sata_s_h_clk",
1892 + .ops = &clk_branch_ops,
1893 + .flags = CLK_IS_ROOT,
1894 + },
1895 + },
1896 +};
1897 +
1898 +static struct clk_branch sata_phy_cfg_clk = {
1899 + .halt_reg = 0x2fcc,
1900 + .halt_bit = 14,
1901 + .clkr = {
1902 + .enable_reg = 0x2c40,
1903 + .enable_mask = BIT(4),
1904 + .hw.init = &(struct clk_init_data){
1905 + .name = "sata_phy_cfg_clk",
1906 + .ops = &clk_branch_ops,
1907 + .flags = CLK_IS_ROOT,
1908 + },
1909 + },
1910 +};
1911 +
1912 +static const struct freq_tbl clk_tbl_usb30_master[] = {
1913 + { 125000000, P_PLL0, 1, 5, 32 },
1914 + { }
1915 +};
1916 +
1917 +static struct clk_rcg usb30_master_clk_src = {
1918 + .ns_reg = 0x3b2c,
1919 + .md_reg = 0x3b28,
1920 + .mn = {
1921 + .mnctr_en_bit = 8,
1922 + .mnctr_reset_bit = 7,
1923 + .mnctr_mode_shift = 5,
1924 + .n_val_shift = 16,
1925 + .m_val_shift = 16,
1926 + .width = 8,
1927 + },
1928 + .p = {
1929 + .pre_div_shift = 3,
1930 + .pre_div_width = 2,
1931 + },
1932 + .s = {
1933 + .src_sel_shift = 0,
1934 + .parent_map = gcc_pxo_pll8_pll0,
1935 + },
1936 + .freq_tbl = clk_tbl_usb30_master,
1937 + .clkr = {
1938 + .enable_reg = 0x3b2c,
1939 + .enable_mask = BIT(11),
1940 + .hw.init = &(struct clk_init_data){
1941 + .name = "usb30_master_ref_src",
1942 + .parent_names = gcc_pxo_pll8_pll0_map,
1943 + .num_parents = 3,
1944 + .ops = &clk_rcg_ops,
1945 + .flags = CLK_SET_RATE_GATE,
1946 + },
1947 + },
1948 +};
1949 +
1950 +static struct clk_branch usb30_0_branch_clk = {
1951 + .halt_reg = 0x2fc4,
1952 + .halt_bit = 22,
1953 + .clkr = {
1954 + .enable_reg = 0x3b24,
1955 + .enable_mask = BIT(4),
1956 + .hw.init = &(struct clk_init_data){
1957 + .name = "usb30_0_branch_clk",
1958 + .parent_names = (const char *[]){ "usb30_master_ref_src", },
1959 + .num_parents = 1,
1960 + .ops = &clk_branch_ops,
1961 + .flags = CLK_SET_RATE_PARENT,
1962 + },
1963 + },
1964 +};
1965 +
1966 +static struct clk_branch usb30_1_branch_clk = {
1967 + .halt_reg = 0x2fc4,
1968 + .halt_bit = 17,
1969 + .clkr = {
1970 + .enable_reg = 0x3b34,
1971 + .enable_mask = BIT(4),
1972 + .hw.init = &(struct clk_init_data){
1973 + .name = "usb30_1_branch_clk",
1974 + .parent_names = (const char *[]){ "usb30_master_ref_src", },
1975 + .num_parents = 1,
1976 + .ops = &clk_branch_ops,
1977 + .flags = CLK_SET_RATE_PARENT,
1978 + },
1979 + },
1980 +};
1981 +
1982 +static const struct freq_tbl clk_tbl_usb30_utmi[] = {
1983 + { 60000000, P_PLL0, 1, 1, 40 },
1984 + { }
1985 +};
1986 +
1987 +static struct clk_rcg usb30_utmi_clk = {
1988 + .ns_reg = 0x3b44,
1989 + .md_reg = 0x3b40,
1990 + .mn = {
1991 + .mnctr_en_bit = 8,
1992 + .mnctr_reset_bit = 7,
1993 + .mnctr_mode_shift = 5,
1994 + .n_val_shift = 16,
1995 + .m_val_shift = 16,
1996 + .width = 8,
1997 + },
1998 + .p = {
1999 + .pre_div_shift = 3,
2000 + .pre_div_width = 2,
2001 + },
2002 + .s = {
2003 + .src_sel_shift = 0,
2004 + .parent_map = gcc_pxo_pll8_pll0,
2005 + },
2006 + .freq_tbl = clk_tbl_usb30_utmi,
2007 + .clkr = {
2008 + .enable_reg = 0x3b44,
2009 + .enable_mask = BIT(11),
2010 + .hw.init = &(struct clk_init_data){
2011 + .name = "usb30_utmi_clk",
2012 + .parent_names = gcc_pxo_pll8_pll0_map,
2013 + .num_parents = 3,
2014 + .ops = &clk_rcg_ops,
2015 + .flags = CLK_SET_RATE_GATE,
2016 + },
2017 + },
2018 +};
2019 +
2020 +static struct clk_branch usb30_0_utmi_clk_ctl = {
2021 + .halt_reg = 0x2fc4,
2022 + .halt_bit = 21,
2023 + .clkr = {
2024 + .enable_reg = 0x3b48,
2025 + .enable_mask = BIT(4),
2026 + .hw.init = &(struct clk_init_data){
2027 + .name = "usb30_0_utmi_clk_ctl",
2028 + .parent_names = (const char *[]){ "usb30_utmi_clk", },
2029 + .num_parents = 1,
2030 + .ops = &clk_branch_ops,
2031 + .flags = CLK_SET_RATE_PARENT,
2032 + },
2033 + },
2034 +};
2035 +
2036 +static struct clk_branch usb30_1_utmi_clk_ctl = {
2037 + .halt_reg = 0x2fc4,
2038 + .halt_bit = 15,
2039 + .clkr = {
2040 + .enable_reg = 0x3b4c,
2041 + .enable_mask = BIT(4),
2042 + .hw.init = &(struct clk_init_data){
2043 + .name = "usb30_1_utmi_clk_ctl",
2044 + .parent_names = (const char *[]){ "usb30_utmi_clk", },
2045 + .num_parents = 1,
2046 + .ops = &clk_branch_ops,
2047 + .flags = CLK_SET_RATE_PARENT,
2048 + },
2049 + },
2050 +};
2051 +
2052 +static const struct freq_tbl clk_tbl_usb[] = {
2053 + { 60000000, P_PLL8, 1, 5, 32 },
2054 + { }
2055 +};
2056 +
2057 +static struct clk_rcg usb_hs1_xcvr_clk_src = {
2058 + .ns_reg = 0x290C,
2059 + .md_reg = 0x2908,
2060 + .mn = {
2061 + .mnctr_en_bit = 8,
2062 + .mnctr_reset_bit = 7,
2063 + .mnctr_mode_shift = 5,
2064 + .n_val_shift = 16,
2065 + .m_val_shift = 16,
2066 + .width = 8,
2067 + },
2068 + .p = {
2069 + .pre_div_shift = 3,
2070 + .pre_div_width = 2,
2071 + },
2072 + .s = {
2073 + .src_sel_shift = 0,
2074 + .parent_map = gcc_pxo_pll8_pll0,
2075 + },
2076 + .freq_tbl = clk_tbl_usb,
2077 + .clkr = {
2078 + .enable_reg = 0x2968,
2079 + .enable_mask = BIT(11),
2080 + .hw.init = &(struct clk_init_data){
2081 + .name = "usb_hs1_xcvr_src",
2082 + .parent_names = gcc_pxo_pll8_pll0_map,
2083 + .num_parents = 3,
2084 + .ops = &clk_rcg_ops,
2085 + .flags = CLK_SET_RATE_GATE,
2086 + },
2087 + },
2088 +};
2089 +
2090 +static struct clk_branch usb_hs1_xcvr_clk = {
2091 + .halt_reg = 0x2fcc,
2092 + .halt_bit = 17,
2093 + .clkr = {
2094 + .enable_reg = 0x290c,
2095 + .enable_mask = BIT(9),
2096 + .hw.init = &(struct clk_init_data){
2097 + .name = "usb_hs1_xcvr_clk",
2098 + .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2099 + .num_parents = 1,
2100 + .ops = &clk_branch_ops,
2101 + .flags = CLK_SET_RATE_PARENT,
2102 + },
2103 + },
2104 +};
2105 +
2106 +static struct clk_branch usb_hs1_h_clk = {
2107 + .hwcg_reg = 0x2900,
2108 + .hwcg_bit = 6,
2109 + .halt_reg = 0x2fc8,
2110 + .halt_bit = 1,
2111 + .clkr = {
2112 + .enable_reg = 0x2900,
2113 + .enable_mask = BIT(4),
2114 + .hw.init = &(struct clk_init_data){
2115 + .name = "usb_hs1_h_clk",
2116 + .ops = &clk_branch_ops,
2117 + .flags = CLK_IS_ROOT,
2118 + },
2119 + },
2120 +};
2121 +
2122 +static struct clk_rcg usb_fs1_xcvr_clk_src = {
2123 + .ns_reg = 0x2968,
2124 + .md_reg = 0x2964,
2125 + .mn = {
2126 + .mnctr_en_bit = 8,
2127 + .mnctr_reset_bit = 7,
2128 + .mnctr_mode_shift = 5,
2129 + .n_val_shift = 16,
2130 + .m_val_shift = 16,
2131 + .width = 8,
2132 + },
2133 + .p = {
2134 + .pre_div_shift = 3,
2135 + .pre_div_width = 2,
2136 + },
2137 + .s = {
2138 + .src_sel_shift = 0,
2139 + .parent_map = gcc_pxo_pll8_pll0,
2140 + },
2141 + .freq_tbl = clk_tbl_usb,
2142 + .clkr = {
2143 + .enable_reg = 0x2968,
2144 + .enable_mask = BIT(11),
2145 + .hw.init = &(struct clk_init_data){
2146 + .name = "usb_fs1_xcvr_src",
2147 + .parent_names = gcc_pxo_pll8_pll0_map,
2148 + .num_parents = 3,
2149 + .ops = &clk_rcg_ops,
2150 + .flags = CLK_SET_RATE_GATE,
2151 + },
2152 + },
2153 +};
2154 +
2155 +static struct clk_branch usb_fs1_xcvr_clk = {
2156 + .halt_reg = 0x2fcc,
2157 + .halt_bit = 17,
2158 + .clkr = {
2159 + .enable_reg = 0x2968,
2160 + .enable_mask = BIT(9),
2161 + .hw.init = &(struct clk_init_data){
2162 + .name = "usb_fs1_xcvr_clk",
2163 + .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2164 + .num_parents = 1,
2165 + .ops = &clk_branch_ops,
2166 + .flags = CLK_SET_RATE_PARENT,
2167 + },
2168 + },
2169 +};
2170 +
2171 +static struct clk_branch usb_fs1_sys_clk = {
2172 + .halt_reg = 0x2fcc,
2173 + .halt_bit = 18,
2174 + .clkr = {
2175 + .enable_reg = 0x296c,
2176 + .enable_mask = BIT(4),
2177 + .hw.init = &(struct clk_init_data){
2178 + .name = "usb_fs1_sys_clk",
2179 + .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2180 + .num_parents = 1,
2181 + .ops = &clk_branch_ops,
2182 + .flags = CLK_SET_RATE_PARENT,
2183 + },
2184 + },
2185 +};
2186 +
2187 +static struct clk_branch usb_fs1_h_clk = {
2188 + .halt_reg = 0x2fcc,
2189 + .halt_bit = 19,
2190 + .clkr = {
2191 + .enable_reg = 0x2960,
2192 + .enable_mask = BIT(4),
2193 + .hw.init = &(struct clk_init_data){
2194 + .name = "usb_fs1_h_clk",
2195 + .ops = &clk_branch_ops,
2196 + .flags = CLK_IS_ROOT,
2197 + },
2198 + },
2199 +};
2200 +
2201 +static struct clk_regmap *gcc_ipq806x_clks[] = {
2202 + [PLL3] = &pll3.clkr,
2203 + [PLL8] = &pll8.clkr,
2204 + [PLL8_VOTE] = &pll8_vote,
2205 + [PLL14] = &pll14.clkr,
2206 + [PLL14_VOTE] = &pll14_vote,
2207 + [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2208 + [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2209 + [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2210 + [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2211 + [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2212 + [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2213 + [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2214 + [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2215 + [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2216 + [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2217 + [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2218 + [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2219 + [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2220 + [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2221 + [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2222 + [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2223 + [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2224 + [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2225 + [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2226 + [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2227 + [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2228 + [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2229 + [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2230 + [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2231 + [GP0_SRC] = &gp0_src.clkr,
2232 + [GP0_CLK] = &gp0_clk.clkr,
2233 + [GP1_SRC] = &gp1_src.clkr,
2234 + [GP1_CLK] = &gp1_clk.clkr,
2235 + [GP2_SRC] = &gp2_src.clkr,
2236 + [GP2_CLK] = &gp2_clk.clkr,
2237 + [PMEM_A_CLK] = &pmem_clk.clkr,
2238 + [PRNG_SRC] = &prng_src.clkr,
2239 + [PRNG_CLK] = &prng_clk.clkr,
2240 + [SDC1_SRC] = &sdc1_src.clkr,
2241 + [SDC1_CLK] = &sdc1_clk.clkr,
2242 + [SDC3_SRC] = &sdc3_src.clkr,
2243 + [SDC3_CLK] = &sdc3_clk.clkr,
2244 + [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2245 + [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2246 + [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2247 + [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2248 + [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2249 + [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2250 + [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2251 + [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2252 + [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2253 + [TSIF_H_CLK] = &tsif_h_clk.clkr,
2254 + [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2255 + [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2256 + [ADM0_CLK] = &adm0_clk.clkr,
2257 + [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2258 + [PCIE_A_CLK] = &pcie_a_clk.clkr,
2259 + [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
2260 + [PCIE_H_CLK] = &pcie_h_clk.clkr,
2261 + [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
2262 + [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
2263 + [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2264 + [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2265 + [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2266 + [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2267 + [SATA_H_CLK] = &sata_h_clk.clkr,
2268 + [SATA_CLK_SRC] = &sata_ref_src.clkr,
2269 + [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
2270 + [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
2271 + [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
2272 + [SATA_A_CLK] = &sata_a_clk.clkr,
2273 + [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
2274 + [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
2275 + [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
2276 + [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
2277 + [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
2278 + [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
2279 + [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
2280 + [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
2281 + [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
2282 + [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
2283 + [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
2284 + [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
2285 + [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
2286 + [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
2287 + [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
2288 + [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
2289 + [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
2290 + [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
2291 + [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
2292 + [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
2293 + [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
2294 + [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2295 + [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
2296 + [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2297 + [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2298 + [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
2299 + [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
2300 + [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
2301 +};
2302 +
2303 +static const struct qcom_reset_map gcc_ipq806x_resets[] = {
2304 + [QDSS_STM_RESET] = { 0x2060, 6 },
2305 + [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2306 + [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2307 + [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
2308 + [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2309 + [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
2310 + [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2311 + [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2312 + [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2313 + [ADM0_C2_RESET] = { 0x220c, 4 },
2314 + [ADM0_C1_RESET] = { 0x220c, 3 },
2315 + [ADM0_C0_RESET] = { 0x220c, 2 },
2316 + [ADM0_PBUS_RESET] = { 0x220c, 1 },
2317 + [ADM0_RESET] = { 0x220c, 0 },
2318 + [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2319 + [QDSS_POR_RESET] = { 0x2260, 4 },
2320 + [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2321 + [QDSS_HRESET_RESET] = { 0x2260, 2 },
2322 + [QDSS_AXI_RESET] = { 0x2260, 1 },
2323 + [QDSS_DBG_RESET] = { 0x2260, 0 },
2324 + [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
2325 + [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
2326 + [PCIE_EXT_RESET] = { 0x22dc, 6 },
2327 + [PCIE_PHY_RESET] = { 0x22dc, 5 },
2328 + [PCIE_PCI_RESET] = { 0x22dc, 4 },
2329 + [PCIE_POR_RESET] = { 0x22dc, 3 },
2330 + [PCIE_HCLK_RESET] = { 0x22dc, 2 },
2331 + [PCIE_ACLK_RESET] = { 0x22dc, 0 },
2332 + [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2333 + [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2334 + [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2335 + [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2336 + [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2337 + [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2338 + [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2339 + [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2340 + [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2341 + [DFAB_ARB0_RESET] = { 0x2560, 7 },
2342 + [DFAB_ARB1_RESET] = { 0x2564, 7 },
2343 + [PPSS_PROC_RESET] = { 0x2594, 1 },
2344 + [PPSS_RESET] = { 0x2594, 0 },
2345 + [DMA_BAM_RESET] = { 0x25c0, 7 },
2346 + [SPS_TIC_H_RESET] = { 0x2600, 7 },
2347 + [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2348 + [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2349 + [TSIF_H_RESET] = { 0x2700, 7 },
2350 + [CE1_H_RESET] = { 0x2720, 7 },
2351 + [CE1_CORE_RESET] = { 0x2724, 7 },
2352 + [CE1_SLEEP_RESET] = { 0x2728, 7 },
2353 + [CE2_H_RESET] = { 0x2740, 7 },
2354 + [CE2_CORE_RESET] = { 0x2744, 7 },
2355 + [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2356 + [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2357 + [RPM_PROC_RESET] = { 0x27c0, 7 },
2358 + [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2359 + [SDC1_RESET] = { 0x2830, 0 },
2360 + [SDC2_RESET] = { 0x2850, 0 },
2361 + [SDC3_RESET] = { 0x2870, 0 },
2362 + [SDC4_RESET] = { 0x2890, 0 },
2363 + [USB_HS1_RESET] = { 0x2910, 0 },
2364 + [USB_HSIC_RESET] = { 0x2934, 0 },
2365 + [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2366 + [USB_FS1_RESET] = { 0x2974, 0 },
2367 + [GSBI1_RESET] = { 0x29dc, 0 },
2368 + [GSBI2_RESET] = { 0x29fc, 0 },
2369 + [GSBI3_RESET] = { 0x2a1c, 0 },
2370 + [GSBI4_RESET] = { 0x2a3c, 0 },
2371 + [GSBI5_RESET] = { 0x2a5c, 0 },
2372 + [GSBI6_RESET] = { 0x2a7c, 0 },
2373 + [GSBI7_RESET] = { 0x2a9c, 0 },
2374 + [SPDM_RESET] = { 0x2b6c, 0 },
2375 + [SEC_CTRL_RESET] = { 0x2b80, 7 },
2376 + [TLMM_H_RESET] = { 0x2ba0, 7 },
2377 + [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
2378 + [SATA_RESET] = { 0x2c1c, 0 },
2379 + [TSSC_RESET] = { 0x2ca0, 7 },
2380 + [PDM_RESET] = { 0x2cc0, 12 },
2381 + [MPM_H_RESET] = { 0x2da0, 7 },
2382 + [MPM_RESET] = { 0x2da4, 0 },
2383 + [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2384 + [PRNG_RESET] = { 0x2e80, 12 },
2385 + [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
2386 + [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
2387 + [CE3_SLEEP_RESET] = { 0x36d0, 7 },
2388 + [PCIE_1_M_RESET] = { 0x3a98, 1 },
2389 + [PCIE_1_S_RESET] = { 0x3a98, 0 },
2390 + [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
2391 + [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
2392 + [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
2393 + [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
2394 + [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
2395 + [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
2396 + [PCIE_2_M_RESET] = { 0x3ad8, 1 },
2397 + [PCIE_2_S_RESET] = { 0x3ad8, 0 },
2398 + [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
2399 + [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
2400 + [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
2401 + [PCIE_2_POR_RESET] = { 0x3adc, 3 },
2402 + [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
2403 + [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
2404 + [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
2405 + [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
2406 + [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
2407 + [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
2408 + [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
2409 + [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
2410 + [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
2411 + [USB30_0_PHY_RESET] = { 0x3b50, 0 },
2412 + [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
2413 + [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
2414 + [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
2415 + [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
2416 + [USB30_1_PHY_RESET] = { 0x3b58, 0 },
2417 + [NSSFB0_RESET] = { 0x3b60, 6 },
2418 + [NSSFB1_RESET] = { 0x3b60, 7 },
2419 +};
2420 +
2421 +static const struct regmap_config gcc_ipq806x_regmap_config = {
2422 + .reg_bits = 32,
2423 + .reg_stride = 4,
2424 + .val_bits = 32,
2425 + .max_register = 0x3e40,
2426 + .fast_io = true,
2427 +};
2428 +
2429 +static const struct qcom_cc_desc gcc_ipq806x_desc = {
2430 + .config = &gcc_ipq806x_regmap_config,
2431 + .clks = gcc_ipq806x_clks,
2432 + .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
2433 + .resets = gcc_ipq806x_resets,
2434 + .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
2435 +};
2436 +
2437 +static const struct of_device_id gcc_ipq806x_match_table[] = {
2438 + { .compatible = "qcom,gcc-ipq8064" },
2439 + { }
2440 +};
2441 +MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
2442 +
2443 +static int gcc_ipq806x_probe(struct platform_device *pdev)
2444 +{
2445 + struct clk *clk;
2446 + struct device *dev = &pdev->dev;
2447 +
2448 + /* Temporary until RPM clocks supported */
2449 + clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000);
2450 + if (IS_ERR(clk))
2451 + return PTR_ERR(clk);
2452 +
2453 + clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 25000000);
2454 + if (IS_ERR(clk))
2455 + return PTR_ERR(clk);
2456 +
2457 + return qcom_cc_probe(pdev, &gcc_ipq806x_desc);
2458 +}
2459 +
2460 +static int gcc_ipq806x_remove(struct platform_device *pdev)
2461 +{
2462 + qcom_cc_remove(pdev);
2463 + return 0;
2464 +}
2465 +
2466 +static struct platform_driver gcc_ipq806x_driver = {
2467 + .probe = gcc_ipq806x_probe,
2468 + .remove = gcc_ipq806x_remove,
2469 + .driver = {
2470 + .name = "gcc-ipq806x",
2471 + .owner = THIS_MODULE,
2472 + .of_match_table = gcc_ipq806x_match_table,
2473 + },
2474 +};
2475 +
2476 +static int __init gcc_ipq806x_init(void)
2477 +{
2478 + return platform_driver_register(&gcc_ipq806x_driver);
2479 +}
2480 +core_initcall(gcc_ipq806x_init);
2481 +
2482 +static void __exit gcc_ipq806x_exit(void)
2483 +{
2484 + platform_driver_unregister(&gcc_ipq806x_driver);
2485 +}
2486 +module_exit(gcc_ipq806x_exit);
2487 +
2488 +MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
2489 +MODULE_LICENSE("GPL v2");
2490 +MODULE_ALIAS("platform:gcc-ipq806x");
2491 --- /dev/null
2492 +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
2493 @@ -0,0 +1,293 @@
2494 +/*
2495 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
2496 + *
2497 + * This software is licensed under the terms of the GNU General Public
2498 + * License version 2, as published by the Free Software Foundation, and
2499 + * may be copied, distributed, and modified under those terms.
2500 + *
2501 + * This program is distributed in the hope that it will be useful,
2502 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2503 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2504 + * GNU General Public License for more details.
2505 + */
2506 +
2507 +#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H
2508 +#define _DT_BINDINGS_CLK_GCC_IPQ806X_H
2509 +
2510 +#define AFAB_CLK_SRC 0
2511 +#define QDSS_STM_CLK 1
2512 +#define SCSS_A_CLK 2
2513 +#define SCSS_H_CLK 3
2514 +#define AFAB_CORE_CLK 4
2515 +#define SCSS_XO_SRC_CLK 5
2516 +#define AFAB_EBI1_CH0_A_CLK 6
2517 +#define AFAB_EBI1_CH1_A_CLK 7
2518 +#define AFAB_AXI_S0_FCLK 8
2519 +#define AFAB_AXI_S1_FCLK 9
2520 +#define AFAB_AXI_S2_FCLK 10
2521 +#define AFAB_AXI_S3_FCLK 11
2522 +#define AFAB_AXI_S4_FCLK 12
2523 +#define SFAB_CORE_CLK 13
2524 +#define SFAB_AXI_S0_FCLK 14
2525 +#define SFAB_AXI_S1_FCLK 15
2526 +#define SFAB_AXI_S2_FCLK 16
2527 +#define SFAB_AXI_S3_FCLK 17
2528 +#define SFAB_AXI_S4_FCLK 18
2529 +#define SFAB_AXI_S5_FCLK 19
2530 +#define SFAB_AHB_S0_FCLK 20
2531 +#define SFAB_AHB_S1_FCLK 21
2532 +#define SFAB_AHB_S2_FCLK 22
2533 +#define SFAB_AHB_S3_FCLK 23
2534 +#define SFAB_AHB_S4_FCLK 24
2535 +#define SFAB_AHB_S5_FCLK 25
2536 +#define SFAB_AHB_S6_FCLK 26
2537 +#define SFAB_AHB_S7_FCLK 27
2538 +#define QDSS_AT_CLK_SRC 28
2539 +#define QDSS_AT_CLK 29
2540 +#define QDSS_TRACECLKIN_CLK_SRC 30
2541 +#define QDSS_TRACECLKIN_CLK 31
2542 +#define QDSS_TSCTR_CLK_SRC 32
2543 +#define QDSS_TSCTR_CLK 33
2544 +#define SFAB_ADM0_M0_A_CLK 34
2545 +#define SFAB_ADM0_M1_A_CLK 35
2546 +#define SFAB_ADM0_M2_H_CLK 36
2547 +#define ADM0_CLK 37
2548 +#define ADM0_PBUS_CLK 38
2549 +#define IMEM0_A_CLK 39
2550 +#define QDSS_H_CLK 40
2551 +#define PCIE_A_CLK 41
2552 +#define PCIE_AUX_CLK 42
2553 +#define PCIE_H_CLK 43
2554 +#define PCIE_PHY_CLK 44
2555 +#define SFAB_CLK_SRC 45
2556 +#define SFAB_LPASS_Q6_A_CLK 46
2557 +#define SFAB_AFAB_M_A_CLK 47
2558 +#define AFAB_SFAB_M0_A_CLK 48
2559 +#define AFAB_SFAB_M1_A_CLK 49
2560 +#define SFAB_SATA_S_H_CLK 50
2561 +#define DFAB_CLK_SRC 51
2562 +#define DFAB_CLK 52
2563 +#define SFAB_DFAB_M_A_CLK 53
2564 +#define DFAB_SFAB_M_A_CLK 54
2565 +#define DFAB_SWAY0_H_CLK 55
2566 +#define DFAB_SWAY1_H_CLK 56
2567 +#define DFAB_ARB0_H_CLK 57
2568 +#define DFAB_ARB1_H_CLK 58
2569 +#define PPSS_H_CLK 59
2570 +#define PPSS_PROC_CLK 60
2571 +#define PPSS_TIMER0_CLK 61
2572 +#define PPSS_TIMER1_CLK 62
2573 +#define PMEM_A_CLK 63
2574 +#define DMA_BAM_H_CLK 64
2575 +#define SIC_H_CLK 65
2576 +#define SPS_TIC_H_CLK 66
2577 +#define CFPB_2X_CLK_SRC 67
2578 +#define CFPB_CLK 68
2579 +#define CFPB0_H_CLK 69
2580 +#define CFPB1_H_CLK 70
2581 +#define CFPB2_H_CLK 71
2582 +#define SFAB_CFPB_M_H_CLK 72
2583 +#define CFPB_MASTER_H_CLK 73
2584 +#define SFAB_CFPB_S_H_CLK 74
2585 +#define CFPB_SPLITTER_H_CLK 75
2586 +#define TSIF_H_CLK 76
2587 +#define TSIF_INACTIVITY_TIMERS_CLK 77
2588 +#define TSIF_REF_SRC 78
2589 +#define TSIF_REF_CLK 79
2590 +#define CE1_H_CLK 80
2591 +#define CE1_CORE_CLK 81
2592 +#define CE1_SLEEP_CLK 82
2593 +#define CE2_H_CLK 83
2594 +#define CE2_CORE_CLK 84
2595 +#define SFPB_H_CLK_SRC 85
2596 +#define SFPB_H_CLK 86
2597 +#define SFAB_SFPB_M_H_CLK 87
2598 +#define SFAB_SFPB_S_H_CLK 88
2599 +#define RPM_PROC_CLK 89
2600 +#define RPM_BUS_H_CLK 90
2601 +#define RPM_SLEEP_CLK 91
2602 +#define RPM_TIMER_CLK 92
2603 +#define RPM_MSG_RAM_H_CLK 93
2604 +#define PMIC_ARB0_H_CLK 94
2605 +#define PMIC_ARB1_H_CLK 95
2606 +#define PMIC_SSBI2_SRC 96
2607 +#define PMIC_SSBI2_CLK 97
2608 +#define SDC1_H_CLK 98
2609 +#define SDC2_H_CLK 99
2610 +#define SDC3_H_CLK 100
2611 +#define SDC4_H_CLK 101
2612 +#define SDC1_SRC 102
2613 +#define SDC1_CLK 103
2614 +#define SDC2_SRC 104
2615 +#define SDC2_CLK 105
2616 +#define SDC3_SRC 106
2617 +#define SDC3_CLK 107
2618 +#define SDC4_SRC 108
2619 +#define SDC4_CLK 109
2620 +#define USB_HS1_H_CLK 110
2621 +#define USB_HS1_XCVR_SRC 111
2622 +#define USB_HS1_XCVR_CLK 112
2623 +#define USB_HSIC_H_CLK 113
2624 +#define USB_HSIC_XCVR_SRC 114
2625 +#define USB_HSIC_XCVR_CLK 115
2626 +#define USB_HSIC_SYSTEM_CLK_SRC 116
2627 +#define USB_HSIC_SYSTEM_CLK 117
2628 +#define CFPB0_C0_H_CLK 118
2629 +#define CFPB0_D0_H_CLK 119
2630 +#define CFPB0_C1_H_CLK 120
2631 +#define CFPB0_D1_H_CLK 121
2632 +#define USB_FS1_H_CLK 122
2633 +#define USB_FS1_XCVR_SRC 123
2634 +#define USB_FS1_XCVR_CLK 124
2635 +#define USB_FS1_SYSTEM_CLK 125
2636 +#define GSBI_COMMON_SIM_SRC 126
2637 +#define GSBI1_H_CLK 127
2638 +#define GSBI2_H_CLK 128
2639 +#define GSBI3_H_CLK 129
2640 +#define GSBI4_H_CLK 130
2641 +#define GSBI5_H_CLK 131
2642 +#define GSBI6_H_CLK 132
2643 +#define GSBI7_H_CLK 133
2644 +#define GSBI1_QUP_SRC 134
2645 +#define GSBI1_QUP_CLK 135
2646 +#define GSBI2_QUP_SRC 136
2647 +#define GSBI2_QUP_CLK 137
2648 +#define GSBI3_QUP_SRC 138
2649 +#define GSBI3_QUP_CLK 139
2650 +#define GSBI4_QUP_SRC 140
2651 +#define GSBI4_QUP_CLK 141
2652 +#define GSBI5_QUP_SRC 142
2653 +#define GSBI5_QUP_CLK 143
2654 +#define GSBI6_QUP_SRC 144
2655 +#define GSBI6_QUP_CLK 145
2656 +#define GSBI7_QUP_SRC 146
2657 +#define GSBI7_QUP_CLK 147
2658 +#define GSBI1_UART_SRC 148
2659 +#define GSBI1_UART_CLK 149
2660 +#define GSBI2_UART_SRC 150
2661 +#define GSBI2_UART_CLK 151
2662 +#define GSBI3_UART_SRC 152
2663 +#define GSBI3_UART_CLK 153
2664 +#define GSBI4_UART_SRC 154
2665 +#define GSBI4_UART_CLK 155
2666 +#define GSBI5_UART_SRC 156
2667 +#define GSBI5_UART_CLK 157
2668 +#define GSBI6_UART_SRC 158
2669 +#define GSBI6_UART_CLK 159
2670 +#define GSBI7_UART_SRC 160
2671 +#define GSBI7_UART_CLK 161
2672 +#define GSBI1_SIM_CLK 162
2673 +#define GSBI2_SIM_CLK 163
2674 +#define GSBI3_SIM_CLK 164
2675 +#define GSBI4_SIM_CLK 165
2676 +#define GSBI5_SIM_CLK 166
2677 +#define GSBI6_SIM_CLK 167
2678 +#define GSBI7_SIM_CLK 168
2679 +#define USB_HSIC_HSIC_CLK_SRC 169
2680 +#define USB_HSIC_HSIC_CLK 170
2681 +#define USB_HSIC_HSIO_CAL_CLK 171
2682 +#define SPDM_CFG_H_CLK 172
2683 +#define SPDM_MSTR_H_CLK 173
2684 +#define SPDM_FF_CLK_SRC 174
2685 +#define SPDM_FF_CLK 175
2686 +#define SEC_CTRL_CLK 176
2687 +#define SEC_CTRL_ACC_CLK_SRC 177
2688 +#define SEC_CTRL_ACC_CLK 178
2689 +#define TLMM_H_CLK 179
2690 +#define TLMM_CLK 180
2691 +#define SATA_H_CLK 181
2692 +#define SATA_CLK_SRC 182
2693 +#define SATA_RXOOB_CLK 183
2694 +#define SATA_PMALIVE_CLK 184
2695 +#define SATA_PHY_REF_CLK 185
2696 +#define SATA_A_CLK 186
2697 +#define SATA_PHY_CFG_CLK 187
2698 +#define TSSC_CLK_SRC 188
2699 +#define TSSC_CLK 189
2700 +#define PDM_SRC 190
2701 +#define PDM_CLK 191
2702 +#define GP0_SRC 192
2703 +#define GP0_CLK 193
2704 +#define GP1_SRC 194
2705 +#define GP1_CLK 195
2706 +#define GP2_SRC 196
2707 +#define GP2_CLK 197
2708 +#define MPM_CLK 198
2709 +#define EBI1_CLK_SRC 199
2710 +#define EBI1_CH0_CLK 200
2711 +#define EBI1_CH1_CLK 201
2712 +#define EBI1_2X_CLK 202
2713 +#define EBI1_CH0_DQ_CLK 203
2714 +#define EBI1_CH1_DQ_CLK 204
2715 +#define EBI1_CH0_CA_CLK 205
2716 +#define EBI1_CH1_CA_CLK 206
2717 +#define EBI1_XO_CLK 207
2718 +#define SFAB_SMPSS_S_H_CLK 208
2719 +#define PRNG_SRC 209
2720 +#define PRNG_CLK 210
2721 +#define PXO_SRC 211
2722 +#define SPDM_CY_PORT0_CLK 212
2723 +#define SPDM_CY_PORT1_CLK 213
2724 +#define SPDM_CY_PORT2_CLK 214
2725 +#define SPDM_CY_PORT3_CLK 215
2726 +#define SPDM_CY_PORT4_CLK 216
2727 +#define SPDM_CY_PORT5_CLK 217
2728 +#define SPDM_CY_PORT6_CLK 218
2729 +#define SPDM_CY_PORT7_CLK 219
2730 +#define PLL0 220
2731 +#define PLL0_VOTE 221
2732 +#define PLL3 222
2733 +#define PLL3_VOTE 223
2734 +#define PLL4 224
2735 +#define PLL4_VOTE 225
2736 +#define PLL8 226
2737 +#define PLL8_VOTE 227
2738 +#define PLL9 228
2739 +#define PLL10 229
2740 +#define PLL11 230
2741 +#define PLL12 231
2742 +#define PLL14 232
2743 +#define PLL14_VOTE 233
2744 +#define PLL18 234
2745 +#define CE5_SRC 235
2746 +#define CE5_H_CLK 236
2747 +#define CE5_CORE_CLK 237
2748 +#define CE3_SLEEP_CLK 238
2749 +#define SFAB_AHB_S8_FCLK 239
2750 +#define SPDM_CY_PORT8_CLK 246
2751 +#define PCIE_ALT_REF_SRC 247
2752 +#define PCIE_ALT_REF_CLK 248
2753 +#define PCIE_1_A_CLK 249
2754 +#define PCIE_1_AUX_CLK 250
2755 +#define PCIE_1_H_CLK 251
2756 +#define PCIE_1_PHY_CLK 252
2757 +#define PCIE_1_ALT_REF_SRC 253
2758 +#define PCIE_1_ALT_REF_CLK 254
2759 +#define PCIE_2_A_CLK 255
2760 +#define PCIE_2_AUX_CLK 256
2761 +#define PCIE_2_H_CLK 257
2762 +#define PCIE_2_PHY_CLK 258
2763 +#define PCIE_2_ALT_REF_SRC 259
2764 +#define PCIE_2_ALT_REF_CLK 260
2765 +#define EBI2_CLK 261
2766 +#define USB30_SLEEP_CLK 262
2767 +#define USB30_UTMI_SRC 263
2768 +#define USB30_0_UTMI_CLK 264
2769 +#define USB30_1_UTMI_CLK 264
2770 +#define USB30_MASTER_SRC 265
2771 +#define USB30_0_MASTER_CLK 266
2772 +#define USB30_1_MASTER_CLK 267
2773 +#define GMAC_CORE1_CLK_SRC 268
2774 +#define GMAC_CORE2_CLK_SRC 269
2775 +#define GMAC_CORE3_CLK_SRC 270
2776 +#define GMAC_CORE4_CLK_SRC 271
2777 +#define GMAC_CORE1_CLK 272
2778 +#define GMAC_CORE2_CLK 273
2779 +#define GMAC_CORE3_CLK 274
2780 +#define GMAC_CORE4_CLK 275
2781 +#define UBI32_CORE1_CLK_SRC 276
2782 +#define UBI32_CORE2_CLK_SRC 277
2783 +#define UBI32_CORE1_CLK 278
2784 +#define UBI32_CORE2_CLK 279
2785 +
2786 +#endif
2787 --- /dev/null
2788 +++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
2789 @@ -0,0 +1,132 @@
2790 +/*
2791 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
2792 + *
2793 + * This software is licensed under the terms of the GNU General Public
2794 + * License version 2, as published by the Free Software Foundation, and
2795 + * may be copied, distributed, and modified under those terms.
2796 + *
2797 + * This program is distributed in the hope that it will be useful,
2798 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2799 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2800 + * GNU General Public License for more details.
2801 + */
2802 +
2803 +#ifndef _DT_BINDINGS_RESET_IPQ_806X_H
2804 +#define _DT_BINDINGS_RESET_IPQ_806X_H
2805 +
2806 +#define QDSS_STM_RESET 0
2807 +#define AFAB_SMPSS_S_RESET 1
2808 +#define AFAB_SMPSS_M1_RESET 2
2809 +#define AFAB_SMPSS_M0_RESET 3
2810 +#define AFAB_EBI1_CH0_RESET 4
2811 +#define AFAB_EBI1_CH1_RESET 5
2812 +#define SFAB_ADM0_M0_RESET 6
2813 +#define SFAB_ADM0_M1_RESET 7
2814 +#define SFAB_ADM0_M2_RESET 8
2815 +#define ADM0_C2_RESET 9
2816 +#define ADM0_C1_RESET 10
2817 +#define ADM0_C0_RESET 11
2818 +#define ADM0_PBUS_RESET 12
2819 +#define ADM0_RESET 13
2820 +#define QDSS_CLKS_SW_RESET 14
2821 +#define QDSS_POR_RESET 15
2822 +#define QDSS_TSCTR_RESET 16
2823 +#define QDSS_HRESET_RESET 17
2824 +#define QDSS_AXI_RESET 18
2825 +#define QDSS_DBG_RESET 19
2826 +#define SFAB_PCIE_M_RESET 20
2827 +#define SFAB_PCIE_S_RESET 21
2828 +#define PCIE_EXT_RESET 22
2829 +#define PCIE_PHY_RESET 23
2830 +#define PCIE_PCI_RESET 24
2831 +#define PCIE_POR_RESET 25
2832 +#define PCIE_HCLK_RESET 26
2833 +#define PCIE_ACLK_RESET 27
2834 +#define SFAB_LPASS_RESET 28
2835 +#define SFAB_AFAB_M_RESET 29
2836 +#define AFAB_SFAB_M0_RESET 30
2837 +#define AFAB_SFAB_M1_RESET 31
2838 +#define SFAB_SATA_S_RESET 32
2839 +#define SFAB_DFAB_M_RESET 33
2840 +#define DFAB_SFAB_M_RESET 34
2841 +#define DFAB_SWAY0_RESET 35
2842 +#define DFAB_SWAY1_RESET 36
2843 +#define DFAB_ARB0_RESET 37
2844 +#define DFAB_ARB1_RESET 38
2845 +#define PPSS_PROC_RESET 39
2846 +#define PPSS_RESET 40
2847 +#define DMA_BAM_RESET 41
2848 +#define SPS_TIC_H_RESET 42
2849 +#define SFAB_CFPB_M_RESET 43
2850 +#define SFAB_CFPB_S_RESET 44
2851 +#define TSIF_H_RESET 45
2852 +#define CE1_H_RESET 46
2853 +#define CE1_CORE_RESET 47
2854 +#define CE1_SLEEP_RESET 48
2855 +#define CE2_H_RESET 49
2856 +#define CE2_CORE_RESET 50
2857 +#define SFAB_SFPB_M_RESET 51
2858 +#define SFAB_SFPB_S_RESET 52
2859 +#define RPM_PROC_RESET 53
2860 +#define PMIC_SSBI2_RESET 54
2861 +#define SDC1_RESET 55
2862 +#define SDC2_RESET 56
2863 +#define SDC3_RESET 57
2864 +#define SDC4_RESET 58
2865 +#define USB_HS1_RESET 59
2866 +#define USB_HSIC_RESET 60
2867 +#define USB_FS1_XCVR_RESET 61
2868 +#define USB_FS1_RESET 62
2869 +#define GSBI1_RESET 63
2870 +#define GSBI2_RESET 64
2871 +#define GSBI3_RESET 65
2872 +#define GSBI4_RESET 66
2873 +#define GSBI5_RESET 67
2874 +#define GSBI6_RESET 68
2875 +#define GSBI7_RESET 69
2876 +#define SPDM_RESET 70
2877 +#define SEC_CTRL_RESET 71
2878 +#define TLMM_H_RESET 72
2879 +#define SFAB_SATA_M_RESET 73
2880 +#define SATA_RESET 74
2881 +#define TSSC_RESET 75
2882 +#define PDM_RESET 76
2883 +#define MPM_H_RESET 77
2884 +#define MPM_RESET 78
2885 +#define SFAB_SMPSS_S_RESET 79
2886 +#define PRNG_RESET 80
2887 +#define SFAB_CE3_M_RESET 81
2888 +#define SFAB_CE3_S_RESET 82
2889 +#define CE3_SLEEP_RESET 83
2890 +#define PCIE_1_M_RESET 84
2891 +#define PCIE_1_S_RESET 85
2892 +#define PCIE_1_EXT_RESET 86
2893 +#define PCIE_1_PHY_RESET 87
2894 +#define PCIE_1_PCI_RESET 88
2895 +#define PCIE_1_POR_RESET 89
2896 +#define PCIE_1_HCLK_RESET 90
2897 +#define PCIE_1_ACLK_RESET 91
2898 +#define PCIE_2_M_RESET 92
2899 +#define PCIE_2_S_RESET 93
2900 +#define PCIE_2_EXT_RESET 94
2901 +#define PCIE_2_PHY_RESET 95
2902 +#define PCIE_2_PCI_RESET 96
2903 +#define PCIE_2_POR_RESET 97
2904 +#define PCIE_2_HCLK_RESET 98
2905 +#define PCIE_2_ACLK_RESET 99
2906 +#define SFAB_USB30_S_RESET 100
2907 +#define SFAB_USB30_M_RESET 101
2908 +#define USB30_0_PORT2_HS_PHY_RESET 102
2909 +#define USB30_0_MASTER_RESET 103
2910 +#define USB30_0_SLEEP_RESET 104
2911 +#define USB30_0_UTMI_PHY_RESET 105
2912 +#define USB30_0_POWERON_RESET 106
2913 +#define USB30_0_PHY_RESET 107
2914 +#define USB30_1_MASTER_RESET 108
2915 +#define USB30_1_SLEEP_RESET 109
2916 +#define USB30_1_UTMI_PHY_RESET 110
2917 +#define USB30_1_POWERON_RESET 111
2918 +#define USB30_1_PHY_RESET 112
2919 +#define NSSFB0_RESET 113
2920 +#define NSSFB1_RESET 114
2921 +#endif
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