target/linux/ipq806x/patches/0106-clk-qcom-Properly-support-display-clocks-on-msm8974.patch

   1 From 4ccbe584ecb970f86bab58c0ca93998cccc9e810 Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Fri, 16 May 2014 16:07:12 -0700
   4 Subject: [PATCH 106/182] clk: qcom: Properly support display clocks on
   5  msm8974
   6
   7 The display clocks all source from dedicated phy PLLs within their
   8 respective multimedia hardware block. Hook up these PLLs to the
   9 display clocks with the appropriate parent mappings, clock flags,
  10 and the appropriate clock ops. This should allow the display
  11 clocks to work once the appropriate phy PLL driver registers their
  12 PLL clocks.
  13
  14 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  15 Signed-off-by: Mike Turquette <mturquette@linaro.org>
  16 ---
  17  drivers/clk/qcom/mmcc-msm8974.c |  105 ++++++++++++++++++++-------------------
  18  1 file changed, 54 insertions(+), 51 deletions(-)
  19
  20 --- a/drivers/clk/qcom/mmcc-msm8974.c
  21 +++ b/drivers/clk/qcom/mmcc-msm8974.c
  22 @@ -41,9 +41,11 @@
  23  #define P_EDPVCO       3
  24  #define P_GPLL1                4
  25  #define P_DSI0PLL      4
  26 +#define P_DSI0PLL_BYTE 4
  27  #define P_MMPLL2       4
  28  #define P_MMPLL3       4
  29  #define P_DSI1PLL      5
  30 +#define P_DSI1PLL_BYTE 5
  31
  32  static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
  33         [P_XO]          = 0,
  34 @@ -161,6 +163,24 @@ static const char *mmcc_xo_dsi_hdmi_edp_
  35         "dsi1pll",
  36  };
  37
  38 +static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
  39 +       [P_XO]                  = 0,
  40 +       [P_EDPLINK]             = 4,
  41 +       [P_HDMIPLL]             = 3,
  42 +       [P_GPLL0]               = 5,
  43 +       [P_DSI0PLL_BYTE]        = 1,
  44 +       [P_DSI1PLL_BYTE]        = 2,
  45 +};
  46 +
  47 +static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
  48 +       "xo",
  49 +       "edp_link_clk",
  50 +       "hdmipll",
  51 +       "gpll0_vote",
  52 +       "dsi0pllbyte",
  53 +       "dsi1pllbyte",
  54 +};
  55 +
  56  #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  57
  58  static struct clk_pll mmpll0 = {
  59 @@ -500,15 +520,8 @@ static struct clk_rcg2 jpeg2_clk_src = {
  60         },
  61  };
  62
  63 -static struct freq_tbl ftbl_mdss_pclk0_clk[] = {
  64 -       F(125000000, P_DSI0PLL, 2, 0, 0),
  65 -       F(250000000, P_DSI0PLL, 1, 0, 0),
  66 -       { }
  67 -};
  68 -
  69 -static struct freq_tbl ftbl_mdss_pclk1_clk[] = {
  70 -       F(125000000, P_DSI1PLL, 2, 0, 0),
  71 -       F(250000000, P_DSI1PLL, 1, 0, 0),
  72 +static struct freq_tbl pixel_freq_tbl[] = {
  73 +       { .src = P_DSI0PLL },
  74         { }
  75  };
  76
  77 @@ -517,12 +530,13 @@ static struct clk_rcg2 pclk0_clk_src = {
  78         .mnd_width = 8,
  79         .hid_width = 5,
  80         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
  81 -       .freq_tbl = ftbl_mdss_pclk0_clk,
  82 +       .freq_tbl = pixel_freq_tbl,
  83         .clkr.hw.init = &(struct clk_init_data){
  84                 .name = "pclk0_clk_src",
  85                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
  86                 .num_parents = 6,
  87 -               .ops = &clk_rcg2_ops,
  88 +               .ops = &clk_pixel_ops,
  89 +               .flags = CLK_SET_RATE_PARENT,
  90         },
  91  };
  92
  93 @@ -531,12 +545,13 @@ static struct clk_rcg2 pclk1_clk_src = {
  94         .mnd_width = 8,
  95         .hid_width = 5,
  96         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
  97 -       .freq_tbl = ftbl_mdss_pclk1_clk,
  98 +       .freq_tbl = pixel_freq_tbl,
  99         .clkr.hw.init = &(struct clk_init_data){
 100                 .name = "pclk1_clk_src",
 101                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 102                 .num_parents = 6,
 103 -               .ops = &clk_rcg2_ops,
 104 +               .ops = &clk_pixel_ops,
 105 +               .flags = CLK_SET_RATE_PARENT,
 106         },
 107  };
 108
 109 @@ -754,41 +769,36 @@ static struct clk_rcg2 cpp_clk_src = {
 110         },
 111  };
 112
 113 -static struct freq_tbl ftbl_mdss_byte0_clk[] = {
 114 -       F(93750000, P_DSI0PLL, 8, 0, 0),
 115 -       F(187500000, P_DSI0PLL, 4, 0, 0),
 116 -       { }
 117 -};
 118 -
 119 -static struct freq_tbl ftbl_mdss_byte1_clk[] = {
 120 -       F(93750000, P_DSI1PLL, 8, 0, 0),
 121 -       F(187500000, P_DSI1PLL, 4, 0, 0),
 122 +static struct freq_tbl byte_freq_tbl[] = {
 123 +       { .src = P_DSI0PLL_BYTE },
 124         { }
 125  };
 126
 127  static struct clk_rcg2 byte0_clk_src = {
 128         .cmd_rcgr = 0x2120,
 129         .hid_width = 5,
 130 -       .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 131 -       .freq_tbl = ftbl_mdss_byte0_clk,
 132 +       .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 133 +       .freq_tbl = byte_freq_tbl,
 134         .clkr.hw.init = &(struct clk_init_data){
 135                 .name = "byte0_clk_src",
 136 -               .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 137 +               .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 138                 .num_parents = 6,
 139 -               .ops = &clk_rcg2_ops,
 140 +               .ops = &clk_byte_ops,
 141 +               .flags = CLK_SET_RATE_PARENT,
 142         },
 143  };
 144
 145  static struct clk_rcg2 byte1_clk_src = {
 146         .cmd_rcgr = 0x2140,
 147         .hid_width = 5,
 148 -       .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 149 -       .freq_tbl = ftbl_mdss_byte1_clk,
 150 +       .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 151 +       .freq_tbl = byte_freq_tbl,
 152         .clkr.hw.init = &(struct clk_init_data){
 153                 .name = "byte1_clk_src",
 154 -               .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 155 +               .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 156                 .num_parents = 6,
 157 -               .ops = &clk_rcg2_ops,
 158 +               .ops = &clk_byte_ops,
 159 +               .flags = CLK_SET_RATE_PARENT,
 160         },
 161  };
 162
 163 @@ -826,12 +836,12 @@ static struct clk_rcg2 edplink_clk_src =
 164                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 165                 .num_parents = 6,
 166                 .ops = &clk_rcg2_ops,
 167 +               .flags = CLK_SET_RATE_PARENT,
 168         },
 169  };
 170
 171 -static struct freq_tbl ftbl_mdss_edppixel_clk[] = {
 172 -       F(175000000, P_EDPVCO, 2, 0, 0),
 173 -       F(350000000, P_EDPVCO, 11, 0, 0),
 174 +static struct freq_tbl edp_pixel_freq_tbl[] = {
 175 +       { .src = P_EDPVCO },
 176         { }
 177  };
 178
 179 @@ -840,12 +850,12 @@ static struct clk_rcg2 edppixel_clk_src
 180         .mnd_width = 8,
 181         .hid_width = 5,
 182         .parent_map = mmcc_xo_dsi_hdmi_edp_map,
 183 -       .freq_tbl = ftbl_mdss_edppixel_clk,
 184 +       .freq_tbl = edp_pixel_freq_tbl,
 185         .clkr.hw.init = &(struct clk_init_data){
 186                 .name = "edppixel_clk_src",
 187                 .parent_names = mmcc_xo_dsi_hdmi_edp,
 188                 .num_parents = 6,
 189 -               .ops = &clk_rcg2_ops,
 190 +               .ops = &clk_edp_pixel_ops,
 191         },
 192  };
 193
 194 @@ -857,11 +867,11 @@ static struct freq_tbl ftbl_mdss_esc0_1_
 195  static struct clk_rcg2 esc0_clk_src = {
 196         .cmd_rcgr = 0x2160,
 197         .hid_width = 5,
 198 -       .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 199 +       .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 200         .freq_tbl = ftbl_mdss_esc0_1_clk,
 201         .clkr.hw.init = &(struct clk_init_data){
 202                 .name = "esc0_clk_src",
 203 -               .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 204 +               .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 205                 .num_parents = 6,
 206                 .ops = &clk_rcg2_ops,
 207         },
 208 @@ -870,26 +880,18 @@ static struct clk_rcg2 esc0_clk_src = {
 209  static struct clk_rcg2 esc1_clk_src = {
 210         .cmd_rcgr = 0x2180,
 211         .hid_width = 5,
 212 -       .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 213 +       .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 214         .freq_tbl = ftbl_mdss_esc0_1_clk,
 215         .clkr.hw.init = &(struct clk_init_data){
 216                 .name = "esc1_clk_src",
 217 -               .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 218 +               .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 219                 .num_parents = 6,
 220                 .ops = &clk_rcg2_ops,
 221         },
 222  };
 223
 224 -static struct freq_tbl ftbl_mdss_extpclk_clk[] = {
 225 -       F(25200000, P_HDMIPLL, 1, 0, 0),
 226 -       F(27000000, P_HDMIPLL, 1, 0, 0),
 227 -       F(27030000, P_HDMIPLL, 1, 0, 0),
 228 -       F(65000000, P_HDMIPLL, 1, 0, 0),
 229 -       F(74250000, P_HDMIPLL, 1, 0, 0),
 230 -       F(108000000, P_HDMIPLL, 1, 0, 0),
 231 -       F(148500000, P_HDMIPLL, 1, 0, 0),
 232 -       F(268500000, P_HDMIPLL, 1, 0, 0),
 233 -       F(297000000, P_HDMIPLL, 1, 0, 0),
 234 +static struct freq_tbl extpclk_freq_tbl[] = {
 235 +       { .src = P_HDMIPLL },
 236         { }
 237  };
 238
 239 @@ -897,12 +899,13 @@ static struct clk_rcg2 extpclk_clk_src =
 240         .cmd_rcgr = 0x2060,
 241         .hid_width = 5,
 242         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 243 -       .freq_tbl = ftbl_mdss_extpclk_clk,
 244 +       .freq_tbl = extpclk_freq_tbl,
 245         .clkr.hw.init = &(struct clk_init_data){
 246                 .name = "extpclk_clk_src",
 247                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 248                 .num_parents = 6,
 249 -               .ops = &clk_rcg2_ops,
 250 +               .ops = &clk_byte_ops,
 251 +               .flags = CLK_SET_RATE_PARENT,
 252         },
 253  };
 254