target/linux/ipq806x/patches/0096-ARM-dts-qcom-Add-APQ8084-SoC-support.patch

   1 From 8c52931421759b70fc37771be3390813a2a2f9f5 Mon Sep 17 00:00:00 2001
   2 From: Georgi Djakov <gdjakov@mm-sol.com>
   3 Date: Fri, 23 May 2014 18:12:29 +0300
   4 Subject: [PATCH 096/182] ARM: dts: qcom: Add APQ8084 SoC support
   5
   6 Add support for the Qualcomm Snapdragon 805 APQ8084 SoC. It is
   7 used on APQ8084-MTP and other boards.
   8
   9 Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
  10 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  11 ---
  12  arch/arm/boot/dts/qcom-apq8084.dtsi |  179 +++++++++++++++++++++++++++++++++++
  13  arch/arm/mach-qcom/board.c          |    1 +
  14  2 files changed, 180 insertions(+)
  15  create mode 100644 arch/arm/boot/dts/qcom-apq8084.dtsi
  16
  17 --- /dev/null
  18 +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
  19 @@ -0,0 +1,179 @@
  20 +/dts-v1/;
  21 +
  22 +#include "skeleton.dtsi"
  23 +
  24 +/ {
  25 +       model = "Qualcomm APQ 8084";
  26 +       compatible = "qcom,apq8084";
  27 +       interrupt-parent = <&intc>;
  28 +
  29 +       cpus {
  30 +               #address-cells = <1>;
  31 +               #size-cells = <0>;
  32 +
  33 +               cpu@0 {
  34 +                       device_type = "cpu";
  35 +                       compatible = "qcom,krait";
  36 +                       reg = <0>;
  37 +                       enable-method = "qcom,kpss-acc-v2";
  38 +                       next-level-cache = <&L2>;
  39 +                       qcom,acc = <&acc0>;
  40 +               };
  41 +
  42 +               cpu@1 {
  43 +                       device_type = "cpu";
  44 +                       compatible = "qcom,krait";
  45 +                       reg = <1>;
  46 +                       enable-method = "qcom,kpss-acc-v2";
  47 +                       next-level-cache = <&L2>;
  48 +                       qcom,acc = <&acc1>;
  49 +               };
  50 +
  51 +               cpu@2 {
  52 +                       device_type = "cpu";
  53 +                       compatible = "qcom,krait";
  54 +                       reg = <2>;
  55 +                       enable-method = "qcom,kpss-acc-v2";
  56 +                       next-level-cache = <&L2>;
  57 +                       qcom,acc = <&acc2>;
  58 +               };
  59 +
  60 +               cpu@3 {
  61 +                       device_type = "cpu";
  62 +                       compatible = "qcom,krait";
  63 +                       reg = <3>;
  64 +                       enable-method = "qcom,kpss-acc-v2";
  65 +                       next-level-cache = <&L2>;
  66 +                       qcom,acc = <&acc3>;
  67 +               };
  68 +
  69 +               L2: l2-cache {
  70 +                       compatible = "qcom,arch-cache";
  71 +                       cache-level = <2>;
  72 +                       qcom,saw = <&saw_l2>;
  73 +               };
  74 +       };
  75 +
  76 +       cpu-pmu {
  77 +               compatible = "qcom,krait-pmu";
  78 +               interrupts = <1 7 0xf04>;
  79 +       };
  80 +
  81 +       timer {
  82 +               compatible = "arm,armv7-timer";
  83 +               interrupts = <1 2 0xf08>,
  84 +                            <1 3 0xf08>,
  85 +                            <1 4 0xf08>,
  86 +                            <1 1 0xf08>;
  87 +               clock-frequency = <19200000>;
  88 +       };
  89 +
  90 +       soc: soc {
  91 +               #address-cells = <1>;
  92 +               #size-cells = <1>;
  93 +               ranges;
  94 +               compatible = "simple-bus";
  95 +
  96 +               intc: interrupt-controller@f9000000 {
  97 +                       compatible = "qcom,msm-qgic2";
  98 +                       interrupt-controller;
  99 +                       #interrupt-cells = <3>;
 100 +                       reg = <0xf9000000 0x1000>,
 101 +                             <0xf9002000 0x1000>;
 102 +               };
 103 +
 104 +               timer@f9020000 {
 105 +                       #address-cells = <1>;
 106 +                       #size-cells = <1>;
 107 +                       ranges;
 108 +                       compatible = "arm,armv7-timer-mem";
 109 +                       reg = <0xf9020000 0x1000>;
 110 +                       clock-frequency = <19200000>;
 111 +
 112 +                       frame@f9021000 {
 113 +                               frame-number = <0>;
 114 +                               interrupts = <0 8 0x4>,
 115 +                                            <0 7 0x4>;
 116 +                               reg = <0xf9021000 0x1000>,
 117 +                                     <0xf9022000 0x1000>;
 118 +                       };
 119 +
 120 +                       frame@f9023000 {
 121 +                               frame-number = <1>;
 122 +                               interrupts = <0 9 0x4>;
 123 +                               reg = <0xf9023000 0x1000>;
 124 +                               status = "disabled";
 125 +                       };
 126 +
 127 +                       frame@f9024000 {
 128 +                               frame-number = <2>;
 129 +                               interrupts = <0 10 0x4>;
 130 +                               reg = <0xf9024000 0x1000>;
 131 +                               status = "disabled";
 132 +                       };
 133 +
 134 +                       frame@f9025000 {
 135 +                               frame-number = <3>;
 136 +                               interrupts = <0 11 0x4>;
 137 +                               reg = <0xf9025000 0x1000>;
 138 +                               status = "disabled";
 139 +                       };
 140 +
 141 +                       frame@f9026000 {
 142 +                               frame-number = <4>;
 143 +                               interrupts = <0 12 0x4>;
 144 +                               reg = <0xf9026000 0x1000>;
 145 +                               status = "disabled";
 146 +                       };
 147 +
 148 +                       frame@f9027000 {
 149 +                               frame-number = <5>;
 150 +                               interrupts = <0 13 0x4>;
 151 +                               reg = <0xf9027000 0x1000>;
 152 +                               status = "disabled";
 153 +                       };
 154 +
 155 +                       frame@f9028000 {
 156 +                               frame-number = <6>;
 157 +                               interrupts = <0 14 0x4>;
 158 +                               reg = <0xf9028000 0x1000>;
 159 +                               status = "disabled";
 160 +                       };
 161 +               };
 162 +
 163 +               saw_l2: regulator@f9012000 {
 164 +                       compatible = "qcom,saw2";
 165 +                       reg = <0xf9012000 0x1000>;
 166 +                       regulator;
 167 +               };
 168 +
 169 +               acc0: clock-controller@f9088000 {
 170 +                       compatible = "qcom,kpss-acc-v2";
 171 +                       reg = <0xf9088000 0x1000>,
 172 +                             <0xf9008000 0x1000>;
 173 +               };
 174 +
 175 +               acc1: clock-controller@f9098000 {
 176 +                       compatible = "qcom,kpss-acc-v2";
 177 +                       reg = <0xf9098000 0x1000>,
 178 +                             <0xf9008000 0x1000>;
 179 +               };
 180 +
 181 +               acc2: clock-controller@f90a8000 {
 182 +                       compatible = "qcom,kpss-acc-v2";
 183 +                       reg = <0xf90a8000 0x1000>,
 184 +                             <0xf9008000 0x1000>;
 185 +               };
 186 +
 187 +               acc3: clock-controller@f90b8000 {
 188 +                       compatible = "qcom,kpss-acc-v2";
 189 +                       reg = <0xf90b8000 0x1000>,
 190 +                             <0xf9008000 0x1000>;
 191 +               };
 192 +
 193 +               restart@fc4ab000 {
 194 +                       compatible = "qcom,pshold";
 195 +                       reg = <0xfc4ab000 0x4>;
 196 +               };
 197 +       };
 198 +};
 199 --- a/arch/arm/mach-qcom/board.c
 200 +++ b/arch/arm/mach-qcom/board.c
 201 @@ -17,6 +17,7 @@
 202  static const char * const qcom_dt_match[] __initconst = {
 203         "qcom,apq8064",
 204         "qcom,apq8074-dragonboard",
 205 +       "qcom,apq8084",
 206         "qcom,msm8660-surf",
 207         "qcom,msm8960-cdp",
 208         NULL