target/linux/ipq806x/patches/0084-soc-qcom-Add-GSBI-driver.patch

   1 From a2f0fc20ea49e5dbbdbb21444683ea760fbdd38f Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Thu, 24 Apr 2014 11:31:21 -0500
   4 Subject: [PATCH 084/182] soc: qcom: Add GSBI driver
   5
   6 The GSBI (General Serial Bus Interface) driver controls the overarching
   7 configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and
   8 earlier QCOM processors.  The GSBI supports UART, I2C, SPI, and UIM
   9 functionality in various combinations.
  10
  11 Signed-off-by: Andy Gross <agross@codeaurora.org>
  12 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  13 ---
  14  drivers/soc/Kconfig          |    2 +
  15  drivers/soc/Makefile         |    5 +++
  16  drivers/soc/qcom/Kconfig     |   11 ++++++
  17  drivers/soc/qcom/Makefile    |    1 +
  18  drivers/soc/qcom/qcom_gsbi.c |   84 ++++++++++++++++++++++++++++++++++++++++++
  19  5 files changed, 103 insertions(+)
  20  create mode 100644 drivers/soc/Makefile
  21  create mode 100644 drivers/soc/qcom/Kconfig
  22  create mode 100644 drivers/soc/qcom/Makefile
  23  create mode 100644 drivers/soc/qcom/qcom_gsbi.c
  24
  25 --- a/drivers/soc/Kconfig
  26 +++ b/drivers/soc/Kconfig
  27 @@ -1,3 +1,5 @@
  28  menu "SOC (System On Chip) specific Drivers"
  29
  30 +source "drivers/soc/qcom/Kconfig"
  31 +
  32  endmenu
  33 --- /dev/null
  34 +++ b/drivers/soc/Makefile
  35 @@ -0,0 +1,5 @@
  36 +#
  37 +# Makefile for the Linux Kernel SOC specific device drivers.
  38 +#
  39 +
  40 +obj-$(CONFIG_ARCH_QCOM)                += qcom/
  41 --- /dev/null
  42 +++ b/drivers/soc/qcom/Kconfig
  43 @@ -0,0 +1,11 @@
  44 +#
  45 +# QCOM Soc drivers
  46 +#
  47 +config QCOM_GSBI
  48 +        tristate "QCOM General Serial Bus Interface"
  49 +        depends on ARCH_QCOM
  50 +        help
  51 +          Say y here to enable GSBI support.  The GSBI provides control
  52 +          functions for connecting the underlying serial UART, SPI, and I2C
  53 +          devices to the output pins.
  54 +
  55 --- /dev/null
  56 +++ b/drivers/soc/qcom/Makefile
  57 @@ -0,0 +1 @@
  58 +obj-$(CONFIG_QCOM_GSBI)        +=      qcom_gsbi.o
  59 --- /dev/null
  60 +++ b/drivers/soc/qcom/qcom_gsbi.c
  61 @@ -0,0 +1,84 @@
  62 +/*
  63 + * Copyright (c) 2014, The Linux foundation. All rights reserved.
  64 + *
  65 + * This program is free software; you can redistribute it and/or modify
  66 + * it under the terms of the GNU General Public License rev 2 and
  67 + * only rev 2 as published by the free Software foundation.
  68 + *
  69 + * This program is distributed in the hope that it will be useful,
  70 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  71 + * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE.  See the
  72 + * GNU General Public License for more details.
  73 + */
  74 +
  75 +#include <linux/clk.h>
  76 +#include <linux/err.h>
  77 +#include <linux/io.h>
  78 +#include <linux/module.h>
  79 +#include <linux/of.h>
  80 +#include <linux/of_platform.h>
  81 +#include <linux/platform_device.h>
  82 +
  83 +#define GSBI_CTRL_REG          0x0000
  84 +#define GSBI_PROTOCOL_SHIFT    4
  85 +
  86 +static int gsbi_probe(struct platform_device *pdev)
  87 +{
  88 +       struct device_node *node = pdev->dev.of_node;
  89 +       struct resource *res;
  90 +       void __iomem *base;
  91 +       struct clk *hclk;
  92 +       u32 mode, crci = 0;
  93 +
  94 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  95 +       base = devm_ioremap_resource(&pdev->dev, res);
  96 +       if (IS_ERR(base))
  97 +               return PTR_ERR(base);
  98 +
  99 +       if (of_property_read_u32(node, "qcom,mode", &mode)) {
 100 +               dev_err(&pdev->dev, "missing mode configuration\n");
 101 +               return -EINVAL;
 102 +       }
 103 +
 104 +       /* not required, so default to 0 if not present */
 105 +       of_property_read_u32(node, "qcom,crci", &crci);
 106 +
 107 +       dev_info(&pdev->dev, "GSBI port protocol: %d crci: %d\n", mode, crci);
 108 +
 109 +       hclk = devm_clk_get(&pdev->dev, "iface");
 110 +       if (IS_ERR(hclk))
 111 +               return PTR_ERR(hclk);
 112 +
 113 +       clk_prepare_enable(hclk);
 114 +
 115 +       writel_relaxed((mode << GSBI_PROTOCOL_SHIFT) | crci,
 116 +                               base + GSBI_CTRL_REG);
 117 +
 118 +       /* make sure the gsbi control write is not reordered */
 119 +       wmb();
 120 +
 121 +       clk_disable_unprepare(hclk);
 122 +
 123 +       return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
 124 +}
 125 +
 126 +static const struct of_device_id gsbi_dt_match[] = {
 127 +       { .compatible = "qcom,gsbi-v1.0.0", },
 128 +};
 129 +
 130 +MODULE_DEVICE_TABLE(of, gsbi_dt_match);
 131 +
 132 +static struct platform_driver gsbi_driver = {
 133 +       .driver = {
 134 +               .name           = "gsbi",
 135 +               .owner          = THIS_MODULE,
 136 +               .of_match_table = gsbi_dt_match,
 137 +       },
 138 +       .probe = gsbi_probe,
 139 +};
 140 +
 141 +module_platform_driver(gsbi_driver);
 142 +
 143 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
 144 +MODULE_DESCRIPTION("QCOM GSBI driver");
 145 +MODULE_LICENSE("GPL v2");