target/linux/ipq806x/patches/0048-mmc-sdhci-msm-Add-platform_execute_tuning-implementa.patch

   1 From c2a237b3e467c8bb349c4624b71ec400abaf8ad1 Mon Sep 17 00:00:00 2001
   2 From: Georgi Djakov <gdjakov@mm-sol.com>
   3 Date: Mon, 10 Mar 2014 17:37:13 +0200
   4 Subject: [PATCH 048/182] mmc: sdhci-msm: Add platform_execute_tuning
   5  implementation
   6
   7 This patch adds implementation for platform specific tuning in order
   8 to support HS200 bus speed mode on Qualcomm SDHCI controller.
   9
  10 Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
  11 Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
  12 Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
  13 Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
  14 Signed-off-by: Chris Ball <chris@printf.net>
  15 ---
  16  drivers/mmc/host/sdhci-msm.c |  420 +++++++++++++++++++++++++++++++++++++++++-
  17  1 file changed, 415 insertions(+), 5 deletions(-)
  18
  19 --- a/drivers/mmc/host/sdhci-msm.c
  20 +++ b/drivers/mmc/host/sdhci-msm.c
  21 @@ -18,6 +18,8 @@
  22  #include <linux/of_device.h>
  23  #include <linux/regulator/consumer.h>
  24  #include <linux/delay.h>
  25 +#include <linux/mmc/mmc.h>
  26 +#include <linux/slab.h>
  27
  28  #include "sdhci-pltfm.h"
  29
  30 @@ -26,6 +28,42 @@
  31  #define CORE_POWER             0x0
  32  #define CORE_SW_RST            BIT(7)
  33
  34 +#define MAX_PHASES             16
  35 +#define CORE_DLL_LOCK          BIT(7)
  36 +#define CORE_DLL_EN            BIT(16)
  37 +#define CORE_CDR_EN            BIT(17)
  38 +#define CORE_CK_OUT_EN         BIT(18)
  39 +#define CORE_CDR_EXT_EN                BIT(19)
  40 +#define CORE_DLL_PDN           BIT(29)
  41 +#define CORE_DLL_RST           BIT(30)
  42 +#define CORE_DLL_CONFIG                0x100
  43 +#define CORE_DLL_STATUS                0x108
  44 +
  45 +#define CORE_VENDOR_SPEC       0x10c
  46 +#define CORE_CLK_PWRSAVE       BIT(1)
  47 +
  48 +#define CDR_SELEXT_SHIFT       20
  49 +#define CDR_SELEXT_MASK                (0xf << CDR_SELEXT_SHIFT)
  50 +#define CMUX_SHIFT_PHASE_SHIFT 24
  51 +#define CMUX_SHIFT_PHASE_MASK  (7 << CMUX_SHIFT_PHASE_SHIFT)
  52 +
  53 +static const u32 tuning_block_64[] = {
  54 +       0x00ff0fff, 0xccc3ccff, 0xffcc3cc3, 0xeffefffe,
  55 +       0xddffdfff, 0xfbfffbff, 0xff7fffbf, 0xefbdf777,
  56 +       0xf0fff0ff, 0x3cccfc0f, 0xcfcc33cc, 0xeeffefff,
  57 +       0xfdfffdff, 0xffbfffdf, 0xfff7ffbb, 0xde7b7ff7
  58 +};
  59 +
  60 +static const u32 tuning_block_128[] = {
  61 +       0xff00ffff, 0x0000ffff, 0xccccffff, 0xcccc33cc,
  62 +       0xcc3333cc, 0xffffcccc, 0xffffeeff, 0xffeeeeff,
  63 +       0xffddffff, 0xddddffff, 0xbbffffff, 0xbbffffff,
  64 +       0xffffffbb, 0xffffff77, 0x77ff7777, 0xffeeddbb,
  65 +       0x00ffffff, 0x00ffffff, 0xccffff00, 0xcc33cccc,
  66 +       0x3333cccc, 0xffcccccc, 0xffeeffff, 0xeeeeffff,
  67 +       0xddffffff, 0xddffffff, 0xffffffdd, 0xffffffbb,
  68 +       0xffffbbbb, 0xffff77ff, 0xff7777ff, 0xeeddbb77
  69 +};
  70
  71  struct sdhci_msm_host {
  72         struct platform_device *pdev;
  73 @@ -38,17 +76,389 @@ struct sdhci_msm_host {
  74  };
  75
  76  /* Platform specific tuning */
  77 -static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
  78 +static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
  79 +{
  80 +       u32 wait_cnt = 50;
  81 +       u8 ck_out_en;
  82 +       struct mmc_host *mmc = host->mmc;
  83 +
  84 +       /* Poll for CK_OUT_EN bit.  max. poll time = 50us */
  85 +       ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
  86 +                       CORE_CK_OUT_EN);
  87 +
  88 +       while (ck_out_en != poll) {
  89 +               if (--wait_cnt == 0) {
  90 +                       dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
  91 +                              mmc_hostname(mmc), poll);
  92 +                       return -ETIMEDOUT;
  93 +               }
  94 +               udelay(1);
  95 +
  96 +               ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
  97 +                               CORE_CK_OUT_EN);
  98 +       }
  99 +
 100 +       return 0;
 101 +}
 102 +
 103 +static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
 104 +{
 105 +       int rc;
 106 +       static const u8 grey_coded_phase_table[] = {
 107 +               0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
 108 +               0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
 109 +       };
 110 +       unsigned long flags;
 111 +       u32 config;
 112 +       struct mmc_host *mmc = host->mmc;
 113 +
 114 +       spin_lock_irqsave(&host->lock, flags);
 115 +
 116 +       config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 117 +       config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
 118 +       config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
 119 +       writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 120 +
 121 +       /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
 122 +       rc = msm_dll_poll_ck_out_en(host, 0);
 123 +       if (rc)
 124 +               goto err_out;
 125 +
 126 +       /*
 127 +        * Write the selected DLL clock output phase (0 ... 15)
 128 +        * to CDR_SELEXT bit field of DLL_CONFIG register.
 129 +        */
 130 +       config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 131 +       config &= ~CDR_SELEXT_MASK;
 132 +       config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
 133 +       writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 134 +
 135 +       /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */
 136 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
 137 +                       | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
 138 +
 139 +       /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
 140 +       rc = msm_dll_poll_ck_out_en(host, 1);
 141 +       if (rc)
 142 +               goto err_out;
 143 +
 144 +       config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 145 +       config |= CORE_CDR_EN;
 146 +       config &= ~CORE_CDR_EXT_EN;
 147 +       writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 148 +       goto out;
 149 +
 150 +err_out:
 151 +       dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
 152 +              mmc_hostname(mmc), phase);
 153 +out:
 154 +       spin_unlock_irqrestore(&host->lock, flags);
 155 +       return rc;
 156 +}
 157 +
 158 +/*
 159 + * Find out the greatest range of consecuitive selected
 160 + * DLL clock output phases that can be used as sampling
 161 + * setting for SD3.0 UHS-I card read operation (in SDR104
 162 + * timing mode) or for eMMC4.5 card read operation (in HS200
 163 + * timing mode).
 164 + * Select the 3/4 of the range and configure the DLL with the
 165 + * selected DLL clock output phase.
 166 + */
 167 +
 168 +static int msm_find_most_appropriate_phase(struct sdhci_host *host,
 169 +                                          u8 *phase_table, u8 total_phases)
 170 +{
 171 +       int ret;
 172 +       u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
 173 +       u8 phases_per_row[MAX_PHASES] = { 0 };
 174 +       int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
 175 +       int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
 176 +       bool phase_0_found = false, phase_15_found = false;
 177 +       struct mmc_host *mmc = host->mmc;
 178 +
 179 +       if (!total_phases || (total_phases > MAX_PHASES)) {
 180 +               dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
 181 +                      mmc_hostname(mmc), total_phases);
 182 +               return -EINVAL;
 183 +       }
 184 +
 185 +       for (cnt = 0; cnt < total_phases; cnt++) {
 186 +               ranges[row_index][col_index] = phase_table[cnt];
 187 +               phases_per_row[row_index] += 1;
 188 +               col_index++;
 189 +
 190 +               if ((cnt + 1) == total_phases) {
 191 +                       continue;
 192 +               /* check if next phase in phase_table is consecutive or not */
 193 +               } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
 194 +                       row_index++;
 195 +                       col_index = 0;
 196 +               }
 197 +       }
 198 +
 199 +       if (row_index >= MAX_PHASES)
 200 +               return -EINVAL;
 201 +
 202 +       /* Check if phase-0 is present in first valid window? */
 203 +       if (!ranges[0][0]) {
 204 +               phase_0_found = true;
 205 +               phase_0_raw_index = 0;
 206 +               /* Check if cycle exist between 2 valid windows */
 207 +               for (cnt = 1; cnt <= row_index; cnt++) {
 208 +                       if (phases_per_row[cnt]) {
 209 +                               for (i = 0; i < phases_per_row[cnt]; i++) {
 210 +                                       if (ranges[cnt][i] == 15) {
 211 +                                               phase_15_found = true;
 212 +                                               phase_15_raw_index = cnt;
 213 +                                               break;
 214 +                                       }
 215 +                               }
 216 +                       }
 217 +               }
 218 +       }
 219 +
 220 +       /* If 2 valid windows form cycle then merge them as single window */
 221 +       if (phase_0_found && phase_15_found) {
 222 +               /* number of phases in raw where phase 0 is present */
 223 +               u8 phases_0 = phases_per_row[phase_0_raw_index];
 224 +               /* number of phases in raw where phase 15 is present */
 225 +               u8 phases_15 = phases_per_row[phase_15_raw_index];
 226 +
 227 +               if (phases_0 + phases_15 >= MAX_PHASES)
 228 +                       /*
 229 +                        * If there are more than 1 phase windows then total
 230 +                        * number of phases in both the windows should not be
 231 +                        * more than or equal to MAX_PHASES.
 232 +                        */
 233 +                       return -EINVAL;
 234 +
 235 +               /* Merge 2 cyclic windows */
 236 +               i = phases_15;
 237 +               for (cnt = 0; cnt < phases_0; cnt++) {
 238 +                       ranges[phase_15_raw_index][i] =
 239 +                           ranges[phase_0_raw_index][cnt];
 240 +                       if (++i >= MAX_PHASES)
 241 +                               break;
 242 +               }
 243 +
 244 +               phases_per_row[phase_0_raw_index] = 0;
 245 +               phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
 246 +       }
 247 +
 248 +       for (cnt = 0; cnt <= row_index; cnt++) {
 249 +               if (phases_per_row[cnt] > curr_max) {
 250 +                       curr_max = phases_per_row[cnt];
 251 +                       selected_row_index = cnt;
 252 +               }
 253 +       }
 254 +
 255 +       i = (curr_max * 3) / 4;
 256 +       if (i)
 257 +               i--;
 258 +
 259 +       ret = ranges[selected_row_index][i];
 260 +
 261 +       if (ret >= MAX_PHASES) {
 262 +               ret = -EINVAL;
 263 +               dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
 264 +                      mmc_hostname(mmc), ret);
 265 +       }
 266 +
 267 +       return ret;
 268 +}
 269 +
 270 +static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
 271 +{
 272 +       u32 mclk_freq = 0, config;
 273 +
 274 +       /* Program the MCLK value to MCLK_FREQ bit field */
 275 +       if (host->clock <= 112000000)
 276 +               mclk_freq = 0;
 277 +       else if (host->clock <= 125000000)
 278 +               mclk_freq = 1;
 279 +       else if (host->clock <= 137000000)
 280 +               mclk_freq = 2;
 281 +       else if (host->clock <= 150000000)
 282 +               mclk_freq = 3;
 283 +       else if (host->clock <= 162000000)
 284 +               mclk_freq = 4;
 285 +       else if (host->clock <= 175000000)
 286 +               mclk_freq = 5;
 287 +       else if (host->clock <= 187000000)
 288 +               mclk_freq = 6;
 289 +       else if (host->clock <= 200000000)
 290 +               mclk_freq = 7;
 291 +
 292 +       config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 293 +       config &= ~CMUX_SHIFT_PHASE_MASK;
 294 +       config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
 295 +       writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 296 +}
 297 +
 298 +/* Initialize the DLL (Programmable Delay Line) */
 299 +static int msm_init_cm_dll(struct sdhci_host *host)
 300  {
 301 +       struct mmc_host *mmc = host->mmc;
 302 +       int wait_cnt = 50;
 303 +       unsigned long flags;
 304 +
 305 +       spin_lock_irqsave(&host->lock, flags);
 306 +
 307         /*
 308 -        * Tuning is required for SDR104, HS200 and HS400 cards and if the clock
 309 -        * frequency greater than 100MHz in those modes. The standard tuning
 310 -        * procedure should not be executed, but a custom implementation will be
 311 -        * added here instead.
 312 +        * Make sure that clock is always enabled when DLL
 313 +        * tuning is in progress. Keeping PWRSAVE ON may
 314 +        * turn off the clock.
 315          */
 316 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
 317 +                       & ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC);
 318 +
 319 +       /* Write 1 to DLL_RST bit of DLL_CONFIG register */
 320 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
 321 +                       | CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
 322 +
 323 +       /* Write 1 to DLL_PDN bit of DLL_CONFIG register */
 324 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
 325 +                       | CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
 326 +       msm_cm_dll_set_freq(host);
 327 +
 328 +       /* Write 0 to DLL_RST bit of DLL_CONFIG register */
 329 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
 330 +                       & ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
 331 +
 332 +       /* Write 0 to DLL_PDN bit of DLL_CONFIG register */
 333 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
 334 +                       & ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
 335 +
 336 +       /* Set DLL_EN bit to 1. */
 337 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
 338 +                       | CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG);
 339 +
 340 +       /* Set CK_OUT_EN bit to 1. */
 341 +       writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
 342 +                       | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
 343 +
 344 +       /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
 345 +       while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
 346 +                CORE_DLL_LOCK)) {
 347 +               /* max. wait for 50us sec for LOCK bit to be set */
 348 +               if (--wait_cnt == 0) {
 349 +                       dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
 350 +                              mmc_hostname(mmc));
 351 +                       spin_unlock_irqrestore(&host->lock, flags);
 352 +                       return -ETIMEDOUT;
 353 +               }
 354 +               udelay(1);
 355 +       }
 356 +
 357 +       spin_unlock_irqrestore(&host->lock, flags);
 358         return 0;
 359  }
 360
 361 +static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
 362 +{
 363 +       int tuning_seq_cnt = 3;
 364 +       u8 phase, *data_buf, tuned_phases[16], tuned_phase_cnt = 0;
 365 +       const u32 *tuning_block_pattern = tuning_block_64;
 366 +       int size = sizeof(tuning_block_64);     /* Pattern size in bytes */
 367 +       int rc;
 368 +       struct mmc_host *mmc = host->mmc;
 369 +       struct mmc_ios ios = host->mmc->ios;
 370 +
 371 +       /*
 372 +        * Tuning is required for SDR104, HS200 and HS400 cards and
 373 +        * if clock frequency is greater than 100MHz in these modes.
 374 +        */
 375 +       if (host->clock <= 100 * 1000 * 1000 ||
 376 +           !((ios.timing == MMC_TIMING_MMC_HS200) ||
 377 +             (ios.timing == MMC_TIMING_UHS_SDR104)))
 378 +               return 0;
 379 +
 380 +       if ((opcode == MMC_SEND_TUNING_BLOCK_HS200) &&
 381 +           (mmc->ios.bus_width == MMC_BUS_WIDTH_8)) {
 382 +               tuning_block_pattern = tuning_block_128;
 383 +               size = sizeof(tuning_block_128);
 384 +       }
 385 +
 386 +       data_buf = kmalloc(size, GFP_KERNEL);
 387 +       if (!data_buf)
 388 +               return -ENOMEM;
 389 +
 390 +retry:
 391 +       /* First of all reset the tuning block */
 392 +       rc = msm_init_cm_dll(host);
 393 +       if (rc)
 394 +               goto out;
 395 +
 396 +       phase = 0;
 397 +       do {
 398 +               struct mmc_command cmd = { 0 };
 399 +               struct mmc_data data = { 0 };
 400 +               struct mmc_request mrq = {
 401 +                       .cmd = &cmd,
 402 +                       .data = &data
 403 +               };
 404 +               struct scatterlist sg;
 405 +
 406 +               /* Set the phase in delay line hw block */
 407 +               rc = msm_config_cm_dll_phase(host, phase);
 408 +               if (rc)
 409 +                       goto out;
 410 +
 411 +               cmd.opcode = opcode;
 412 +               cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
 413 +
 414 +               data.blksz = size;
 415 +               data.blocks = 1;
 416 +               data.flags = MMC_DATA_READ;
 417 +               data.timeout_ns = NSEC_PER_SEC; /* 1 second */
 418 +
 419 +               data.sg = &sg;
 420 +               data.sg_len = 1;
 421 +               sg_init_one(&sg, data_buf, size);
 422 +               memset(data_buf, 0, size);
 423 +               mmc_wait_for_req(mmc, &mrq);
 424 +
 425 +               if (!cmd.error && !data.error &&
 426 +                   !memcmp(data_buf, tuning_block_pattern, size)) {
 427 +                       /* Tuning is successful at this tuning point */
 428 +                       tuned_phases[tuned_phase_cnt++] = phase;
 429 +                       dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
 430 +                                mmc_hostname(mmc), phase);
 431 +               }
 432 +       } while (++phase < ARRAY_SIZE(tuned_phases));
 433 +
 434 +       if (tuned_phase_cnt) {
 435 +               rc = msm_find_most_appropriate_phase(host, tuned_phases,
 436 +                                                    tuned_phase_cnt);
 437 +               if (rc < 0)
 438 +                       goto out;
 439 +               else
 440 +                       phase = rc;
 441 +
 442 +               /*
 443 +                * Finally set the selected phase in delay
 444 +                * line hw block.
 445 +                */
 446 +               rc = msm_config_cm_dll_phase(host, phase);
 447 +               if (rc)
 448 +                       goto out;
 449 +               dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
 450 +                        mmc_hostname(mmc), phase);
 451 +       } else {
 452 +               if (--tuning_seq_cnt)
 453 +                       goto retry;
 454 +               /* Tuning failed */
 455 +               dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
 456 +                      mmc_hostname(mmc));
 457 +               rc = -EIO;
 458 +       }
 459 +
 460 +out:
 461 +       kfree(data_buf);
 462 +       return rc;
 463 +}
 464 +
 465  static const struct of_device_id sdhci_msm_dt_match[] = {
 466         { .compatible = "qcom,sdhci-msm-v4" },
 467         {},