target/linux/ipq806x/patches/0006-clocksource-qcom-split-building-of-legacy-vs-multipl.patch

   1 From 085d4b834dfced8580aab74707e30699b63e7c36 Mon Sep 17 00:00:00 2001
   2 From: Kumar Gala <galak@codeaurora.org>
   3 Date: Wed, 29 Jan 2014 17:01:37 -0600
   4 Subject: [PATCH 006/182] clocksource: qcom: split building of legacy vs
   5  multiplatform support
   6
   7 The majority of the clocksource code for the Qualcomm platform is shared
   8 between newer (multiplatform) and older platforms.  However there is a bit
   9 of code that isn't, so only build it for the appropriate config.
  10
  11 Acked-by: Olof Johansson <olof@lixom.net>
  12 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  13 ---
  14  drivers/clocksource/qcom-timer.c |   23 ++++++++++++-----------
  15  1 file changed, 12 insertions(+), 11 deletions(-)
  16
  17 --- a/drivers/clocksource/qcom-timer.c
  18 +++ b/drivers/clocksource/qcom-timer.c
  19 @@ -106,15 +106,6 @@ static notrace cycle_t msm_read_timer_co
  20         return readl_relaxed(source_base + TIMER_COUNT_VAL);
  21  }
  22
  23 -static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
  24 -{
  25 -       /*
  26 -        * Shift timer count down by a constant due to unreliable lower bits
  27 -        * on some targets.
  28 -        */
  29 -       return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
  30 -}
  31 -
  32  static struct clocksource msm_clocksource = {
  33         .name   = "dg_timer",
  34         .rating = 300,
  35 @@ -228,7 +219,7 @@ err:
  36         sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
  37  }
  38
  39 -#ifdef CONFIG_OF
  40 +#ifdef CONFIG_ARCH_QCOM
  41  static void __init msm_dt_timer_init(struct device_node *np)
  42  {
  43         u32 freq;
  44 @@ -281,7 +272,7 @@ static void __init msm_dt_timer_init(str
  45  }
  46  CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
  47  CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
  48 -#endif
  49 +#else
  50
  51  static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
  52                                 u32 sts)
  53 @@ -301,6 +292,15 @@ static int __init msm_timer_map(phys_add
  54         return 0;
  55  }
  56
  57 +static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
  58 +{
  59 +       /*
  60 +        * Shift timer count down by a constant due to unreliable lower bits
  61 +        * on some targets.
  62 +        */
  63 +       return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
  64 +}
  65 +
  66  void __init msm7x01_timer_init(void)
  67  {
  68         struct clocksource *cs = &msm_clocksource;
  69 @@ -327,3 +327,4 @@ void __init qsd8x50_timer_init(void)
  70                 return;
  71         msm_timer_init(19200000 / 4, 32, 7, false);
  72  }
  73 +#endif