target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #include "qcom-ipq8065.dtsi"
   4 #include <dt-bindings/input/input.h>
   5
   6 / {
   7         model = "Askey RT4230W REV6";
   8         compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
   9
  10         memory@0 {
  11                 reg = <0x42000000 0x3e000000>;
  12                 device_type = "memory";
  13         };
  14
  15         aliases {
  16                 led-boot = &ledctrl3;
  17                 led-failsafe = &ledctrl1;
  18                 led-running = &ledctrl2;
  19                 led-upgrade = &ledctrl3;
  20         };
  21
  22         chosen {
  23                 bootargs = "rootfstype=squashfs noinitrd";
  24         };
  25
  26         keys {
  27                 compatible = "gpio-keys";
  28                 pinctrl-0 = <&button_pins>;
  29                 pinctrl-names = "default";
  30
  31                 reset {
  32                         label = "reset";
  33                         gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  34                         linux,code = <KEY_RESTART>;
  35                 };
  36
  37                 wps {
  38                         label = "wps";
  39                         gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
  40                         linux,code = <KEY_WPS_BUTTON>;
  41                 };
  42         };
  43
  44         leds {
  45                 compatible = "gpio-leds";
  46                 pinctrl-0 = <&led_pins>;
  47                 pinctrl-names = "default";
  48
  49                 ledctrl1: ledctrl1 {
  50                         label = "ledctrl1";
  51                         gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  52                 };
  53
  54                 ledctrl2: ledctrl2 {
  55                         label = "ledctrl2";
  56                         gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  57                 };
  58
  59                 ledctrl3: ledctrl3 {
  60                         label = "ledctrl3";
  61                         gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  62                 };
  63         };
  64 };
  65
  66 &qcom_pinmux {
  67         button_pins: button_pins {
  68                 mux {
  69                         pins = "gpio54", "gpio68";
  70                         function = "gpio";
  71                         drive-strength = <2>;
  72                         bias-pull-up;
  73                 };
  74         };
  75
  76         led_pins: led_pins {
  77                 mux {
  78                         pins = "gpio22", "gpio23", "gpio24";
  79                         function = "gpio";
  80                         drive-strength = <2>;
  81                         bias-pull-down;
  82                 };
  83         };
  84
  85         rgmii2_pins: rgmii2_pins {
  86                 mux {
  87                         pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
  88                                 "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
  89                         function = "rgmii2";
  90                         drive-strength = <8>;
  91                         bias-disable;
  92                 };
  93
  94                 tx {
  95                         pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
  96                         input-disable;
  97                 };
  98         };
  99
 100         spi_pins: spi_pins {
 101                 cs {
 102                         pins = "gpio20";
 103                         drive-strength = <12>;
 104                 };
 105         };
 106 };
 107
 108 &gsbi5 {
 109         qcom,mode = <GSBI_PROT_SPI>;
 110         status = "okay";
 111
 112         spi@1a280000 {
 113                 status = "okay";
 114
 115                 pinctrl-0 = <&spi_pins>;
 116                 pinctrl-names = "default";
 117
 118                 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
 119
 120                 flash@0 {
 121                         compatible = "everspin,mr25h256";
 122                         #address-cells = <1>;
 123                         #size-cells = <1>;
 124                         spi-max-frequency = <40000000>;
 125                         reg = <0>;
 126                 };
 127         };
 128 };
 129
 130 &nand {
 131         status = "okay";
 132
 133         pinctrl-0 = <&nand_pins>;
 134         pinctrl-names = "default";
 135
 136         nand@0 {
 137                 reg = <0>;
 138                 compatible = "qcom,nandcs";
 139
 140                 nand-ecc-strength = <4>;
 141                 nand-bus-width = <8>;
 142                 nand-ecc-step-size = <512>;
 143
 144                 partitions {
 145                         compatible = "fixed-partitions";
 146                         #address-cells = <1>;
 147                         #size-cells = <1>;
 148
 149                         partition@0 {
 150                                 label = "0:SBL1";
 151                                 reg = <0x0000000 0x0040000>;
 152                                 read-only;
 153                         };
 154                         partition@40000 {
 155                                 label = "0:MIBIB";
 156                                 reg = <0x0040000 0x0140000>;
 157                                 read-only;
 158                         };
 159                         partition@180000 {
 160                                 label = "0:SBL2";
 161                                 reg = <0x0180000 0x0140000>;
 162                                 read-only;
 163                         };
 164                         partition@2c0000 {
 165                                 label = "0:SBL3";
 166                                 reg = <0x02c0000 0x0280000>;
 167                                 read-only;
 168                         };
 169                         partition@540000 {
 170                                 label = "0:DDRCONFIG";
 171                                 reg = <0x0540000 0x0120000>;
 172                                 read-only;
 173                         };
 174                         partition@660000 {
 175                                 label = "0:SSD";
 176                                 reg = <0x0660000 0x0120000>;
 177                                 read-only;
 178                         };
 179                         partition@780000 {
 180                                 label = "0:TZ";
 181                                 reg = <0x0780000 0x0280000>;
 182                                 read-only;
 183                         };
 184                         partition@a00000 {
 185                                 label = "0:RPM";
 186                                 reg = <0x0a00000 0x0280000>;
 187                                 read-only;
 188                         };
 189                         partition@c80000 {
 190                                 label = "0:APPSBL";
 191                                 reg = <0x0c80000 0x0500000>;
 192                                 read-only;
 193                         };
 194                         partition@1180000 {
 195                                 label = "0:APPSBLENV";
 196                                 reg = <0x1180000 0x0080000>;
 197                         };
 198                         ART: partition@1200000 {
 199                                 label = "0:ART";
 200                                 reg = <0x1200000 0x0140000>;
 201                                 read-only;
 202                         };
 203                         partition@1340000 {
 204                                 label = "0:BOOTCONFIG";
 205                                 reg = <0x1340000 0x0060000>;
 206                                 read-only;
 207                         };
 208                         partition@13a0000 {
 209                                 label = "0:SBL2_1";
 210                                 reg = <0x13a0000 0x0140000>;
 211                                 read-only;
 212                         };
 213                         partition@14e0000 {
 214                                 label = "0:SBL3_1";
 215                                 reg = <0x14e0000 0x0280000>;
 216                                 read-only;
 217                         };
 218                         partition@1760000 {
 219                                 label = "0:DDRCONFIG_1";
 220                                 reg = <0x1760000 0x0120000>;
 221                                 read-only;
 222                         };
 223                         partition@1880000 {
 224                                 label = "0:SSD_1";
 225                                 reg = <0x1880000 0x0120000>;
 226                                 read-only;
 227                         };
 228                         partition@19a0000 {
 229                                 label = "0:TZ_1";
 230                                 reg = <0x19a0000 0x0280000>;
 231                                 read-only;
 232                         };
 233                         partition@1c20000 {
 234                                 label = "0:RPM_1";
 235                                 reg = <0x1c20000 0x0280000>;
 236                                 read-only;
 237                         };
 238                         partition@1ea0000 {
 239                                 label = "0:BOOTCONFIG1";
 240                                 reg = <0x1ea0000 0x0060000>;
 241                                 read-only;
 242                         };
 243                         partition@1f00000 {
 244                                 label = "0:APPSBL_1";
 245                                 reg = <0x1f00000 0x0500000>;
 246                                 read-only;
 247                         };
 248                         partition@2400000 {
 249                                 label = "ubi";
 250                                 reg = <0x2400000 0x1a000000>;
 251                         };
 252                 };
 253         };
 254 };
 255
 256 &mdio0 {
 257         status = "okay";
 258
 259         pinctrl-0 = <&mdio0_pins>;
 260         pinctrl-names = "default";
 261
 262         phy0: ethernet-phy@0 {
 263                 reg = <0x0>;
 264                 qca,ar8327-initvals = <
 265                         0x00004 0x7600000   /* PAD0_MODE */
 266                         0x00008 0x1000000   /* PAD5_MODE */
 267                         0x0000c 0x80        /* PAD6_MODE */
 268                         0x000e4 0xaa545     /* MAC_POWER_SEL */
 269                         0x000e0 0xc74164de  /* SGMII_CTRL */
 270                         0x0007c 0x4e        /* PORT0_STATUS */
 271                         0x00094 0x4e        /* PORT6_STATUS */
 272                         0x00050 0xcf02cf02  /* LED_CTRL_0 */
 273                         0x00054 0xc832c832  /* LED_CTRL_1 */
 274                         >;
 275         };
 276 };
 277
 278 &gmac0 {
 279         status = "okay";
 280         phy-mode = "rgmii";
 281         qcom,id = <0>;
 282
 283         nvmem-cells = <&macaddr_ART_0>;
 284         nvmem-cell-names = "mac-address";
 285
 286         pinctrl-0 = <&rgmii2_pins>;
 287         pinctrl-names = "default";
 288
 289         fixed-link {
 290                 speed = <1000>;
 291                 full-duplex;
 292         };
 293 };
 294
 295 &gmac1 {
 296         status = "okay";
 297         phy-mode = "sgmii";
 298         qcom,id = <1>;
 299
 300         nvmem-cells = <&macaddr_ART_6>;
 301         nvmem-cell-names = "mac-address";
 302
 303         fixed-link {
 304                 speed = <1000>;
 305                 full-duplex;
 306         };
 307 };
 308
 309 &adm_dma {
 310         status = "okay";
 311 };
 312
 313 &usb3_0 {
 314         status = "okay";
 315 };
 316
 317 &usb3_1 {
 318         status = "okay";
 319 };
 320
 321 &pcie0 {
 322         status = "okay";
 323         reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
 324         pinctrl-0 = <&pcie0_pins>;
 325         pinctrl-names = "default";
 326 };
 327
 328 &pcie1 {
 329         status = "okay";
 330         reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
 331         pinctrl-0 = <&pcie1_pins>;
 332         pinctrl-names = "default";
 333         max-link-speed = <1>;
 334 };
 335
 336 &ART {
 337         compatible = "nvmem-cells";
 338         #address-cells = <1>;
 339         #size-cells = <1>;
 340
 341         macaddr_ART_0: macaddr@0 {
 342                 reg = <0x0 0x6>;
 343         };
 344
 345         macaddr_ART_6: macaddr@6 {
 346                 reg = <0x6 0x6>;
 347         };
 348 };