ipq806x: Fix nighthawk R7800/XR450/XR500 wan MAC
[openwrt/staging/nbd.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8065-nighthawk.dtsi
1 #include "qcom-ipq8065-smb208.dtsi"
2
3 #include <dt-bindings/input/input.h>
4
5 / {
6 memory@0 {
7 reg = <0x42000000 0x1e000000>;
8 device_type = "memory";
9 };
10
11 reserved-memory {
12 rsvd@5fe00000 {
13 reg = <0x5fe00000 0x200000>;
14 reusable;
15 };
16
17 ramoops@42100000 {
18 compatible = "ramoops";
19 reg = <0x42100000 0x40000>;
20 record-size = <0x4000>;
21 console-size = <0x4000>;
22 ftrace-size = <0x4000>;
23 pmsg-size = <0x4000>;
24 };
25 };
26
27 aliases {
28 label-mac-device = &gmac2;
29
30 led-boot = &power_white;
31 led-failsafe = &power_amber;
32 led-running = &power_white;
33 led-upgrade = &power_amber;
34
35 mdio-gpio0 = &mdio0;
36 };
37
38 keys {
39 compatible = "gpio-keys";
40 pinctrl-0 = <&button_pins>;
41 pinctrl-names = "default";
42
43 wifi {
44 label = "wifi";
45 gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
46 linux,code = <KEY_RFKILL>;
47 debounce-interval = <60>;
48 wakeup-source;
49 };
50
51 reset {
52 label = "reset";
53 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
54 linux,code = <KEY_RESTART>;
55 debounce-interval = <60>;
56 wakeup-source;
57 };
58
59 wps {
60 label = "wps";
61 gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
62 linux,code = <KEY_WPS_BUTTON>;
63 debounce-interval = <60>;
64 wakeup-source;
65 };
66 };
67
68 leds: leds {
69 compatible = "gpio-leds";
70 pinctrl-0 = <&led_pins>;
71 pinctrl-names = "default";
72
73 power_white: power_white {
74 label = "white:power";
75 gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
76 default-state = "keep";
77 };
78
79 power_amber: power_amber {
80 label = "amber:power";
81 gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
82 };
83
84 wan_white {
85 label = "white:wan";
86 gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
87 };
88
89 wan_amber {
90 label = "amber:wan";
91 gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
92 };
93
94 wifi {
95 label = "white:wifi";
96 gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
97 };
98
99 wps {
100 label = "white:wps";
101 gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
102 };
103 };
104 };
105
106 &qcom_pinmux {
107 button_pins: button_pins {
108 mux {
109 pins = "gpio6", "gpio54", "gpio65";
110 function = "gpio";
111 drive-strength = <2>;
112 bias-pull-up;
113 };
114 };
115
116 led_pins: led_pins {
117 mux {
118 pins = "gpio7", "gpio8", "gpio9",
119 "gpio22", "gpio23", "gpio24",
120 "gpio26", "gpio53", "gpio64";
121 function = "gpio";
122 drive-strength = <2>;
123 bias-pull-down;
124 };
125 };
126
127 mdio0_pins: mdio0-pins {
128 clk {
129 pins = "gpio1";
130 input-disable;
131 };
132 };
133
134 rgmii2_pins: rgmii2-pins {
135 tx {
136 pins = "gpio27", "gpio28", "gpio29",
137 "gpio30", "gpio31", "gpio32";
138 input-disable;
139 };
140 };
141
142 spi_pins: spi_pins {
143 mux {
144 pins = "gpio18", "gpio19", "gpio21";
145 function = "gsbi5";
146 bias-pull-down;
147 };
148
149 data {
150 pins = "gpio18", "gpio19";
151 drive-strength = <10>;
152 };
153
154 cs {
155 pins = "gpio20";
156 drive-strength = <10>;
157 bias-pull-up;
158 };
159
160 clk {
161 pins = "gpio21";
162 drive-strength = <12>;
163 };
164 };
165
166 spi6_pins: spi6_pins {
167 mux {
168 pins = "gpio55", "gpio56", "gpio58";
169 function = "gsbi6";
170 bias-pull-down;
171 };
172
173 mosi {
174 pins = "gpio55";
175 drive-strength = <12>;
176 };
177
178 miso {
179 pins = "gpio56";
180 drive-strength = <14>;
181 };
182
183 cs {
184 pins = "gpio57";
185 drive-strength = <12>;
186 bias-pull-up;
187 };
188
189 clk {
190 pins = "gpio58";
191 drive-strength = <12>;
192 };
193
194 reset {
195 pins = "gpio33";
196 drive-strength = <10>;
197 bias-pull-down;
198 output-high;
199 };
200 };
201
202 usb0_pwr_en_pins: usb0_pwr_en_pins {
203 mux {
204 pins = "gpio15";
205 function = "gpio";
206 drive-strength = <12>;
207 bias-pull-down;
208 output-high;
209 };
210 };
211
212 usb1_pwr_en_pins: usb1_pwr_en_pins {
213 mux {
214 pins = "gpio16", "gpio68";
215 function = "gpio";
216 drive-strength = <12>;
217 bias-pull-down;
218 output-high;
219 };
220 };
221 };
222
223 &nand {
224 status = "okay";
225
226 nand@0 {
227 reg = <0>;
228 compatible = "qcom,nandcs";
229
230 nand-ecc-strength = <4>;
231 nand-bus-width = <8>;
232 nand-ecc-step-size = <512>;
233
234 nand-is-boot-medium;
235 qcom,boot-partitions = <0x0 0x1180000>;
236
237 partitions: partitions {
238 compatible = "fixed-partitions";
239 #address-cells = <1>;
240 #size-cells = <1>;
241
242 partition@0 {
243 label = "qcadata";
244 reg = <0x0000000 0x0c80000>;
245 read-only;
246 };
247
248 partition@c80000 {
249 label = "APPSBL";
250 reg = <0x0c80000 0x0500000>;
251 read-only;
252 };
253
254 partition@1180000 {
255 label = "APPSBLENV";
256 reg = <0x1180000 0x0080000>;
257 read-only;
258 };
259
260 art: partition@1200000 {
261 label = "art";
262 reg = <0x1200000 0x0140000>;
263 read-only;
264
265 nvmem-layout {
266 compatible = "fixed-layout";
267 #address-cells = <1>;
268 #size-cells = <1>;
269
270 macaddr_art_0: macaddr@0 {
271 reg = <0x0 0x6>;
272 };
273
274 macaddr_art_6: macaddr@6 {
275 compatible = "mac-base";
276 reg = <0x6 0x6>;
277 #nvmem-cell-cells = <1>;
278 };
279
280 macaddr_art_c: macaddr@c {
281 reg = <0xc 0x6>;
282 };
283
284 precal_art_1000: precal@1000 {
285 reg = <0x1000 0x2f20>;
286 };
287
288 precal_art_5000: precal@5000 {
289 reg = <0x5000 0x2f20>;
290 };
291 };
292 };
293
294 partition@1340000 {
295 label = "artbak";
296 reg = <0x1340000 0x0140000>;
297 read-only;
298 };
299
300 partition@1480000 {
301 label = "kernel";
302 reg = <0x1480000 0x0400000>;
303 };
304 };
305 };
306 };
307
308 &mdio0 {
309 status = "okay";
310
311 pinctrl-0 = <&mdio0_pins>;
312 pinctrl-names = "default";
313
314 switch@10 {
315 compatible = "qca,qca8337";
316 #address-cells = <1>;
317 #size-cells = <0>;
318 reg = <0x10>;
319
320 ports {
321 #address-cells = <1>;
322 #size-cells = <0>;
323
324 port@0 {
325 reg = <0>;
326 label = "cpu";
327 ethernet = <&gmac1>;
328 phy-mode = "rgmii";
329 tx-internal-delay-ps = <1000>;
330 rx-internal-delay-ps = <1000>;
331
332 fixed-link {
333 speed = <1000>;
334 full-duplex;
335 };
336 };
337
338 port@1 {
339 reg = <1>;
340 label = "lan4";
341 phy-mode = "internal";
342 phy-handle = <&phy_port1>;
343 };
344
345 port@2 {
346 reg = <2>;
347 label = "lan3";
348 phy-mode = "internal";
349 phy-handle = <&phy_port2>;
350 };
351
352 port@3 {
353 reg = <3>;
354 label = "lan2";
355 phy-mode = "internal";
356 phy-handle = <&phy_port3>;
357 };
358
359 port@4 {
360 reg = <4>;
361 label = "lan1";
362 phy-mode = "internal";
363 phy-handle = <&phy_port4>;
364 };
365
366 port@5 {
367 reg = <5>;
368 label = "wan";
369 phy-mode = "internal";
370 phy-handle = <&phy_port5>;
371 };
372
373 port@6 {
374 reg = <6>;
375 label = "cpu";
376 ethernet = <&gmac2>;
377 phy-mode = "sgmii";
378 qca,sgmii-enable-pll;
379
380 fixed-link {
381 speed = <1000>;
382 full-duplex;
383 };
384 };
385 };
386
387 mdio {
388 #address-cells = <1>;
389 #size-cells = <0>;
390
391 phy_port1: phy@0 {
392 reg = <0>;
393 };
394
395 phy_port2: phy@1 {
396 reg = <1>;
397 };
398
399 phy_port3: phy@2 {
400 reg = <2>;
401 };
402
403 phy_port4: phy@3 {
404 reg = <3>;
405 };
406
407 phy_port5: phy@4 {
408 reg = <4>;
409 };
410 };
411 };
412 };
413
414 &gmac1 {
415 status = "okay";
416
417 phy-mode = "rgmii";
418 qcom,id = <1>;
419 qcom,phy_mdio_addr = <4>;
420 qcom,poll_required = <0>;
421 qcom,rgmii_delay = <1>;
422 qcom,phy_mii_type = <0>;
423 qcom,emulation = <0>;
424 qcom,irq = <255>;
425 mdiobus = <&mdio0>;
426
427 pinctrl-0 = <&rgmii2_pins>;
428 pinctrl-names = "default";
429
430 nvmem-cells = <&macaddr_art_6 0>;
431 nvmem-cell-names = "mac-address";
432
433 fixed-link {
434 speed = <1000>;
435 full-duplex;
436 };
437 };
438
439 &gmac2 {
440 status = "okay";
441
442 phy-mode = "sgmii";
443 qcom,id = <2>;
444 qcom,phy_mdio_addr = <0>; /* none */
445 qcom,poll_required = <0>; /* no polling */
446 qcom,rgmii_delay = <0>;
447 qcom,phy_mii_type = <1>;
448 qcom,emulation = <0>;
449 qcom,irq = <258>;
450 mdiobus = <&mdio0>;
451
452 nvmem-cells = <&macaddr_art_0>;
453 nvmem-cell-names = "mac-address";
454
455 fixed-link {
456 speed = <1000>;
457 full-duplex;
458 };
459 };
460
461 &adm_dma {
462 status = "okay";
463 };
464
465 &sata_phy {
466 status = "okay";
467 };
468
469 &sata {
470 status = "okay";
471 };
472
473 &hs_phy_0 {
474 status = "okay";
475 };
476
477 &ss_phy_0 {
478 status = "okay";
479 };
480
481 &usb3_0 {
482 status = "okay";
483
484 pinctrl-0 = <&usb0_pwr_en_pins>;
485 pinctrl-names = "default";
486 };
487
488 &hs_phy_1 {
489 status = "okay";
490 };
491
492 &ss_phy_1 {
493 status = "okay";
494 };
495
496 &usb3_1 {
497 status = "okay";
498
499 pinctrl-0 = <&usb1_pwr_en_pins>;
500 pinctrl-names = "default";
501 };
502
503 &pcie0 {
504 status = "okay";
505
506 bridge@0,0 {
507 reg = <0x00000000 0 0 0 0>;
508 #address-cells = <3>;
509 #size-cells = <2>;
510 ranges;
511
512 wifi0: wifi@1,0 {
513 compatible = "pci168c,0046";
514 reg = <0x00010000 0 0 0 0>;
515 };
516 };
517 };
518
519 &pcie1 {
520 status = "okay";
521
522 max-link-speed = <1>;
523
524 bridge@0,0 {
525 reg = <0x00000000 0 0 0 0>;
526 #address-cells = <3>;
527 #size-cells = <2>;
528 ranges;
529
530 wifi1: wifi@1,0 {
531 compatible = "pci168c,0046";
532 reg = <0x00010000 0 0 0 0>;
533 };
534 };
535 };