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ipq40xx: use patches that were sent upstream
[openwrt/staging/lynxis.git] / target / linux / ipq40xx / patches-4.14 / 078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch
1 From 187519403273f0599c848d20eca9acce8b1807a5 Mon Sep 17 00:00:00 2001
2 From: Sricharan R <sricharan@codeaurora.org>
3 Date: Fri, 25 May 2018 11:41:12 +0530
4 Subject: [PATCH] ARM: dts: ipq4019: Add a few peripheral nodes
5
6 Now with the driver updates for some peripherals being there,
7 add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
8 peripheral support.
9
10 Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
11 Signed-off-by: Sricharan R <sricharan@codeaurora.org>
12 Signed-off-by: Andy Gross <andy.gross@linaro.org>
13 ---
14 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
15 arch/arm/boot/dts/qcom-ipq4019.dtsi | 156 ++++++++++++++++++++++++--
16 2 files changed, 146 insertions(+), 12 deletions(-)
17
18 diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
19 index ef8d8c88ed7b..418f9a022336 100644
20 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
21 +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
22 @@ -69,7 +69,7 @@
23 status = "ok";
24 };
25
26 - spi_0: spi@78b5000 {
27 + spi@78b5000 {
28 pinctrl-0 = <&spi_0_pins>;
29 pinctrl-names = "default";
30 status = "ok";
31 diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
32 index 2efc8a2d41a7..737097e9fb4f 100644
33 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
34 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
35 @@ -40,8 +40,10 @@
36 };
37
38 aliases {
39 - spi0 = &spi_0;
40 - i2c0 = &i2c_0;
41 + spi0 = &blsp1_spi1;
42 + spi1 = &blsp1_spi2;
43 + i2c0 = &blsp1_i2c3;
44 + i2c1 = &blsp1_i2c4;
45 };
46
47 cpus {
48 @@ -120,6 +122,12 @@
49 };
50 };
51
52 + firmware {
53 + scm {
54 + compatible = "qcom,scm-ipq4019";
55 + };
56 + };
57 +
58 timer {
59 compatible = "arm,armv7-timer";
60 interrupts = <1 2 0xf08>,
61 @@ -165,13 +173,13 @@
62 #gpio-cells = <2>;
63 interrupt-controller;
64 #interrupt-cells = <2>;
65 - interrupts = <0 208 0>;
66 + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
67 };
68
69 blsp_dma: dma@7884000 {
70 compatible = "qcom,bam-v1.7.0";
71 reg = <0x07884000 0x23000>;
72 - interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
73 + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
75 clock-names = "bam_clk";
76 #dma-cells = <1>;
77 @@ -179,7 +187,7 @@
78 status = "disabled";
79 };
80
81 - spi_0: spi@78b5000 {
82 + blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
83 compatible = "qcom,spi-qup-v2.2.1";
84 reg = <0x78b5000 0x600>;
85 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
86 @@ -188,10 +196,26 @@
87 clock-names = "core", "iface";
88 #address-cells = <1>;
89 #size-cells = <0>;
90 + dmas = <&blsp_dma 5>, <&blsp_dma 4>;
91 + dma-names = "rx", "tx";
92 + status = "disabled";
93 + };
94 +
95 + blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
96 + compatible = "qcom,spi-qup-v2.2.1";
97 + reg = <0x78b6000 0x600>;
98 + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
99 + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
100 + <&gcc GCC_BLSP1_AHB_CLK>;
101 + clock-names = "core", "iface";
102 + #address-cells = <1>;
103 + #size-cells = <0>;
104 + dmas = <&blsp_dma 7>, <&blsp_dma 6>;
105 + dma-names = "rx", "tx";
106 status = "disabled";
107 };
108
109 - i2c_0: i2c@78b7000 {
110 + blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
111 compatible = "qcom,i2c-qup-v2.2.1";
112 reg = <0x78b7000 0x600>;
113 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
114 @@ -200,14 +224,29 @@
115 clock-names = "iface", "core";
116 #address-cells = <1>;
117 #size-cells = <0>;
118 + dmas = <&blsp_dma 9>, <&blsp_dma 8>;
119 + dma-names = "rx", "tx";
120 status = "disabled";
121 };
122
123 + blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
124 + compatible = "qcom,i2c-qup-v2.2.1";
125 + reg = <0x78b8000 0x600>;
126 + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
127 + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
128 + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
129 + clock-names = "iface", "core";
130 + #address-cells = <1>;
131 + #size-cells = <0>;
132 + dmas = <&blsp_dma 11>, <&blsp_dma 10>;
133 + dma-names = "rx", "tx";
134 + status = "disabled";
135 + };
136
137 cryptobam: dma@8e04000 {
138 compatible = "qcom,bam-v1.7.0";
139 reg = <0x08e04000 0x20000>;
140 - interrupts = <GIC_SPI 207 0>;
141 + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
143 clock-names = "bam_clk";
144 #dma-cells = <1>;
145 @@ -275,7 +314,7 @@
146 blsp1_uart1: serial@78af000 {
147 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
148 reg = <0x78af000 0x200>;
149 - interrupts = <0 107 0>;
150 + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
151 status = "disabled";
152 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
153 <&gcc GCC_BLSP1_AHB_CLK>;
154 @@ -287,7 +326,7 @@
155 serial@78b0000 {
156 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
157 reg = <0x78b0000 0x200>;
158 - interrupts = <0 108 0>;
159 + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
160 status = "disabled";
161 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
162 <&gcc GCC_BLSP1_AHB_CLK>;
163 @@ -309,6 +348,101 @@
164 reg = <0x4ab000 0x4>;
165 };
166
167 + pcie0: pci@40000000 {
168 + compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
169 + reg = <0x40000000 0xf1d
170 + 0x40000f20 0xa8
171 + 0x80000 0x2000
172 + 0x40100000 0x1000>;
173 + reg-names = "dbi", "elbi", "parf", "config";
174 + device_type = "pci";
175 + linux,pci-domain = <0>;
176 + bus-range = <0x00 0xff>;
177 + num-lanes = <1>;
178 + #address-cells = <3>;
179 + #size-cells = <2>;
180 +
181 + ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
182 + 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
183 +
184 + interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
185 + interrupt-names = "msi";
186 + #interrupt-cells = <1>;
187 + interrupt-map-mask = <0 0 0 0x7>;
188 + interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
189 + <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
190 + <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
191 + <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
192 + clocks = <&gcc GCC_PCIE_AHB_CLK>,
193 + <&gcc GCC_PCIE_AXI_M_CLK>,
194 + <&gcc GCC_PCIE_AXI_S_CLK>;
195 + clock-names = "aux",
196 + "master_bus",
197 + "slave_bus";
198 +
199 + resets = <&gcc PCIE_AXI_M_ARES>,
200 + <&gcc PCIE_AXI_S_ARES>,
201 + <&gcc PCIE_PIPE_ARES>,
202 + <&gcc PCIE_AXI_M_VMIDMT_ARES>,
203 + <&gcc PCIE_AXI_S_XPU_ARES>,
204 + <&gcc PCIE_PARF_XPU_ARES>,
205 + <&gcc PCIE_PHY_ARES>,
206 + <&gcc PCIE_AXI_M_STICKY_ARES>,
207 + <&gcc PCIE_PIPE_STICKY_ARES>,
208 + <&gcc PCIE_PWR_ARES>,
209 + <&gcc PCIE_AHB_ARES>,
210 + <&gcc PCIE_PHY_AHB_ARES>;
211 + reset-names = "axi_m",
212 + "axi_s",
213 + "pipe",
214 + "axi_m_vmid",
215 + "axi_s_xpu",
216 + "parf",
217 + "phy",
218 + "axi_m_sticky",
219 + "pipe_sticky",
220 + "pwr",
221 + "ahb",
222 + "phy_ahb";
223 +
224 + status = "disabled";
225 + };
226 +
227 + qpic_bam: dma@7984000 {
228 + compatible = "qcom,bam-v1.7.0";
229 + reg = <0x7984000 0x1a000>;
230 + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
231 + clocks = <&gcc GCC_QPIC_CLK>;
232 + clock-names = "bam_clk";
233 + #dma-cells = <1>;
234 + qcom,ee = <0>;
235 + status = "disabled";
236 + };
237 +
238 + nand: qpic-nand@79b0000 {
239 + compatible = "qcom,ipq4019-nand";
240 + reg = <0x79b0000 0x1000>;
241 + #address-cells = <1>;
242 + #size-cells = <0>;
243 + clocks = <&gcc GCC_QPIC_CLK>,
244 + <&gcc GCC_QPIC_AHB_CLK>;
245 + clock-names = "core", "aon";
246 +
247 + dmas = <&qpic_bam 0>,
248 + <&qpic_bam 1>,
249 + <&qpic_bam 2>;
250 + dma-names = "tx", "rx", "cmd";
251 + status = "disabled";
252 +
253 + nand@0 {
254 + reg = <0>;
255 +
256 + nand-ecc-strength = <4>;
257 + nand-ecc-step-size = <512>;
258 + nand-bus-width = <8>;
259 + };
260 + };
261 +
262 wifi0: wifi@a000000 {
263 compatible = "qcom,ipq4019-wifi";
264 reg = <0xa000000 0x200000>;
265 @@ -342,7 +476,7 @@
266 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
267 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
268 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
269 - <GIC_SPI 168 IRQ_TYPE_NONE>;
270 + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
271 interrupt-names = "msi0", "msi1", "msi2", "msi3",
272 "msi4", "msi5", "msi6", "msi7",
273 "msi8", "msi9", "msi10", "msi11",
274 @@ -384,7 +518,7 @@
275 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
276 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
277 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
278 - <GIC_SPI 169 IRQ_TYPE_NONE>;
279 + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
280 interrupt-names = "msi0", "msi1", "msi2", "msi3",
281 "msi4", "msi5", "msi6", "msi7",
282 "msi8", "msi9", "msi10", "msi11",
283 --
284 2.11.0
285
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