target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4019-r619ac.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "qcom-ipq4019.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/soc/qcom,tcsr.h>
   7 #include <dt-bindings/leds/common.h>
   8
   9 / {
  10         chosen {
  11                 bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
  12         };
  13
  14         aliases {
  15                 led-boot = &led_sys;
  16                 led-failsafe = &led_sys;
  17                 led-running = &led_sys;
  18                 led-upgrade = &led_sys;
  19         };
  20
  21         soc {
  22                 tcsr@1949000 {
  23                         compatible = "qcom,tcsr";
  24                         reg = <0x1949000 0x100>;
  25                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  26                 };
  27
  28                 tcsr@194b000 {
  29                         compatible = "qcom,tcsr";
  30                         reg = <0x194b000 0x100>;
  31                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  32                 };
  33
  34                 ess_tcsr@1953000 {
  35                         compatible = "qcom,tcsr";
  36                         reg = <0x1953000 0x1000>;
  37                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  38                 };
  39
  40                 tcsr@1957000 {
  41                         compatible = "qcom,tcsr";
  42                         reg = <0x1957000 0x100>;
  43                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  44                 };
  45         };
  46
  47         leds {
  48                 compatible = "gpio-leds";
  49
  50                 led_sys: led-0 {
  51                         gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
  52                         color = <LED_COLOR_ID_BLUE>;
  53                         function = LED_FUNCTION_POWER;
  54                 };
  55
  56                 led-1 {
  57                         gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
  58                         linux,default-trigger = "phy0tpt";
  59                         color = <LED_COLOR_ID_BLUE>;
  60                         function = LED_FUNCTION_WLAN;
  61                         function-enumerator = <0>;
  62                 };
  63
  64                 led-2 {
  65                         gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
  66                         linux,default-trigger = "phy1tpt";
  67                         color = <LED_COLOR_ID_BLUE>;
  68                         function = LED_FUNCTION_WLAN;
  69                         function-enumerator = <1>;
  70                 };
  71         };
  72
  73         keys {
  74                 compatible = "gpio-keys";
  75
  76                 reset {
  77                         label = "reset";
  78                         gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  79                         linux,code = <KEY_RESTART>;
  80                 };
  81         };
  82 };
  83
  84 &watchdog {
  85         status = "okay";
  86 };
  87
  88 &prng {
  89         status = "okay";
  90 };
  91
  92 &crypto {
  93         status = "okay";
  94 };
  95
  96 &blsp_dma {
  97         status = "okay";
  98 };
  99
 100 &blsp1_spi1 {
 101         status = "okay";
 102
 103         flash@0 {
 104                 reg = <0>;
 105                 compatible = "jedec,spi-nor";
 106                 spi-max-frequency = <24000000>;
 107
 108                 partitions {
 109                         compatible = "fixed-partitions";
 110                         #address-cells = <1>;
 111                         #size-cells = <1>;
 112
 113                         partition@0 {
 114                                 label = "SBL1";
 115                                 reg = <0x0 0x40000>;
 116                                 read-only;
 117                         };
 118
 119                         partition@40000 {
 120                                 label = "MIBIB";
 121                                 reg = <0x40000 0x20000>;
 122                                 read-only;
 123                         };
 124
 125                         partition@60000 {
 126                                 label = "QSEE";
 127                                 reg = <0x60000 0x60000>;
 128                                 read-only;
 129                         };
 130
 131                         partition@c0000 {
 132                                 label = "CDT";
 133                                 reg = <0xc0000 0x10000>;
 134                                 read-only;
 135                         };
 136
 137                         partition@d0000 {
 138                                 label = "DDRPARAMS";
 139                                 reg = <0xd0000 0x10000>;
 140                                 read-only;
 141                         };
 142
 143                         partition@e0000 {
 144                                 label = "APPSBLENV";
 145                                 reg = <0xe0000 0x10000>;
 146                                 read-only;
 147                         };
 148
 149                         partition@f0000 {
 150                                 label = "APPSBL";
 151                                 reg = <0xf0000 0x80000>;
 152                                 read-only;
 153                         };
 154
 155                         partition@170000 {
 156                                 label = "ART";
 157                                 reg = <0x170000 0x10000>;
 158                                 read-only;
 159
 160                                 nvmem-layout {
 161                                         compatible = "fixed-layout";
 162                                         #address-cells = <1>;
 163                                         #size-cells = <1>;
 164
 165                                         precal_art_1000: precal@1000 {
 166                                                 reg = <0x1000 0x2f20>;
 167                                         };
 168
 169                                         precal_art_5000: precal@5000 {
 170                                                 reg = <0x5000 0x2f20>;
 171                                         };
 172                                 };
 173                         };
 174                 };
 175         };
 176 };
 177
 178 &nand {
 179         status = "okay";
 180
 181         nand@0 {
 182                 partitions {
 183                         compatible = "fixed-partitions";
 184                         #address-cells = <1>;
 185                         #size-cells = <1>;
 186
 187                         nand_rootfs: partition@0 {
 188                                 label = "ubi";
 189                                 /* reg defined in 64M/128M variant dts. */
 190                         };
 191                 };
 192         };
 193 };
 194
 195 &blsp1_uart1 {
 196         pinctrl-0 = <&serial_0_pins>;
 197         pinctrl-names = "default";
 198         status = "okay";
 199 };
 200
 201 &cryptobam {
 202         status = "okay";
 203 };
 204
 205 &pcie0 {
 206         status = "okay";
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&pcie_pins>;
 209         perst-gpio = <&tlmm 4 GPIO_ACTIVE_LOW>;
 210         wake-gpio = <&tlmm 40 GPIO_ACTIVE_HIGH>;
 211
 212         /* Free slot for use */
 213         bridge@0,0 {
 214                 reg = <0x00000000 0 0 0 0>;
 215                 #address-cells = <3>;
 216                 #size-cells = <2>;
 217                 ranges;
 218         };
 219 };
 220
 221 &qpic_bam {
 222         status = "okay";
 223 };
 224
 225 &sdhci {
 226         pinctrl-0 = <&sd_0_pins>;
 227         pinctrl-names = "default";
 228         vqmmc-supply = <&vqmmc>;
 229         status = "okay";
 230 };
 231
 232 &tlmm {
 233         pcie_pins: pcie_pinmux {
 234                 mux {
 235                         pins = "gpio2";
 236                         function = "gpio";
 237                         output-low;
 238                         bias-pull-down;
 239                 };
 240         };
 241
 242         mdio_pins: mdio_pinmux {
 243                 mux_1 {
 244                         pins = "gpio6";
 245                         function = "mdio";
 246                         bias-pull-up;
 247                 };
 248
 249                 mux_2 {
 250                         pins = "gpio7";
 251                         function = "mdc";
 252                         bias-pull-up;
 253                 };
 254         };
 255
 256         sd_0_pins: sd_0_pinmux {
 257                 mux_1 {
 258                         pins = "gpio23", "gpio24", "gpio25", "gpio26", "gpio28";
 259                         function = "sdio";
 260                         drive-strength = <10>;
 261                 };
 262
 263                 mux_2 {
 264                         pins = "gpio27";
 265                         function = "sdio";
 266                         drive-strength = <16>;
 267                 };
 268         };
 269
 270         serial_0_pins: serial0-pinmux {
 271                 mux {
 272                         pins = "gpio16", "gpio17";
 273                         function = "blsp_uart0";
 274                         bias-disable;
 275                 };
 276         };
 277 };
 278
 279 &mdio {
 280         status = "okay";
 281         pinctrl-0 = <&mdio_pins>;
 282         pinctrl-names = "default";
 283 };
 284
 285 &ethphy0 {
 286         qcom,single-led-1000;
 287         qcom,single-led-100;
 288         qcom,single-led-10;
 289 };
 290
 291 &ethphy1 {
 292         qcom,single-led-1000;
 293         qcom,single-led-100;
 294         qcom,single-led-10;
 295 };
 296
 297 &ethphy2 {
 298         qcom,single-led-1000;
 299         qcom,single-led-100;
 300         qcom,single-led-10;
 301 };
 302
 303 &ethphy3 {
 304         qcom,single-led-1000;
 305         qcom,single-led-100;
 306         qcom,single-led-10;
 307 };
 308
 309 &ethphy4 {
 310         qcom,single-led-1000;
 311         qcom,single-led-100;
 312         qcom,single-led-10;
 313 };
 314
 315 &gmac {
 316         status = "okay";
 317 };
 318
 319 &switch {
 320         status = "okay";
 321 };
 322
 323 &swport1 {
 324         status = "okay";
 325
 326         label = "lan4";
 327 };
 328
 329 &swport2 {
 330         status = "okay";
 331
 332         label = "lan3";
 333 };
 334
 335 &swport3 {
 336         status = "okay";
 337
 338         label = "lan2";
 339 };
 340
 341 &swport4 {
 342         status = "okay";
 343
 344         label = "lan1";
 345 };
 346
 347 &swport5 {
 348         status = "okay";
 349 };
 350
 351 &usb3_ss_phy {
 352         status = "okay";
 353 };
 354
 355 &usb3_hs_phy {
 356         status = "okay";
 357 };
 358
 359 &usb3 {
 360         status = "okay";
 361 };
 362
 363 &usb2_hs_phy {
 364         status = "okay";
 365 };
 366
 367 &usb2 {
 368         status = "okay";
 369 };
 370
 371 &vqmmc {
 372         status = "okay";
 373 };
 374
 375 &wifi0 {
 376         status = "okay";
 377         nvmem-cell-names = "pre-calibration";
 378         nvmem-cells = <&precal_art_1000>;
 379         qcom,ath10k-calibration-variant = "P&W-R619AC";
 380 };
 381
 382 &wifi1 {
 383         status = "okay";
 384         nvmem-cell-names = "pre-calibration";
 385         nvmem-cells = <&precal_art_5000>;
 386         qcom,ath10k-calibration-variant = "P&W-R619AC";
 387 };