mediatek: add missing ';;' in shell switch case block
[openwrt/staging/pepe2k.git] / target / linux / ipq40xx / files-6.6 / arch / arm / boot / dts / qcom / qcom-ipq4019-gl-b2200.dts
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/soc/qcom,tcsr.h>
8
9 / {
10 model = "GL.iNet GL-B2200";
11 compatible = "glinet,gl-b2200", "qcom,ipq4019";
12
13 memory {
14 device_type = "memory";
15 reg = <0x80000000 0x10000000>;
16 };
17
18 chosen {
19 bootargs-append = " root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused";
20 };
21
22 aliases {
23 ethernet1 = &swport4;
24 };
25
26 soc {
27 tcsr@1949000 {
28 compatible = "qcom,tcsr";
29 reg = <0x1949000 0x100>;
30 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
31 };
32
33 tcsr@194b000 {
34 /* select hostmode */
35 compatible = "qcom,tcsr";
36 reg = <0x194b000 0x100>;
37 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
38 status = "okay";
39 };
40
41 ess_tcsr@1953000 {
42 compatible = "qcom,tcsr";
43 reg = <0x1953000 0x1000>;
44 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
45 };
46
47 tcsr@1957000 {
48 compatible = "qcom,tcsr";
49 reg = <0x1957000 0x100>;
50 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
51 };
52 };
53
54 keys {
55 compatible = "gpio-keys";
56
57 wps {
58 label = "wps";
59 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
60 linux,code = <KEY_WPS_BUTTON>;
61 linux,input-type = <1>;
62 };
63
64 reset {
65 label = "reset";
66 gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
67 linux,code = <KEY_RESTART>;
68 linux,input-type = <1>;
69 };
70 };
71
72 leds {
73 compatible = "gpio-leds";
74
75 power_blue {
76 function = LED_FUNCTION_POWER;
77 color = <LED_COLOR_ID_BLUE>;
78 gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
79 default-state = "on";
80 };
81 internet_blue {
82 label = "blue:internet";
83 gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
84 };
85 power_white {
86 function = LED_FUNCTION_POWER;
87 color = <LED_COLOR_ID_WHITE>;
88 gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
89 };
90 internet_white {
91 label = "white:internet";
92 gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
93 };
94 };
95 };
96
97 &prng {
98 status = "okay";
99 };
100
101 &crypto {
102 status = "okay";
103 };
104
105 &vqmmc {
106 status = "okay";
107 };
108
109 &sdhci {
110 status = "okay";
111 pinctrl-0 = <&sd_pins>;
112 pinctrl-names = "default";
113 cd-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
114 vqmmc-supply = <&vqmmc>;
115 };
116
117 &blsp_dma {
118 status = "okay";
119 };
120
121 &cryptobam {
122 status = "okay";
123 };
124
125 &blsp1_spi1 {
126 pinctrl-0 = <&spi_0_pins>;
127 pinctrl-names = "default";
128 status = "okay";
129 cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
130
131 flash@0 {
132 compatible = "jedec,spi-nor";
133 reg = <0>;
134 spi-max-frequency = <24000000>;
135
136 partitions {
137 compatible = "fixed-partitions";
138 #address-cells = <1>;
139 #size-cells = <1>;
140
141 partition@0 {
142 label = "SBL1";
143 reg = <0x0 0x40000>;
144 read-only;
145 };
146
147 partition@40000 {
148 label = "MIBIB";
149 reg = <0x40000 0x20000>;
150 read-only;
151 };
152
153 partition@60000 {
154 label = "QSEE";
155 reg = <0x60000 0x60000>;
156 read-only;
157 };
158
159 partition@c0000 {
160 label = "CDT";
161 reg = <0xc0000 0x10000>;
162 read-only;
163 };
164
165 partition@d0000 {
166 label = "DDRPARAMS";
167 reg = <0xd0000 0x10000>;
168 read-only;
169 };
170
171 partition@e0000 {
172 label = "APPSBLENV";
173 reg = <0xe0000 0x10000>;
174 read-only;
175 };
176
177 partition@f0000 {
178 label = "APPSBL";
179 reg = <0xf0000 0x80000>;
180 read-only;
181 };
182
183 partition@170000 {
184 label = "ART";
185 reg = <0x170000 0x10000>;
186 read-only;
187
188 nvmem-layout {
189 compatible = "fixed-layout";
190 #address-cells = <1>;
191 #size-cells = <1>;
192
193 precal_art_1000: precal@1000 {
194 reg = <0x1000 0x2f20>;
195 };
196
197 precal_art_5000: precal@5000 {
198 reg = <0x5000 0x2f20>;
199 };
200
201 precal_art_9000: precal@9000 {
202 reg = <0x9000 0x2f20>;
203 };
204 };
205 };
206 };
207 };
208 };
209
210 &blsp1_spi2 {
211 pinctrl-0 = <&spi_1_pins>;
212 pinctrl-names = "default";
213 status = "okay";
214
215 spidev1: spi@0 {
216 compatible = "silabs,si3210";
217 reg = <0>;
218 spi-max-frequency = <24000000>;
219 };
220 };
221
222 &blsp1_uart1 {
223 pinctrl-0 = <&serial_pins>;
224 pinctrl-names = "default";
225 status = "okay";
226 };
227
228 &blsp1_uart2 {
229 pinctrl-0 = <&serial_1_pins>;
230 pinctrl-names = "default";
231 status = "okay";
232 };
233
234 &tlmm {
235 serial_pins: serial_pinmux {
236 mux {
237 pins = "gpio16", "gpio17";
238 function = "blsp_uart0";
239 bias-disable;
240 };
241 };
242
243 serial_1_pins: serial1_pinmux {
244 mux {
245 pins = "gpio8", "gpio9",
246 "gpio10", "gpio11";
247 function = "blsp_uart1";
248 bias-disable;
249 };
250 };
251
252 spi_0_pins: spi_0_pinmux {
253 pinmux {
254 function = "blsp_spi0";
255 pins = "gpio13", "gpio14", "gpio15";
256 };
257 pinmux_cs {
258 function = "gpio";
259 pins = "gpio12";
260 };
261 pinconf {
262 pins = "gpio13", "gpio14", "gpio15";
263 drive-strength = <12>;
264 bias-disable;
265 };
266 pinconf_cs {
267 pins = "gpio12";
268 drive-strength = <2>;
269 bias-disable;
270 output-high;
271 };
272 };
273
274 spi_1_pins: spi_1_pinmux {
275 mux {
276 pins = "gpio44", "gpio46", "gpio47";
277 function = "blsp_spi1";
278 bias-disable;
279 };
280 cs {
281 pins = "gpio45";
282 function = "gpio";
283 bias-pull-up;
284 };
285 reset {
286 pins = "gpio43";
287 function = "gpio";
288 output-high;
289 };
290 mux_2 {
291 pins = "gpio35";
292 function = "gpio";
293 output-high;
294 };
295 host_int {
296 pins = "gpio2";
297 function = "gpio";
298 input;
299 };
300 wake {
301 pins = "gpio48";
302 function = "gpio";
303 output-high;
304 };
305 };
306
307 sd_pins: sd_pins {
308 pinmux {
309 function = "sdio";
310 pins = "gpio23", "gpio24", "gpio25", "gpio26",
311 "gpio29", "gpio30", "gpio31", "gpio32";
312 drive-strength = <10>;
313 };
314
315 pinmux_sd_clk {
316 function = "sdio";
317 pins = "gpio27";
318 drive-strength = <16>;
319 };
320
321 pinmux_sd7 {
322 function = "sdio";
323 pins = "gpio28";
324 drive-strength = <10>;
325 bias-disable;
326 };
327 };
328
329 };
330
331 &pcie0 {
332 status = "okay";
333 perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
334 wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
335
336 bridge@0,0 {
337 reg = <0x00000000 0 0 0 0>;
338 #address-cells = <3>;
339 #size-cells = <2>;
340 ranges;
341
342 wifi2: wifi@1,0 {
343 status = "okay";
344 /* Bootlog shows this is a 168c:0056 - QCA 9888v2 */
345 compatible = "qcom,ath10k";
346 reg = <0x00010000 0 0 0 0>;
347 nvmem-cell-names = "pre-calibration";
348 nvmem-cells = <&precal_art_9000>;
349 qcom,ath10k-calibration-variant = "GL-B2200";
350 ieee80211-freq-limit = <5450000 5900000>;
351 };
352 };
353 };
354
355 &mdio {
356 status = "okay";
357 };
358
359 &gmac {
360 status = "okay";
361 };
362
363 &switch {
364 status = "okay";
365 };
366
367 &swport4 {
368 status = "okay";
369
370 label = "wan";
371 };
372
373 &swport5 {
374 status = "okay";
375
376 label = "lan";
377 };
378
379 &wifi0 {
380 status = "okay";
381 nvmem-cell-names = "pre-calibration";
382 nvmem-cells = <&precal_art_1000>;
383 qcom,ath10k-calibration-variant = "GL-B2200";
384 };
385
386 &wifi1 {
387 status = "okay";
388 nvmem-cell-names = "pre-calibration";
389 nvmem-cells = <&precal_art_5000>;
390 qcom,ath10k-calibration-variant = "GL-B2200";
391 ieee80211-freq-limit = <5100000 5400000>;
392 };