target/linux/ipq40xx/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 // Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
   3
   4 #include "qcom-ipq4019.dtsi"
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7 #include <dt-bindings/soc/qcom,tcsr.h>
   8
   9 / {
  10         aliases {
  11                 ethernet1 = &swport5;
  12         };
  13
  14         soc {
  15                 rng@22000 {
  16                         status = "okay";
  17                 };
  18
  19                 mdio@90000 {
  20                         status = "okay";
  21
  22                         pinctrl-0 = <&mdio_pins>;
  23                         pinctrl-names = "default";
  24                 };
  25
  26                 counter@4a1000 {
  27                         compatible = "qcom,qca-gcnt";
  28                         reg = <0x4a1000 0x4>;
  29                 };
  30
  31                 tcsr@1949000 {
  32                         compatible = "qcom,tcsr";
  33                         reg = <0x1949000 0x100>;
  34                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  35                 };
  36
  37                 tcsr@194b000 {
  38                         status = "okay";
  39
  40                         compatible = "qcom,tcsr";
  41                         reg = <0x194b000 0x100>;
  42                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  43                 };
  44
  45                 ess_tcsr@1953000 {
  46                         compatible = "qcom,tcsr";
  47                         reg = <0x1953000 0x1000>;
  48                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  49                 };
  50
  51                 tcsr@1957000 {
  52                         compatible = "qcom,tcsr";
  53                         reg = <0x1957000 0x100>;
  54                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  55                 };
  56
  57                 crypto@8e3a000 {
  58                         status = "okay";
  59                 };
  60
  61                 watchdog@b017000 {
  62                         status = "okay";
  63                 };
  64         };
  65 };
  66
  67 &tlmm {
  68         mdio_pins: mdio_pinmux {
  69                 pinmux_1 {
  70                         pins = "gpio53";
  71                         function = "mdio";
  72                 };
  73
  74                 pinmux_2 {
  75                         pins = "gpio52";
  76                         function = "mdc";
  77                 };
  78
  79                 pinconf {
  80                         pins = "gpio52", "gpio53";
  81                         bias-pull-up;
  82                 };
  83         };
  84
  85         serial_pins: serial_pinmux {
  86                 mux {
  87                         pins = "gpio60", "gpio61";
  88                         function = "blsp_uart0";
  89                         bias-disable;
  90                 };
  91         };
  92
  93         spi_0_pins: spi_0_pinmux {
  94                 pin {
  95                         function = "blsp_spi0";
  96                         pins = "gpio55", "gpio56", "gpio57";
  97                         drive-strength = <2>;
  98                         bias-disable;
  99                 };
 100
 101                 pin_cs {
 102                         function = "gpio";
 103                         pins = "gpio54", "gpio59";
 104                         drive-strength = <2>;
 105                         bias-disable;
 106                         output-high;
 107                 };
 108         };
 109 };
 110
 111 &blsp_dma {
 112         status = "okay";
 113 };
 114
 115 &blsp1_spi1 {
 116         status = "okay";
 117
 118         pinctrl-0 = <&spi_0_pins>;
 119         pinctrl-names = "default";
 120         cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
 121
 122         flash@0 {
 123                 status = "okay";
 124
 125                 compatible = "jedec,spi-nor";
 126                 reg = <0>;
 127                 spi-max-frequency = <24000000>;
 128
 129                 partitions {
 130                         compatible = "fixed-partitions";
 131                         #address-cells = <1>;
 132                         #size-cells = <1>;
 133
 134                         partition@0 {
 135                                 label = "SBL1";
 136                                 reg = <0x00000000 0x00040000>;
 137                                 read-only;
 138                         };
 139
 140                         partition@40000 {
 141                                 label = "MIBIB";
 142                                 reg = <0x00040000 0x00020000>;
 143                                 read-only;
 144                         };
 145
 146                         partition@60000 {
 147                                 label = "QSEE";
 148                                 reg = <0x00060000 0x00060000>;
 149                                 read-only;
 150                         };
 151
 152                         partition@c0000 {
 153                                 label = "CDT";
 154                                 reg = <0x000c0000 0x00010000>;
 155                                 read-only;
 156                         };
 157
 158                         partition@d0000 {
 159                                 label = "DDRPARAMS";
 160                                 reg = <0x000d0000 0x00010000>;
 161                                 read-only;
 162                         };
 163
 164                         partition@e0000 {
 165                                 label = "APPSBLENV"; /* uboot env*/
 166                                 reg = <0x000e0000 0x00010000>;
 167                                 read-only;
 168                         };
 169
 170                         partition@f0000 {
 171                                 label = "APPSBL"; /* uboot */
 172                                 reg = <0x000f0000 0x00080000>;
 173                                 read-only;
 174                         };
 175
 176                         partition@170000 {
 177                                 label = "ART";
 178                                 reg = <0x00170000 0x00010000>;
 179                                 read-only;
 180
 181                                 nvmem-layout {
 182                                         compatible = "fixed-layout";
 183                                         #address-cells = <1>;
 184                                         #size-cells = <1>;
 185
 186                                         precal_art_1000: precal@1000 {
 187                                                 reg = <0x1000 0x2f20>;
 188                                         };
 189
 190                                         precal_art_5000: precal@5000 {
 191                                                 reg = <0x5000 0x2f20>;
 192                                         };
 193                                 };
 194                         };
 195                 };
 196         };
 197
 198         spi-nand@1 {
 199                 status = "okay";
 200
 201                 compatible = "spi-nand";
 202                 reg = <1>;
 203                 spi-max-frequency = <24000000>;
 204
 205                 partitions {
 206                         compatible = "fixed-partitions";
 207                         #address-cells = <1>;
 208                         #size-cells = <1>;
 209
 210                         partition@0 {
 211                                 label = "ubi";
 212                                 reg = <0x00000000 0x08000000>;
 213                         };
 214                 };
 215         };
 216 };
 217
 218 &blsp1_uart1 {
 219         status = "okay";
 220
 221         pinctrl-0 = <&serial_pins>;
 222         pinctrl-names = "default";
 223 };
 224
 225 &cryptobam {
 226         status = "okay";
 227 };
 228
 229 &gmac {
 230         status = "okay";
 231 };
 232
 233 &switch {
 234         status = "okay";
 235 };
 236
 237 &swport4 {
 238         status = "okay";
 239
 240         label = "lan";
 241 };
 242
 243 &swport5 {
 244         status = "okay";
 245 };
 246
 247 &wifi0 {
 248         status = "okay";
 249         nvmem-cell-names = "pre-calibration";
 250         nvmem-cells = <&precal_art_1000>;
 251         qcom,ath10k-calibration-variant = "8devices-Jalapeno";
 252 };
 253
 254 &wifi1 {
 255         status = "okay";
 256         nvmem-cell-names = "pre-calibration";
 257         nvmem-cells = <&precal_art_5000>;
 258         qcom,ath10k-calibration-variant = "8devices-Jalapeno";
 259 };
 260
 261 &usb3 {
 262         status = "okay";
 263 };
 264
 265 &usb3_ss_phy {
 266         status = "okay";
 267 };
 268
 269 &usb3_hs_phy {
 270         status = "okay";
 271 };
 272
 273 &usb2 {
 274         status = "okay";
 275 };
 276
 277 &usb2_hs_phy {
 278         status = "okay";
 279 };