target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-gl-b2200.dts

   1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
   2
   3 #include "qcom-ipq4019.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/leds/common.h>
   7 #include <dt-bindings/soc/qcom,tcsr.h>
   8
   9 / {
  10         model = "GL.iNet GL-B2200";
  11         compatible = "glinet,gl-b2200", "qcom,ipq4019";
  12
  13         memory {
  14                 device_type = "memory";
  15                 reg = <0x80000000 0x10000000>;
  16         };
  17
  18         chosen {
  19                 bootargs-append = " root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused";
  20         };
  21
  22         aliases {
  23                 ethernet1 = &swport4;
  24         };
  25
  26         soc {
  27                 rng@22000 {
  28                         status = "okay";
  29                 };
  30
  31                 mdio@90000 {
  32                         status = "okay";
  33                 };
  34
  35                 tcsr@1949000 {
  36                         compatible = "qcom,tcsr";
  37                         reg = <0x1949000 0x100>;
  38                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  39                 };
  40
  41                 tcsr@194b000 {
  42                         /* select hostmode */
  43                         compatible = "qcom,tcsr";
  44                         reg = <0x194b000 0x100>;
  45                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  46                         status = "okay";
  47                 };
  48
  49                 ess_tcsr@1953000 {
  50                         compatible = "qcom,tcsr";
  51                         reg = <0x1953000 0x1000>;
  52                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  53                 };
  54
  55                 tcsr@1957000 {
  56                         compatible = "qcom,tcsr";
  57                         reg = <0x1957000 0x100>;
  58                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  59                 };
  60
  61                 crypto@8e3a000 {
  62                         status = "okay";
  63                 };
  64         };
  65
  66         keys {
  67                 compatible = "gpio-keys";
  68
  69                 wps {
  70                         label = "wps";
  71                         gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
  72                         linux,code = <KEY_WPS_BUTTON>;
  73                         linux,input-type = <1>;
  74                 };
  75
  76                 reset {
  77                         label = "reset";
  78                         gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
  79                         linux,code = <KEY_RESTART>;
  80                         linux,input-type = <1>;
  81                 };
  82         };
  83
  84         leds {
  85                 compatible = "gpio-leds";
  86
  87                 power_blue {
  88                         function = LED_FUNCTION_POWER;
  89                         color = <LED_COLOR_ID_BLUE>;
  90                         gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
  91                         default-state = "on";
  92                 };
  93                 internet_blue {
  94                         label = "blue:internet";
  95                         gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
  96                 };
  97                 power_white {
  98                         function = LED_FUNCTION_POWER;
  99                         color = <LED_COLOR_ID_WHITE>;
 100                         gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
 101                 };
 102                 internet_white {
 103                         label = "white:internet";
 104                         gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
 105                 };
 106         };
 107 };
 108
 109 &vqmmc {
 110         status = "okay";
 111 };
 112
 113 &sdhci {
 114         status = "okay";
 115         pinctrl-0 = <&sd_pins>;
 116         pinctrl-names = "default";
 117         cd-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
 118         vqmmc-supply = <&vqmmc>;
 119 };
 120
 121 &blsp_dma {
 122         status = "okay";
 123 };
 124
 125 &cryptobam {
 126         status = "okay";
 127 };
 128
 129 &blsp1_spi1 {
 130         pinctrl-0 = <&spi_0_pins>;
 131         pinctrl-names = "default";
 132         status = "okay";
 133         cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
 134
 135         flash@0 {
 136                 compatible = "jedec,spi-nor";
 137                 reg = <0>;
 138                 spi-max-frequency = <24000000>;
 139
 140                 partitions {
 141                         compatible = "fixed-partitions";
 142                         #address-cells = <1>;
 143                         #size-cells = <1>;
 144
 145                         partition@0 {
 146                                 label = "SBL1";
 147                                 reg = <0x0 0x40000>;
 148                                 read-only;
 149                         };
 150
 151                         partition@40000 {
 152                                 label = "MIBIB";
 153                                 reg = <0x40000 0x20000>;
 154                                 read-only;
 155                         };
 156
 157                         partition@60000 {
 158                                 label = "QSEE";
 159                                 reg = <0x60000 0x60000>;
 160                                 read-only;
 161                         };
 162
 163                         partition@c0000 {
 164                                 label = "CDT";
 165                                 reg = <0xc0000 0x10000>;
 166                                 read-only;
 167                         };
 168
 169                         partition@d0000 {
 170                                 label = "DDRPARAMS";
 171                                 reg = <0xd0000 0x10000>;
 172                                 read-only;
 173                         };
 174
 175                         partition@e0000 {
 176                                 label = "APPSBLENV";
 177                                 reg = <0xe0000 0x10000>;
 178                                 read-only;
 179                         };
 180
 181                         partition@f0000 {
 182                                 label = "APPSBL";
 183                                 reg = <0xf0000 0x80000>;
 184                                 read-only;
 185                         };
 186
 187                         partition@170000 {
 188                                 label = "ART";
 189                                 reg = <0x170000 0x10000>;
 190                                 read-only;
 191
 192                                 nvmem-layout {
 193                                         compatible = "fixed-layout";
 194                                         #address-cells = <1>;
 195                                         #size-cells = <1>;
 196
 197                                         precal_art_1000: precal@1000 {
 198                                                 reg = <0x1000 0x2f20>;
 199                                         };
 200
 201                                         precal_art_5000: precal@5000 {
 202                                                 reg = <0x5000 0x2f20>;
 203                                         };
 204
 205                                         precal_art_9000: precal@9000 {
 206                                                 reg = <0x9000 0x2f20>;
 207                                         };
 208                                 };
 209                         };
 210                 };
 211         };
 212 };
 213
 214 &blsp1_spi2 {
 215         pinctrl-0 = <&spi_1_pins>;
 216         pinctrl-names = "default";
 217         status = "okay";
 218
 219         spidev1: spi@0 {
 220                 compatible = "silabs,si3210";
 221                 reg = <0>;
 222                 spi-max-frequency = <24000000>;
 223         };
 224 };
 225
 226 &blsp1_uart1 {
 227         pinctrl-0 = <&serial_pins>;
 228         pinctrl-names = "default";
 229         status = "okay";
 230 };
 231
 232 &blsp1_uart2 {
 233         pinctrl-0 = <&serial_1_pins>;
 234         pinctrl-names = "default";
 235         status = "okay";
 236 };
 237
 238 &tlmm {
 239         serial_pins: serial_pinmux {
 240                 mux {
 241                         pins = "gpio16", "gpio17";
 242                         function = "blsp_uart0";
 243                         bias-disable;
 244                 };
 245         };
 246
 247         serial_1_pins: serial1_pinmux {
 248                 mux {
 249                         pins = "gpio8", "gpio9",
 250                                 "gpio10", "gpio11";
 251                         function = "blsp_uart1";
 252                         bias-disable;
 253                 };
 254         };
 255
 256         spi_0_pins: spi_0_pinmux {
 257                 pinmux {
 258                         function = "blsp_spi0";
 259                         pins = "gpio13", "gpio14", "gpio15";
 260                 };
 261                 pinmux_cs {
 262                         function = "gpio";
 263                         pins = "gpio12";
 264                 };
 265                 pinconf {
 266                         pins = "gpio13", "gpio14", "gpio15";
 267                         drive-strength = <12>;
 268                         bias-disable;
 269                 };
 270                 pinconf_cs {
 271                         pins = "gpio12";
 272                         drive-strength = <2>;
 273                         bias-disable;
 274                         output-high;
 275                 };
 276         };
 277
 278         spi_1_pins: spi_1_pinmux {
 279                 mux {
 280                         pins = "gpio44", "gpio46", "gpio47";
 281                         function = "blsp_spi1";
 282                         bias-disable;
 283                 };
 284                 cs {
 285                         pins = "gpio45";
 286                         function = "gpio";
 287                         bias-pull-up;
 288                 };
 289                 reset {
 290                         pins = "gpio43";
 291                         function = "gpio";
 292                         output-high;
 293                 };
 294                 mux_2 {
 295                         pins = "gpio35";
 296                         function = "gpio";
 297                         output-high;
 298                 };
 299                 host_int {
 300                         pins = "gpio2";
 301                         function = "gpio";
 302                         input;
 303                 };
 304                 wake {
 305                         pins = "gpio48";
 306                         function = "gpio";
 307                         output-high;
 308                 };
 309         };
 310
 311         sd_pins: sd_pins {
 312                 pinmux {
 313                         function = "sdio";
 314                         pins = "gpio23", "gpio24", "gpio25", "gpio26",
 315                                 "gpio29", "gpio30", "gpio31", "gpio32";
 316                         drive-strength = <10>;
 317                 };
 318
 319                 pinmux_sd_clk {
 320                         function = "sdio";
 321                         pins = "gpio27";
 322                         drive-strength = <16>;
 323                 };
 324
 325                 pinmux_sd7 {
 326                         function = "sdio";
 327                         pins = "gpio28";
 328                         drive-strength = <10>;
 329                         bias-disable;
 330                 };
 331         };
 332
 333 };
 334
 335 &pcie0 {
 336         status = "okay";
 337         perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
 338         wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
 339
 340         bridge@0,0 {
 341                 reg = <0x00000000 0 0 0 0>;
 342                 #address-cells = <3>;
 343                 #size-cells = <2>;
 344                 ranges;
 345
 346                 wifi2: wifi@1,0 {
 347                         status = "okay";
 348                         /* Bootlog shows this is a 168c:0056 - QCA 9888v2 */
 349                         compatible = "qcom,ath10k";
 350                         reg = <0x00010000 0 0 0 0>;
 351                         nvmem-cell-names = "pre-calibration";
 352                         nvmem-cells = <&precal_art_9000>;
 353                         qcom,ath10k-calibration-variant = "GL-B2200";
 354                         ieee80211-freq-limit = <5450000 5900000>;
 355                 };
 356         };
 357 };
 358
 359 &gmac {
 360         status = "okay";
 361 };
 362
 363 &switch {
 364         status = "okay";
 365 };
 366
 367 &swport4 {
 368         status = "okay";
 369
 370         label = "wan";
 371 };
 372
 373 &swport5 {
 374         status = "okay";
 375
 376         label = "lan";
 377 };
 378
 379 &wifi0 {
 380         status = "okay";
 381         nvmem-cell-names = "pre-calibration";
 382         nvmem-cells = <&precal_art_1000>;
 383         qcom,ath10k-calibration-variant = "GL-B2200";
 384 };
 385
 386 &wifi1 {
 387         status = "okay";
 388         nvmem-cell-names = "pre-calibration";
 389         nvmem-cells = <&precal_art_5000>;
 390         qcom,ath10k-calibration-variant = "GL-B2200";
 391         ieee80211-freq-limit = <5100000 5400000>;
 392 };