ipq40xx: convert GL-AP1300 to DSA
[openwrt/staging/dedeckeh.git] / target / linux / ipq40xx / files / arch / arm / boot / dts / qcom-ipq4018-gl-ap1300.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/soc/qcom,tcsr.h>
7
8 / {
9 model = "GL.iNet GL-AP1300";
10 compatible = "glinet,gl-ap1300";
11
12 aliases {
13 led-boot = &led_power;
14 led-failsafe = &led_power;
15 led-running = &led_power;
16 led-upgrade = &led_power;
17 };
18
19 memory {
20 device_type = "memory";
21 reg = <0x80000000 0x10000000>;
22 };
23
24 chosen {
25 bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
26 };
27
28 soc {
29 rng@22000 {
30 status = "okay";
31 };
32
33 mdio@90000 {
34 status = "okay";
35 };
36
37 tcsr@1949000 {
38 compatible = "qcom,tcsr";
39 reg = <0x1949000 0x100>;
40 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
41 };
42
43 tcsr@194b000 {
44 /* select hostmode */
45 compatible = "qcom,tcsr";
46 reg = <0x194b000 0x100>;
47 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
48 status = "okay";
49 };
50
51 ess_tcsr@1953000 {
52 compatible = "qcom,tcsr";
53 reg = <0x1953000 0x1000>;
54 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
55 };
56
57 tcsr@1957000 {
58 compatible = "qcom,tcsr";
59 reg = <0x1957000 0x100>;
60 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
61 };
62
63 usb2@60f8800 {
64 status = "okay";
65 };
66
67 usb3@8af8800 {
68 status = "okay";
69 };
70
71 crypto@8e3a000 {
72 status = "okay";
73 };
74
75 watchdog@b017000 {
76 status = "okay";
77 };
78 };
79
80 keys {
81 compatible = "gpio-keys";
82
83 reset {
84 label = "reset";
85 gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
86 linux,code = <KEY_RESTART>;
87 };
88 };
89
90 leds {
91 compatible = "gpio-leds";
92
93 led_power: power {
94 label = "white:power";
95 gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
96 default-state = "on";
97 };
98
99 wan {
100 label = "white:wan";
101 gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
102 };
103 };
104 };
105
106 &blsp_dma {
107 status = "okay";
108 };
109
110 &cryptobam {
111 status = "okay";
112 };
113
114 &blsp1_spi1 {
115 status = "okay";
116
117 pinctrl-0 = <&spi0_pins>;
118 pinctrl-names = "default";
119 cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 5 GPIO_ACTIVE_HIGH>;
120
121 flash@0 {
122 status = "okay";
123
124 compatible = "jedec,spi-nor";
125 reg = <0>;
126 spi-max-frequency = <24000000>;
127
128 partitions {
129 compatible = "fixed-partitions";
130 #address-cells = <1>;
131 #size-cells = <1>;
132
133 partition@0 {
134 label = "SBL1";
135 reg = <0x00000000 0x00040000>;
136 read-only;
137 };
138
139 partition@40000 {
140 label = "MIBIB";
141 reg = <0x00040000 0x00020000>;
142 read-only;
143 };
144
145 partition@60000 {
146 label = "QSEE";
147 reg = <0x00060000 0x00060000>;
148 read-only;
149 };
150
151 partition@c0000 {
152 label = "CDT";
153 reg = <0x000c0000 0x00010000>;
154 read-only;
155 };
156
157 partition@d0000 {
158 label = "DDRPARAMS";
159 reg = <0x000d0000 0x00010000>;
160 read-only;
161 };
162
163 partition@e0000 {
164 label = "APPSBLENV"; /* uboot env*/
165 reg = <0x000e0000 0x00010000>;
166 };
167
168 partition@f0000 {
169 label = "APPSBL"; /* uboot */
170 reg = <0x000f0000 0x00080000>;
171 read-only;
172 };
173
174 partition@170000 {
175 label = "ART";
176 reg = <0x00170000 0x00010000>;
177 read-only;
178 compatible = "nvmem-cells";
179 #address-cells = <1>;
180 #size-cells = <1>;
181
182 macaddr_art_0: mac-address@0 {
183 reg = <0x0 0x6>;
184 };
185
186 macaddr_art_6: mac-address@6 {
187 reg = <0x6 0x6>;
188 };
189
190 precal_art_1000: precal@1000 {
191 reg = <0x1000 0x2f20>;
192 };
193
194 precal_art_5000: precal@5000 {
195 reg = <0x5000 0x2f20>;
196 };
197 };
198 };
199 };
200
201 spi-nand@1 {
202 status = "okay";
203
204 compatible = "spi-nand";
205 reg = <1>;
206 spi-max-frequency = <24000000>;
207
208 partitions {
209 compatible = "fixed-partitions";
210 #address-cells = <1>;
211 #size-cells = <1>;
212
213 partition@0 {
214 label = "ubi";
215 reg = <0x00000000 0x08000000>;
216 };
217 };
218 };
219 };
220
221 &blsp1_uart1 {
222 pinctrl-0 = <&serial_pins>;
223 pinctrl-names = "default";
224 status = "okay";
225 };
226
227 &tlmm {
228 serial_pins: serial_pinmux {
229 mux {
230 pins = "gpio60", "gpio61";
231 function = "blsp_uart0";
232 bias-disable;
233 };
234 };
235
236 spi0_pins: spi0_pinmux {
237 mux_spi {
238 function = "blsp_spi0";
239 pins = "gpio55", "gpio56", "gpio57";
240 drive-strength = <12>;
241 bias-disable;
242 };
243
244 mux_cs {
245 function = "gpio";
246 pins = "gpio54", "gpio5";
247 drive-strength = <2>;
248 bias-disable;
249 output-high;
250 };
251 };
252 };
253
254 &usb2_hs_phy {
255 status = "okay";
256 };
257
258 &usb3_hs_phy {
259 status = "okay";
260 };
261
262 &usb3_ss_phy {
263 status = "okay";
264 };
265
266 &gmac {
267 status = "okay";
268 };
269
270 &switch {
271 status = "okay";
272 };
273
274 &swport4 {
275 status = "okay";
276 label = "lan";
277
278 nvmem-cells = <&macaddr_art_0>;
279 nvmem-cell-names = "mac-address";
280 };
281
282 &swport5 {
283 status = "okay";
284 label = "wan";
285
286 nvmem-cells = <&macaddr_art_6>;
287 nvmem-cell-names = "mac-address";
288 };
289
290 &wifi0 {
291 status = "okay";
292 nvmem-cell-names = "pre-calibration";
293 nvmem-cells = <&precal_art_1000>;
294 qcom,ath10k-calibration-variant = "GL-AP1300";
295 };
296
297 &wifi1 {
298 status = "okay";
299 nvmem-cell-names = "pre-calibration";
300 nvmem-cells = <&precal_art_5000>;
301 qcom,ath10k-calibration-variant = "GL-AP1300";
302 };