ipq40xx: convert to new LED color/function format where possible
[openwrt/staging/nbd.git] / target / linux / ipq40xx / files / arch / arm / boot / dts / qcom-ipq4018-ea6350v3.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/soc/qcom,tcsr.h>
8
9 / {
10 model = "Linksys EA6350v3";
11 compatible = "linksys,ea6350v3";
12
13 aliases {
14 led-boot = &power;
15 led-failsafe = &power;
16 led-running = &power;
17 led-upgrade = &power;
18 };
19
20 soc {
21 rng@22000 {
22 status = "okay";
23 };
24
25 mdio@90000 {
26 status = "okay";
27 };
28
29 tcsr@1949000 {
30 compatible = "qcom,tcsr";
31 reg = <0x1949000 0x100>;
32 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
33 };
34
35 tcsr@194b000 {
36 compatible = "qcom,tcsr";
37 reg = <0x194b000 0x100>;
38 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
39 };
40
41 ess_tcsr@1953000 {
42 compatible = "qcom,tcsr";
43 reg = <0x1953000 0x1000>;
44 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
45 };
46
47 tcsr@1957000 {
48 compatible = "qcom,tcsr";
49 reg = <0x1957000 0x100>;
50 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
51 };
52
53 usb2@60f8800 {
54 status = "okay";
55 };
56
57 usb3@8af8800 {
58 status = "okay";
59 };
60
61 crypto@8e3a000 {
62 status = "okay";
63 };
64
65 watchdog@b017000 {
66 status = "okay";
67 };
68 };
69
70 keys {
71 compatible = "gpio-keys";
72
73 reset {
74 label = "reset";
75 gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
76 linux,code = <KEY_RESTART>;
77 };
78
79 wps {
80 label = "wps";
81 gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
82 linux,code = <KEY_WPS_BUTTON>;
83 };
84 };
85
86 leds {
87 compatible = "gpio-leds";
88
89 power: status {
90 function = LED_FUNCTION_STATUS;
91 color = <LED_COLOR_ID_GREEN>;
92 gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
93 };
94 };
95 };
96
97 &blsp1_uart1 {
98 pinctrl-0 = <&serial_pins>;
99 pinctrl-names = "default";
100 status = "okay";
101 };
102
103 &cryptobam {
104 status = "okay";
105 };
106
107 &gmac {
108 status = "okay";
109 };
110
111 &switch {
112 status = "okay";
113 };
114
115 &swport1 {
116 status = "okay";
117 };
118
119 &swport2 {
120 status = "okay";
121 };
122
123 &swport3 {
124 status = "okay";
125 };
126
127 &swport4 {
128 status = "okay";
129 };
130
131 &swport5 {
132 status = "okay";
133 };
134
135 &wifi0 {
136 status = "okay";
137 nvmem-cell-names = "pre-calibration";
138 nvmem-cells = <&precal_art_1000>;
139 qcom,ath10k-calibration-variant = "linksys-ea6350v3";
140 };
141
142 &wifi1 {
143 status = "okay";
144 nvmem-cell-names = "pre-calibration";
145 nvmem-cells = <&precal_art_5000>;
146 qcom,ath10k-calibration-variant = "linksys-ea6350v3";
147 };
148
149 &blsp_dma {
150 status = "okay";
151 };
152
153 &tlmm {
154 serial_pins: serial_pinmux {
155 mux {
156 pins = "gpio60", "gpio61";
157 function = "blsp_uart0";
158 bias-disable;
159 };
160 };
161
162 spi_0_pins: spi_0_pinmux {
163 mux {
164 function = "blsp_spi0";
165 pins = "gpio55", "gpio56", "gpio57";
166 drive-strength = <12>;
167 bias-disable;
168 };
169
170 mux_cs {
171 function = "gpio";
172 pins = "gpio54", "gpio59";
173 drive-strength = <2>;
174 bias-disable;
175 output-high;
176 };
177 };
178 };
179
180 &blsp1_spi1 { /* BLSP1 QUP1 */
181 pinctrl-0 = <&spi_0_pins>;
182 pinctrl-names = "default";
183 status = "okay";
184 cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
185 <&tlmm 59 GPIO_ACTIVE_HIGH>;
186
187 flash@0 {
188 compatible = "jedec,spi-nor";
189 reg = <0>;
190 spi-max-frequency = <24000000>;
191
192 partitions {
193 compatible = "fixed-partitions";
194 #address-cells = <1>;
195 #size-cells = <1>;
196
197 SBL1@0 {
198 label = "SBL1";
199 reg = <0x00000000 0x00040000>;
200 read-only;
201 };
202 MBIB@40000 {
203 label = "MIBIB";
204 reg = <0x00040000 0x00020000>;
205 read-only;
206 };
207 QSEE@60000 {
208 label = "QSEE";
209 reg = <0x00060000 0x00060000>;
210 read-only;
211 };
212 CDT@c0000 {
213 label = "CDT";
214 reg = <0x000c0000 0x00010000>;
215 read-only;
216 };
217 APPSBLENV@d0000 {
218 label = "APPSBLENV";
219 reg = <0x000d0000 0x00010000>;
220 read-only;
221 };
222 APPSBL@e0000 {
223 label = "APPSBL"; /* uboot */
224 reg = <0x000e0000 0x00080000>;
225 read-only;
226 };
227 ART@160000 {
228 label = "ART";
229 reg = <0x00160000 0x00010000>;
230 read-only;
231
232 nvmem-layout {
233 compatible = "fixed-layout";
234 #address-cells = <1>;
235 #size-cells = <1>;
236
237 precal_art_1000: precal@1000 {
238 reg = <0x1000 0x2f20>;
239 };
240
241 precal_art_5000: precal@5000 {
242 reg = <0x5000 0x2f20>;
243 };
244 };
245 };
246 u_env@170000 {
247 label = "u_env";
248 reg = <0x00170000 0x00020000>;
249 };
250 s_env@190000 {
251 label = "s_env";
252 reg = <0x00190000 0x00020000>;
253 };
254 devinfo@1b0000 {
255 label = "devinfo";
256 reg = <0x001b0000 0x00010000>;
257 };
258 /* 0x001c0000 - 0x00200000 unused */
259 };
260 };
261
262 flash@1 {
263 status = "okay";
264 compatible = "spi-nand";
265 reg = <1>;
266 spi-max-frequency = <24000000>;
267
268 partitions {
269 compatible = "fixed-partitions";
270 #address-cells = <1>;
271 #size-cells = <1>;
272
273 kernel@0 {
274 label = "kernel";
275 reg = <0x00000000 0x02800000>;
276 };
277 rootfs@500000 {
278 label = "rootfs";
279 reg = <0x00500000 0x02300000>;
280 };
281 alt_kernel@2800000 {
282 label = "alt_kernel";
283 reg = <0x02800000 0x02800000>;
284 };
285 alt_rootfs@2d00000 {
286 label = "alt_rootfs";
287 reg = <0x02d00000 0x02300000>;
288 };
289 sysdiag@5000000 {
290 label = "sysdiag";
291 reg = <0x05000000 0x00100000>;
292 };
293 syscfg@5100000 {
294 label = "syscfg";
295 reg = <0x05100000 0x02F00000>;
296 };
297 /* 0x00000000 - 0x08000000: 128 MiB */
298 };
299 };
300 };
301
302 &usb3_ss_phy {
303 status = "okay";
304 };
305
306 &usb3_hs_phy {
307 status = "okay";
308 };
309
310 &usb2_hs_phy {
311 status = "okay";
312 };