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[openwrt/openwrt.git] / target / linux / ifxmips / files-2.6.32 / drivers / crypto / ifxmips / ifxmips_aes.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
17 * Copyright (C) 2009 Mohammad Firdaus
18 */
19
20 /*!
21 \defgroup IFX_DEU IFX_DEU_DRIVERS
22 \ingroup API
23 \brief ifx DEU driver module
24 */
25
26 /*!
27 \file ifxmips_aes.c
28 \ingroup IFX_DEU
29 \brief AES Encryption Driver main file
30 */
31
32 /*!
33 \defgroup IFX_AES_FUNCTIONS IFX_AES_FUNCTIONS
34 \ingroup IFX_DEU
35 \brief IFX AES driver Functions
36 */
37
38
39 /* Project Header Files */
40 #include <linux/version.h>
41 #include <linux/module.h>
42 #include <linux/init.h>
43 #include <linux/types.h>
44 #include <linux/errno.h>
45 #include <linux/crypto.h>
46 #include <linux/interrupt.h>
47 #include <linux/delay.h>
48 #include <asm/byteorder.h>
49 #include <crypto/algapi.h>
50 #include "ifxmips_deu.h"
51
52 /* DMA related header and variables */
53 #ifdef CONFIG_CRYPTO_DEV_DMA
54 #include "ifxmips_deu_dma.h"
55 #include <asm/ifx/irq.h>
56 #include <asm/ifx/ifx_dma_core.h>
57 extern _ifx_deu_device ifx_deu[1];
58 extern u32 *aes_buff_in;
59 extern u32 *aes_buff_out;
60 #ifndef CONFIG_CRYPTO_DEV_POLL_DMA
61 #define CONFIG_CRYPTO_DEV_POLL_DMA
62 #endif
63 #endif /* CONFIG_CRYPTO_DEV_DMA */
64
65 spinlock_t aes_lock;
66 #define CRTCL_SECT_INIT spin_lock_init(&aes_lock)
67 #define CRTCL_SECT_START spin_lock_irqsave(&aes_lock, flag)
68 #define CRTCL_SECT_END spin_unlock_irqrestore(&aes_lock, flag)
69
70 /* Definition of constants */
71 #define AES_START IFX_AES_CON
72 #define AES_MIN_KEY_SIZE 16
73 #define AES_MAX_KEY_SIZE 32
74 #define AES_BLOCK_SIZE 16
75 #define CTR_RFC3686_NONCE_SIZE 4
76 #define CTR_RFC3686_IV_SIZE 8
77 #define CTR_RFC3686_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE)
78
79 /* Function decleration */
80 int aes_chip_init(void);
81 u32 endian_swap(u32 input);
82 u32 input_swap(u32 input);
83 u32* memory_alignment(const u8 *arg, u32 *buff_alloc, int in_out, int nbytes);
84 void aes_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);
85 void des_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);
86 int aes_memory_allocate(int value);
87 int des_memory_allocate(int value);
88 void memory_release(u32 *addr);
89
90 #ifndef CONFIG_CRYPTO_DEV_DMA
91 extern void ifx_deu_aes (void *ctx_arg, uint8_t *out_arg, const uint8_t *in_arg,
92 uint8_t *iv_arg, size_t nbytes, int encdec, int mode);
93 #else
94 extern void ifx_deu_aes_core (void *ctx_arg, uint8_t *out_arg, const uint8_t *in_arg,
95 uint8_t *iv_arg, size_t nbytes, int encdec, int mode);
96 #endif
97 /* End of function decleration */
98
99 struct aes_ctx {
100 int key_length;
101 u32 buf[AES_MAX_KEY_SIZE];
102 u8 nonce[CTR_RFC3686_NONCE_SIZE];
103 };
104
105
106 extern int disable_deudma;
107
108
109 /*! \fn int aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)
110 * \ingroup IFX_AES_FUNCTIONS
111 * \brief sets the AES keys
112 * \param tfm linux crypto algo transform
113 * \param in_key input key
114 * \param key_len key lengths of 16, 24 and 32 bytes supported
115 * \return -EINVAL - bad key length, 0 - SUCCESS
116 */
117 int aes_set_key (struct crypto_tfm *tfm, const u8 *in_key, unsigned int key_len)
118 {
119 struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
120 u32 *flags = &tfm->crt_flags;
121
122 DPRINTF(0, "ctx @%p, key_len %d\n", ctx, key_len);
123
124 if (key_len != 16 && key_len != 24 && key_len != 32) {
125 *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
126 return -EINVAL;
127 }
128
129 ctx->key_length = key_len;
130 memcpy ((u8 *) (ctx->buf), in_key, key_len);
131
132 return 0;
133 }
134
135
136 #ifndef CONFIG_CRYPTO_DEV_DMA
137 /*! \fn void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, size_t nbytes, int encdec, int mode)
138 * \ingroup IFX_AES_FUNCTIONS
139 * \brief main interface to AES hardware
140 * \param ctx_arg crypto algo context
141 * \param out_arg output bytestream
142 * \param in_arg input bytestream
143 * \param iv_arg initialization vector
144 * \param nbytes length of bytestream
145 * \param encdec 1 for encrypt; 0 for decrypt
146 * \param mode operation mode such as ebc, cbc, ctr
147 *
148 */
149 void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg,
150 u8 *iv_arg, size_t nbytes, int encdec, int mode)
151 #else
152
153 /*! \fn void ifx_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, size_t nbytes, int encdec, int mode)
154 * \ingroup IFX_AES_FUNCTIONS
155 * \brief main interface to AES hardware
156 * \param ctx_arg crypto algo context
157 * \param out_arg output bytestream
158 * \param in_arg input bytestream
159 * \param iv_arg initialization vector
160 * \param nbytes length of bytestream
161 * \param encdec 1 for encrypt; 0 for decrypt
162 * \param mode operation mode such as ebc, cbc, ctr
163 *
164 */
165 void ifx_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg,
166 u8 *iv_arg, size_t nbytes, int encdec, int mode)
167 #endif
168
169 {
170 /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
171 volatile struct aes_t *aes = (volatile struct aes_t *) AES_START;
172 struct aes_ctx *ctx = (struct aes_ctx *)ctx_arg;
173 u32 *in_key = ctx->buf;
174 ulong flag;
175 /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
176 int key_len = ctx->key_length;
177
178 #ifndef CONFIG_CRYPTO_DEV_DMA
179 int i = 0;
180 int byte_cnt = nbytes;
181
182 #else
183 volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON;
184 struct dma_device_info *dma_device = ifx_deu[0].dma_device;
185 //deu_drv_priv_t *deu_priv = (deu_drv_priv_t *)dma_device->priv;
186 int wlen = 0;
187 u32 *outcopy = NULL;
188 u32 *dword_mem_aligned_in = NULL;
189
190 #ifdef CONFIG_CRYPTO_DEV_POLL_DMA
191 u32 timeout = 0;
192 u32 *out_dma = NULL;
193 #endif
194
195 #endif
196
197 DPRINTF(0, "ctx @%p, mode %d, encdec %d\n", ctx, mode, encdec);
198
199 CRTCL_SECT_START;
200
201 /* 128, 192 or 256 bit key length */
202 aes->controlr.K = key_len / 8 - 2;
203 if (key_len == 128 / 8) {
204 aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));
205 aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));
206 aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));
207 aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));
208 }
209 else if (key_len == 192 / 8) {
210 aes->K5R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));
211 aes->K4R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));
212 aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));
213 aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));
214 aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 4));
215 aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 5));
216 }
217 else if (key_len == 256 / 8) {
218 aes->K7R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));
219 aes->K6R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));
220 aes->K5R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));
221 aes->K4R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));
222 aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 4));
223 aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 5));
224 aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 6));
225 aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 7));
226 }
227 else {
228 printk (KERN_ERR "[%s %s %d]: Invalid key_len : %d\n", __FILE__, __func__, __LINE__, key_len);
229 CRTCL_SECT_END;
230 return;// -EINVAL;
231 }
232
233 /* let HW pre-process DEcryption key in any case (even if
234 ENcryption is used). Key Valid (KV) bit is then only
235 checked in decryption routine! */
236 aes->controlr.PNK = 1;
237
238 #ifdef CONFIG_CRYPTO_DEV_DMA
239 while (aes->controlr.BUS) {
240 // this will not take long
241 }
242 AES_DMA_MISC_CONFIG();
243 #endif
244
245 aes->controlr.E_D = !encdec; /* encryption */
246 aes->controlr.O = mode; /* 0 ECB 1 CBC 2 OFB 3 CFB 4 CTR */
247 aes->controlr.SM = 1; /* start after writing input register */
248 aes->controlr.DAU = 0; /* Disable Automatic Update of init vector */
249 aes->controlr.ARS = 1; /* Autostart Select - write to IHR */
250
251 //aes->controlr.F = 128; //default; only for CFB and OFB modes; change only for customer-specific apps
252 if (mode > 0) {
253 aes->IV3R = DEU_ENDIAN_SWAP(*(u32 *) iv_arg);
254 aes->IV2R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));
255 aes->IV1R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2));
256 aes->IV0R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3));
257 };
258
259 #ifndef CONFIG_CRYPTO_DEV_DMA
260 i = 0;
261 while (byte_cnt >= 16) {
262
263 aes->ID3R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 0));
264 aes->ID2R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 1));
265 aes->ID1R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 2));
266 aes->ID0R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 3)); /* start crypto */
267
268 while (aes->controlr.BUS) {
269 // this will not take long
270 }
271
272 *((volatile u32 *) out_arg + (i * 4) + 0) = aes->OD3R;
273 *((volatile u32 *) out_arg + (i * 4) + 1) = aes->OD2R;
274 *((volatile u32 *) out_arg + (i * 4) + 2) = aes->OD1R;
275 *((volatile u32 *) out_arg + (i * 4) + 3) = aes->OD0R;
276
277 i++;
278 byte_cnt -= 16;
279 }
280
281 #else // dma
282
283 /* Prepare Rx buf length used in dma psuedo interrupt */
284 //deu_priv->deu_rx_buf = out_arg;
285 //deu_priv->deu_rx_len = nbytes;
286
287 /* memory alignment issue */
288 dword_mem_aligned_in = (u32 *) DEU_DWORD_REORDERING(in_arg, aes_buff_in, BUFFER_IN, nbytes);
289
290 dma->controlr.ALGO = 1; //AES
291 dma->controlr.BS = 0;
292 aes->controlr.DAU = 0;
293 dma->controlr.EN = 1;
294
295 while (aes->controlr.BUS) {
296 // wait for AES to be ready
297 };
298
299 wlen = dma_device_write (dma_device, (u8 *)dword_mem_aligned_in, nbytes, NULL);
300 if (wlen != nbytes) {
301 dma->controlr.EN = 0;
302 CRTCL_SECT_END;
303 printk (KERN_ERR "[%s %s %d]: dma_device_write fail!\n", __FILE__, __func__, __LINE__);
304 return; // -EINVAL;
305 }
306
307 WAIT_AES_DMA_READY();
308
309 #ifdef CONFIG_CRYPTO_DEV_POLL_DMA
310
311 outcopy = (u32 *) DEU_DWORD_REORDERING(out_arg, aes_buff_out, BUFFER_OUT, nbytes);
312
313 // polling DMA rx channel
314 while ((dma_device_read (dma_device, (u8 **) &out_dma, NULL)) == 0) {
315 timeout++;
316
317 if (timeout >= 333000) {
318 dma->controlr.EN = 0;
319 CRTCL_SECT_END;
320 printk (KERN_ERR "[%s %s %d]: timeout!!\n", __FILE__, __func__, __LINE__);
321 return; // -EINVAL;
322 }
323 }
324
325 WAIT_AES_DMA_READY();
326
327 AES_MEMORY_COPY(outcopy, out_dma, out_arg, nbytes);
328
329 #else // not working at the moment..
330 CRTCL_SECT_END;
331
332 /* Sleep and wait for Rx finished */
333 DEU_WAIT_EVENT(deu_priv->deu_thread_wait, DEU_EVENT, deu_priv->deu_event_flags);
334
335 CRTCL_SECT_START;
336 #endif
337
338 #endif // dma
339
340 //tc.chen : copy iv_arg back
341 if (mode > 0) {
342 *((u32 *) iv_arg) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg));
343 *((u32 *) iv_arg + 1) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));
344 *((u32 *) iv_arg + 2) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2));
345 *((u32 *) iv_arg + 3) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3));
346 }
347
348 CRTCL_SECT_END;
349 }
350
351 /*!
352 * \fn int ctr_rfc3686_aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)
353 * \ingroup IFX_AES_FUNCTIONS
354 * \brief sets RFC3686 key
355 * \param tfm linux crypto algo transform
356 * \param in_key input key
357 * \param key_len key lengths of 20, 28 and 36 bytes supported; last 4 bytes is nonce
358 * \return 0 - SUCCESS
359 * -EINVAL - bad key length
360 */
361 int ctr_rfc3686_aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)
362 {
363 struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
364 u32 *flags = &tfm->crt_flags;
365
366 printk("ctr_rfc3686_aes_set_key in %s\n", __FILE__);
367
368 memcpy(ctx->nonce, in_key + (key_len - CTR_RFC3686_NONCE_SIZE),
369 CTR_RFC3686_NONCE_SIZE);
370
371 key_len -= CTR_RFC3686_NONCE_SIZE; // remove 4 bytes of nonce
372
373 if (key_len != 16 && key_len != 24 && key_len != 32) {
374 *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
375 return -EINVAL;
376 }
377
378 ctx->key_length = key_len;
379
380 memcpy ((u8 *) (ctx->buf), in_key, key_len);
381
382 return 0;
383 }
384
385 /*! \fn void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode)
386 * \ingroup IFX_AES_FUNCTIONS
387 * \brief main interface with deu hardware in DMA mode
388 * \param ctx_arg crypto algo context
389 * \param out_arg output bytestream
390 * \param in_arg input bytestream
391 * \param iv_arg initialization vector
392 * \param nbytes length of bytestream
393 * \param encdec 1 for encrypt; 0 for decrypt
394 * \param mode operation mode such as ebc, cbc, ctr
395 */
396
397 #ifdef CONFIG_CRYPTO_DEV_DMA
398 void ifx_deu_aes (void *ctx_arg, u8 * out_arg, const u8 * in_arg,
399 u8 * iv_arg, u32 nbytes, int encdec, int mode)
400 {
401 u32 remain = nbytes;
402 u32 inc;
403
404 while (remain > 0)
405 {
406 if (remain >= DEU_MAX_PACKET_SIZE)
407 {
408 inc = DEU_MAX_PACKET_SIZE;
409 }
410 else
411 {
412 inc = remain;
413 }
414
415 remain -= inc;
416
417 ifx_deu_aes_core(ctx_arg, out_arg, in_arg, iv_arg, inc, encdec, mode);
418
419 out_arg += inc;
420 in_arg += inc;
421 }
422
423 }
424 #endif
425
426 //definitions from linux/include/crypto.h:
427 //#define CRYPTO_TFM_MODE_ECB 0x00000001
428 //#define CRYPTO_TFM_MODE_CBC 0x00000002
429 //#define CRYPTO_TFM_MODE_CFB 0x00000004
430 //#define CRYPTO_TFM_MODE_CTR 0x00000008
431 //#define CRYPTO_TFM_MODE_OFB 0x00000010 // not even defined
432 //but hardware definition: 0 ECB 1 CBC 2 OFB 3 CFB 4 CTR
433
434 /*! \fn void ifx_deu_aes_ecb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
435 * \ingroup IFX_AES_FUNCTIONS
436 * \brief sets AES hardware to ECB mode
437 * \param ctx crypto algo context
438 * \param dst output bytestream
439 * \param src input bytestream
440 * \param iv initialization vector
441 * \param nbytes length of bytestream
442 * \param encdec 1 for encrypt; 0 for decrypt
443 * \param inplace not used
444 */
445 void ifx_deu_aes_ecb (void *ctx, uint8_t *dst, const uint8_t *src,
446 uint8_t *iv, size_t nbytes, int encdec, int inplace)
447 {
448 ifx_deu_aes (ctx, dst, src, NULL, nbytes, encdec, 0);
449 }
450
451 /*! \fn void ifx_deu_aes_cbc (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
452 * \ingroup IFX_AES_FUNCTIONS
453 * \brief sets AES hardware to CBC mode
454 * \param ctx crypto algo context
455 * \param dst output bytestream
456 * \param src input bytestream
457 * \param iv initialization vector
458 * \param nbytes length of bytestream
459 * \param encdec 1 for encrypt; 0 for decrypt
460 * \param inplace not used
461 */
462 void ifx_deu_aes_cbc (void *ctx, uint8_t *dst, const uint8_t *src,
463 uint8_t *iv, size_t nbytes, int encdec, int inplace)
464 {
465 ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 1);
466 }
467
468 /*! \fn void ifx_deu_aes_ofb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
469 * \ingroup IFX_AES_FUNCTIONS
470 * \brief sets AES hardware to OFB mode
471 * \param ctx crypto algo context
472 * \param dst output bytestream
473 * \param src input bytestream
474 * \param iv initialization vector
475 * \param nbytes length of bytestream
476 * \param encdec 1 for encrypt; 0 for decrypt
477 * \param inplace not used
478 */
479 void ifx_deu_aes_ofb (void *ctx, uint8_t *dst, const uint8_t *src,
480 uint8_t *iv, size_t nbytes, int encdec, int inplace)
481 {
482 ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 2);
483 }
484
485 /*! \fn void ifx_deu_aes_cfb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
486 * \ingroup IFX_AES_FUNCTIONS
487 * \brief sets AES hardware to CFB mode
488 * \param ctx crypto algo context
489 * \param dst output bytestream
490 * \param src input bytestream
491 * \param iv initialization vector
492 * \param nbytes length of bytestream
493 * \param encdec 1 for encrypt; 0 for decrypt
494 * \param inplace not used
495 */
496 void ifx_deu_aes_cfb (void *ctx, uint8_t *dst, const uint8_t *src,
497 uint8_t *iv, size_t nbytes, int encdec, int inplace)
498 {
499 ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 3);
500 }
501
502 /*! \fn void ifx_deu_aes_ctr (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
503 * \ingroup IFX_AES_FUNCTIONS
504 * \brief sets AES hardware to CTR mode
505 * \param ctx crypto algo context
506 * \param dst output bytestream
507 * \param src input bytestream
508 * \param iv initialization vector
509 * \param nbytes length of bytestream
510 * \param encdec 1 for encrypt; 0 for decrypt
511 * \param inplace not used
512 */
513 void ifx_deu_aes_ctr (void *ctx, uint8_t *dst, const uint8_t *src,
514 uint8_t *iv, size_t nbytes, int encdec, int inplace)
515 {
516 ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 4);
517 }
518
519 /*! \fn void aes_encrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
520 * \ingroup IFX_AES_FUNCTIONS
521 * \brief encrypt AES_BLOCK_SIZE of data
522 * \param tfm linux crypto algo transform
523 * \param out output bytestream
524 * \param in input bytestream
525 */
526 void aes_encrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
527 {
528 struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
529 ifx_deu_aes (ctx, out, in, NULL, AES_BLOCK_SIZE,
530 CRYPTO_DIR_ENCRYPT, 0);
531
532 }
533
534 /*! \fn void aes_decrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
535 * \ingroup IFX_AES_FUNCTIONS
536 * \brief decrypt AES_BLOCK_SIZE of data
537 * \param tfm linux crypto algo transform
538 * \param out output bytestream
539 * \param in input bytestream
540 */
541 void aes_decrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
542 {
543 struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
544 ifx_deu_aes (ctx, out, in, NULL, AES_BLOCK_SIZE,
545 CRYPTO_DIR_DECRYPT, 0);
546 }
547
548 /*
549 * \brief AES function mappings
550 */
551 struct crypto_alg ifxdeu_aes_alg = {
552 .cra_name = "aes",
553 .cra_driver_name = "ifxdeu-aes",
554 .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
555 .cra_blocksize = AES_BLOCK_SIZE,
556 .cra_ctxsize = sizeof(struct aes_ctx),
557 .cra_module = THIS_MODULE,
558 .cra_list = LIST_HEAD_INIT(ifxdeu_aes_alg.cra_list),
559 .cra_u = {
560 .cipher = {
561 .cia_min_keysize = AES_MIN_KEY_SIZE,
562 .cia_max_keysize = AES_MAX_KEY_SIZE,
563 .cia_setkey = aes_set_key,
564 .cia_encrypt = aes_encrypt,
565 .cia_decrypt = aes_decrypt,
566 }
567 }
568 };
569
570 /*! \fn int ecb_aes_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
571 * \ingroup IFX_AES_FUNCTIONS
572 * \brief ECB AES encrypt using linux crypto blkcipher
573 * \param desc blkcipher descriptor
574 * \param dst output scatterlist
575 * \param src input scatterlist
576 * \param nbytes data size in bytes
577 * \return err
578 */
579 int ecb_aes_encrypt(struct blkcipher_desc *desc,
580 struct scatterlist *dst, struct scatterlist *src,
581 unsigned int nbytes)
582 {
583 struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
584 struct blkcipher_walk walk;
585 int err;
586
587 blkcipher_walk_init(&walk, dst, src, nbytes);
588 err = blkcipher_walk_virt(desc, &walk);
589
590 while ((nbytes = walk.nbytes)) {
591 nbytes -= (nbytes % AES_BLOCK_SIZE);
592 ifx_deu_aes_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr,
593 NULL, nbytes, CRYPTO_DIR_ENCRYPT, 0);
594 nbytes &= AES_BLOCK_SIZE - 1;
595 err = blkcipher_walk_done(desc, &walk, nbytes);
596 }
597
598 return err;
599 }
600
601 /*! \fn int ecb_aes_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
602 * \ingroup IFX_AES_FUNCTIONS
603 * \brief ECB AES decrypt using linux crypto blkcipher
604 * \param desc blkcipher descriptor
605 * \param dst output scatterlist
606 * \param src input scatterlist
607 * \param nbytes data size in bytes
608 * \return err
609 */
610 int ecb_aes_decrypt(struct blkcipher_desc *desc,
611 struct scatterlist *dst, struct scatterlist *src,
612 unsigned int nbytes)
613 {
614 struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
615 struct blkcipher_walk walk;
616 int err;
617
618 blkcipher_walk_init(&walk, dst, src, nbytes);
619 err = blkcipher_walk_virt(desc, &walk);
620
621 while ((nbytes = walk.nbytes)) {
622 nbytes -= (nbytes % AES_BLOCK_SIZE);
623 ifx_deu_aes_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr,
624 NULL, nbytes, CRYPTO_DIR_DECRYPT, 0);
625 nbytes &= AES_BLOCK_SIZE - 1;
626 err = blkcipher_walk_done(desc, &walk, nbytes);
627 }
628
629 return err;
630 }
631
632 /*
633 * \brief AES function mappings
634 */
635 struct crypto_alg ifxdeu_ecb_aes_alg = {
636 .cra_name = "ecb(aes)",
637 .cra_driver_name = "ifxdeu-ecb(aes)",
638 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
639 .cra_blocksize = AES_BLOCK_SIZE,
640 .cra_ctxsize = sizeof(struct aes_ctx),
641 .cra_type = &crypto_blkcipher_type,
642 .cra_module = THIS_MODULE,
643 .cra_list = LIST_HEAD_INIT(ifxdeu_ecb_aes_alg.cra_list),
644 .cra_u = {
645 .blkcipher = {
646 .min_keysize = AES_MIN_KEY_SIZE,
647 .max_keysize = AES_MAX_KEY_SIZE,
648 .setkey = aes_set_key,
649 .encrypt = ecb_aes_encrypt,
650 .decrypt = ecb_aes_decrypt,
651 }
652 }
653 };
654
655
656 /*! \fn int cbc_aes_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
657 * \ingroup IFX_AES_FUNCTIONS
658 * \brief CBC AES encrypt using linux crypto blkcipher
659 * \param desc blkcipher descriptor
660 * \param dst output scatterlist
661 * \param src input scatterlist
662 * \param nbytes data size in bytes
663 * \return err
664 */
665 int cbc_aes_encrypt(struct blkcipher_desc *desc,
666 struct scatterlist *dst, struct scatterlist *src,
667 unsigned int nbytes)
668 {
669 struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
670 struct blkcipher_walk walk;
671 int err;
672
673 blkcipher_walk_init(&walk, dst, src, nbytes);
674 err = blkcipher_walk_virt(desc, &walk);
675
676 while ((nbytes = walk.nbytes)) {
677 u8 *iv = walk.iv;
678 nbytes -= (nbytes % AES_BLOCK_SIZE);
679 ifx_deu_aes_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
680 iv, nbytes, CRYPTO_DIR_ENCRYPT, 0);
681 nbytes &= AES_BLOCK_SIZE - 1;
682 err = blkcipher_walk_done(desc, &walk, nbytes);
683 }
684
685 return err;
686 }
687
688 /*! \fn int cbc_aes_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
689 * \ingroup IFX_AES_FUNCTIONS
690 * \brief CBC AES decrypt using linux crypto blkcipher
691 * \param desc blkcipher descriptor
692 * \param dst output scatterlist
693 * \param src input scatterlist
694 * \param nbytes data size in bytes
695 * \return err
696 */
697 int cbc_aes_decrypt(struct blkcipher_desc *desc,
698 struct scatterlist *dst, struct scatterlist *src,
699 unsigned int nbytes)
700 {
701 struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
702 struct blkcipher_walk walk;
703 int err;
704
705 blkcipher_walk_init(&walk, dst, src, nbytes);
706 err = blkcipher_walk_virt(desc, &walk);
707
708 while ((nbytes = walk.nbytes)) {
709 u8 *iv = walk.iv;
710 nbytes -= (nbytes % AES_BLOCK_SIZE);
711 ifx_deu_aes_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
712 iv, nbytes, CRYPTO_DIR_DECRYPT, 0);
713 nbytes &= AES_BLOCK_SIZE - 1;
714 err = blkcipher_walk_done(desc, &walk, nbytes);
715 }
716
717 return err;
718 }
719
720 /*
721 * \brief AES function mappings
722 */
723 struct crypto_alg ifxdeu_cbc_aes_alg = {
724 .cra_name = "cbc(aes)",
725 .cra_driver_name = "ifxdeu-cbc(aes)",
726 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
727 .cra_blocksize = AES_BLOCK_SIZE,
728 .cra_ctxsize = sizeof(struct aes_ctx),
729 .cra_type = &crypto_blkcipher_type,
730 .cra_module = THIS_MODULE,
731 .cra_list = LIST_HEAD_INIT(ifxdeu_cbc_aes_alg.cra_list),
732 .cra_u = {
733 .blkcipher = {
734 .min_keysize = AES_MIN_KEY_SIZE,
735 .max_keysize = AES_MAX_KEY_SIZE,
736 .ivsize = AES_BLOCK_SIZE,
737 .setkey = aes_set_key,
738 .encrypt = cbc_aes_encrypt,
739 .decrypt = cbc_aes_decrypt,
740 }
741 }
742 };
743
744
745 /*! \fn int ctr_basic_aes_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
746 * \ingroup IFX_AES_FUNCTIONS
747 * \brief Counter mode AES encrypt using linux crypto blkcipher
748 * \param desc blkcipher descriptor
749 * \param dst output scatterlist
750 * \param src input scatterlist
751 * \param nbytes data size in bytes
752 * \return err
753 */
754 int ctr_basic_aes_encrypt(struct blkcipher_desc *desc,
755 struct scatterlist *dst, struct scatterlist *src,
756 unsigned int nbytes)
757 {
758 struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
759 struct blkcipher_walk walk;
760 int err;
761
762 blkcipher_walk_init(&walk, dst, src, nbytes);
763 err = blkcipher_walk_virt(desc, &walk);
764
765 while ((nbytes = walk.nbytes)) {
766 u8 *iv = walk.iv;
767 nbytes -= (nbytes % AES_BLOCK_SIZE);
768 ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
769 iv, nbytes, CRYPTO_DIR_ENCRYPT, 0);
770 nbytes &= AES_BLOCK_SIZE - 1;
771 err = blkcipher_walk_done(desc, &walk, nbytes);
772 }
773
774 return err;
775 }
776
777 /*! \fn int ctr_basic_aes_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
778 * \ingroup IFX_AES_FUNCTIONS
779 * \brief Counter mode AES decrypt using linux crypto blkcipher
780 * \param desc blkcipher descriptor
781 * \param dst output scatterlist
782 * \param src input scatterlist
783 * \param nbytes data size in bytes
784 * \return err
785 */
786 int ctr_basic_aes_decrypt(struct blkcipher_desc *desc,
787 struct scatterlist *dst, struct scatterlist *src,
788 unsigned int nbytes)
789 {
790 struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
791 struct blkcipher_walk walk;
792 int err;
793
794 blkcipher_walk_init(&walk, dst, src, nbytes);
795 err = blkcipher_walk_virt(desc, &walk);
796
797 while ((nbytes = walk.nbytes)) {
798 u8 *iv = walk.iv;
799 nbytes -= (nbytes % AES_BLOCK_SIZE);
800 ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
801 iv, nbytes, CRYPTO_DIR_DECRYPT, 0);
802 nbytes &= AES_BLOCK_SIZE - 1;
803 err = blkcipher_walk_done(desc, &walk, nbytes);
804 }
805
806 return err;
807 }
808
809 /*
810 * \brief AES function mappings
811 */
812 struct crypto_alg ifxdeu_ctr_basic_aes_alg = {
813 .cra_name = "ctr(aes)",
814 .cra_driver_name = "ifxdeu-ctr(aes)",
815 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
816 .cra_blocksize = AES_BLOCK_SIZE,
817 .cra_ctxsize = sizeof(struct aes_ctx),
818 .cra_type = &crypto_blkcipher_type,
819 .cra_module = THIS_MODULE,
820 .cra_list = LIST_HEAD_INIT(ifxdeu_ctr_basic_aes_alg.cra_list),
821 .cra_u = {
822 .blkcipher = {
823 .min_keysize = AES_MIN_KEY_SIZE,
824 .max_keysize = AES_MAX_KEY_SIZE,
825 .ivsize = AES_BLOCK_SIZE,
826 .setkey = aes_set_key,
827 .encrypt = ctr_basic_aes_encrypt,
828 .decrypt = ctr_basic_aes_decrypt,
829 }
830 }
831 };
832
833
834 /*! \fn int ctr_rfc3686_aes_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
835 * \ingroup IFX_AES_FUNCTIONS
836 * \brief Counter mode AES (rfc3686) encrypt using linux crypto blkcipher
837 * \param desc blkcipher descriptor
838 * \param dst output scatterlist
839 * \param src input scatterlist
840 * \param nbytes data size in bytes
841 * \return err
842 */
843 int ctr_rfc3686_aes_encrypt(struct blkcipher_desc *desc,
844 struct scatterlist *dst, struct scatterlist *src,
845 unsigned int nbytes)
846 {
847 struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
848 struct blkcipher_walk walk;
849 int err;
850 u8 rfc3686_iv[16];
851
852 blkcipher_walk_init(&walk, dst, src, nbytes);
853 err = blkcipher_walk_virt(desc, &walk);
854
855 /* set up counter block */
856 memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
857 memcpy(rfc3686_iv + CTR_RFC3686_NONCE_SIZE, walk.iv, CTR_RFC3686_IV_SIZE);
858
859 /* initialize counter portion of counter block */
860 *(__be32 *)(rfc3686_iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
861 cpu_to_be32(1);
862
863 while ((nbytes = walk.nbytes)) {
864 nbytes -= (nbytes % AES_BLOCK_SIZE);
865 ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
866 rfc3686_iv, nbytes, CRYPTO_DIR_ENCRYPT, 0);
867 nbytes &= AES_BLOCK_SIZE - 1;
868 err = blkcipher_walk_done(desc, &walk, nbytes);
869 }
870
871 return err;
872 }
873
874 /*! \fn int ctr_rfc3686_aes_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
875 * \ingroup IFX_AES_FUNCTIONS
876 * \brief Counter mode AES (rfc3686) decrypt using linux crypto blkcipher
877 * \param desc blkcipher descriptor
878 * \param dst output scatterlist
879 * \param src input scatterlist
880 * \param nbytes data size in bytes
881 * \return err
882 */
883 int ctr_rfc3686_aes_decrypt(struct blkcipher_desc *desc,
884 struct scatterlist *dst, struct scatterlist *src,
885 unsigned int nbytes)
886 {
887 struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
888 struct blkcipher_walk walk;
889 int err;
890 u8 rfc3686_iv[16];
891
892 blkcipher_walk_init(&walk, dst, src, nbytes);
893 err = blkcipher_walk_virt(desc, &walk);
894
895 /* set up counter block */
896 memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
897 memcpy(rfc3686_iv + CTR_RFC3686_NONCE_SIZE, walk.iv, CTR_RFC3686_IV_SIZE);
898
899 /* initialize counter portion of counter block */
900 *(__be32 *)(rfc3686_iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
901 cpu_to_be32(1);
902
903 while ((nbytes = walk.nbytes)) {
904 nbytes -= (nbytes % AES_BLOCK_SIZE);
905 ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
906 rfc3686_iv, nbytes, CRYPTO_DIR_DECRYPT, 0);
907 nbytes &= AES_BLOCK_SIZE - 1;
908 err = blkcipher_walk_done(desc, &walk, nbytes);
909 }
910
911 return err;
912 }
913
914 /*
915 * \brief AES function mappings
916 */
917 struct crypto_alg ifxdeu_ctr_rfc3686_aes_alg = {
918 .cra_name = "rfc3686(ctr(aes))",
919 .cra_driver_name = "ifxdeu-ctr-rfc3686(aes)",
920 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
921 .cra_blocksize = AES_BLOCK_SIZE,
922 .cra_ctxsize = sizeof(struct aes_ctx),
923 .cra_type = &crypto_blkcipher_type,
924 .cra_module = THIS_MODULE,
925 .cra_list = LIST_HEAD_INIT(ifxdeu_ctr_rfc3686_aes_alg.cra_list),
926 .cra_u = {
927 .blkcipher = {
928 .min_keysize = AES_MIN_KEY_SIZE,
929 .max_keysize = CTR_RFC3686_MAX_KEY_SIZE,
930 .ivsize = CTR_RFC3686_IV_SIZE,
931 .setkey = ctr_rfc3686_aes_set_key,
932 .encrypt = ctr_rfc3686_aes_encrypt,
933 .decrypt = ctr_rfc3686_aes_decrypt,
934 }
935 }
936 };
937
938
939 /*! \fn int __init ifxdeu_init_aes (void)
940 * \ingroup IFX_AES_FUNCTIONS
941 * \brief function to initialize AES driver
942 * \return ret
943 */
944 int __init ifxdeu_init_aes (void)
945 {
946 int ret;
947
948 if ((ret = crypto_register_alg(&ifxdeu_aes_alg)))
949 goto aes_err;
950
951 if ((ret = crypto_register_alg(&ifxdeu_ecb_aes_alg)))
952 goto ecb_aes_err;
953
954 if ((ret = crypto_register_alg(&ifxdeu_cbc_aes_alg)))
955 goto cbc_aes_err;
956
957 if ((ret = crypto_register_alg(&ifxdeu_ctr_basic_aes_alg)))
958 goto ctr_basic_aes_err;
959
960 if ((ret = crypto_register_alg(&ifxdeu_ctr_rfc3686_aes_alg)))
961 goto ctr_rfc3686_aes_err;
962
963 aes_chip_init ();
964
965 CRTCL_SECT_INIT;
966
967 #ifdef CONFIG_CRYPTO_DEV_DMA
968 if (ALLOCATE_MEMORY(BUFFER_IN, AES_ALGO) < 0) {
969 printk(KERN_ERR "[%s %s %d]: malloc memory fail!\n", __FILE__, __func__, __LINE__);
970 goto ctr_rfc3686_aes_err;
971 }
972 if (ALLOCATE_MEMORY(BUFFER_OUT, AES_ALGO) < 0) {
973 printk(KERN_ERR "[%s %s %d]: malloc memory fail!\n", __FILE__, __func__, __LINE__);
974 goto ctr_rfc3686_aes_err;
975 }
976 #endif
977
978 printk (KERN_NOTICE "IFX DEU AES initialized %s.\n", disable_deudma ? "" : " (DMA)");
979 return ret;
980
981 ctr_rfc3686_aes_err:
982 crypto_unregister_alg(&ifxdeu_ctr_rfc3686_aes_alg);
983 printk (KERN_ERR "IFX ctr_rfc3686_aes initialization failed!\n");
984 return ret;
985 ctr_basic_aes_err:
986 crypto_unregister_alg(&ifxdeu_ctr_basic_aes_alg);
987 printk (KERN_ERR "IFX ctr_basic_aes initialization failed!\n");
988 return ret;
989 cbc_aes_err:
990 crypto_unregister_alg(&ifxdeu_cbc_aes_alg);
991 printk (KERN_ERR "IFX cbc_aes initialization failed!\n");
992 return ret;
993 ecb_aes_err:
994 crypto_unregister_alg(&ifxdeu_ecb_aes_alg);
995 printk (KERN_ERR "IFX aes initialization failed!\n");
996 return ret;
997 aes_err:
998 printk(KERN_ERR "IFX DEU AES initialization failed!\n");
999 return ret;
1000 }
1001
1002 /*! \fn void __exit ifxdeu_fini_aes (void)
1003 * \ingroup IFX_AES_FUNCTIONS
1004 * \brief unregister aes driver
1005 */
1006 void __exit ifxdeu_fini_aes (void)
1007 {
1008 crypto_unregister_alg (&ifxdeu_aes_alg);
1009 crypto_unregister_alg (&ifxdeu_ecb_aes_alg);
1010 crypto_unregister_alg (&ifxdeu_cbc_aes_alg);
1011 crypto_unregister_alg (&ifxdeu_ctr_basic_aes_alg);
1012 crypto_unregister_alg (&ifxdeu_ctr_rfc3686_aes_alg);
1013
1014 #ifdef CONFIG_CRYPTO_DEV_DMA
1015 FREE_MEMORY(aes_buff_in);
1016 FREE_MEMORY(aes_buff_out);
1017 #endif
1018
1019 }
1020
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