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[openwrt/staging/dedeckeh.git] / target / linux / generic-2.6 / files / drivers / ssb / driver_pcicore.c
1 /*
2 * Sonics Silicon Backplane
3 * Broadcom PCI-core driver
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11 #include <linux/ssb/ssb.h>
12 #include <linux/pci.h>
13 #include <linux/delay.h>
14
15 #include "ssb_private.h"
16
17
18 static inline
19 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
20 {
21 return ssb_read32(pc->dev, offset);
22 }
23
24 static inline
25 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
26 {
27 ssb_write32(pc->dev, offset, value);
28 }
29
30 /**************************************************
31 * Code for hostmode operation.
32 **************************************************/
33
34 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
35
36 #include <asm/paccess.h>
37 /* Read the bus and catch bus exceptions. This is MIPS specific. */
38 #define mips_busprobe(val, addr) get_dbe((val), (addr))
39
40 /* Assume one-hot slot wiring */
41 #define SSB_PCI_SLOT_MAX 16
42
43 /* Global lock is OK, as we won't have more than one extpci anyway. */
44 static DEFINE_SPINLOCK(cfgspace_lock);
45 /* Core to access the external PCI config space. Can only have one. */
46 static struct ssb_pcicore *extpci_core;
47
48 u32 pci_iobase = 0x100;
49 u32 pci_membase = SSB_PCI_DMA;
50
51 int pcibios_plat_dev_init(struct pci_dev *d)
52 {
53 struct resource *res;
54 int pos, size;
55 u32 *base;
56
57 printk("PCI: Fixing up device %s\n", pci_name(d));
58
59 /* Fix up resource bases */
60 for (pos = 0; pos < 6; pos++) {
61 res = &d->resource[pos];
62 base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
63 if (res->end) {
64 size = res->end - res->start + 1;
65 if (*base & (size - 1))
66 *base = (*base + size) & ~(size - 1);
67 res->start = *base;
68 res->end = res->start + size - 1;
69 *base += size;
70 pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
71 }
72 /* Fix up PCI bridge BAR0 only */
73 if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
74 break;
75 }
76 /* Fix up interrupt lines */
77 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
78 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
79
80 return 0;
81 }
82
83 static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
84 {
85 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
86 return;
87
88 printk("PCI: fixing up bridge\n");
89
90 /* Enable PCI bridge bus mastering and memory space */
91 pci_set_master(dev);
92 pcibios_enable_device(dev, ~0);
93
94 /* Enable PCI bridge BAR1 prefetch and burst */
95 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
96 }
97 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
98
99 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
100 {
101 return ssb_mips_irq(extpci_core->dev) + 2;
102 }
103
104 static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
105 unsigned int bus, unsigned int dev,
106 unsigned int func, unsigned int off)
107 {
108 u32 addr = 0;
109 u32 tmp;
110
111 if (unlikely(pc->cardbusmode && dev > 1))
112 goto out;
113 if (bus == 0) {
114 /* Type 0 transaction */
115 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
116 goto out;
117 /* Slide the window */
118 tmp = SSB_PCICORE_SBTOPCI_CFG0;
119 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
120 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
121 /* Calculate the address */
122 addr = SSB_PCI_CFG;
123 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
124 addr |= (func << 8);
125 addr |= (off & ~3);
126 } else {
127 /* Type 1 transaction */
128 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
129 SSB_PCICORE_SBTOPCI_CFG1);
130 /* Calculate the address */
131 addr = SSB_PCI_CFG;
132 addr |= (bus << 16);
133 addr |= (dev << 11);
134 addr |= (func << 8);
135 addr |= (off & ~3);
136 }
137 out:
138 return addr;
139 }
140
141 static int ssb_extpci_read_config(struct ssb_pcicore *pc,
142 unsigned int bus, unsigned int dev,
143 unsigned int func, unsigned int off,
144 void *buf, int len)
145 {
146 int err = -EINVAL;
147 u32 addr, val;
148 void __iomem *mmio;
149
150 assert(pc->hostmode);
151 if (unlikely(len != 1 && len != 2 && len != 4))
152 goto out;
153 addr = get_cfgspace_addr(pc, bus, dev, func, off);
154 if (unlikely(!addr))
155 goto out;
156 err = -ENOMEM;
157 mmio = ioremap_nocache(addr, len);
158 if (!mmio)
159 goto out;
160
161 if (mips_busprobe(val, (u32 *) mmio)) {
162 val = 0xffffffff;
163 goto unmap;
164 }
165
166 val = readl(mmio);
167 val >>= (8 * (off & 3));
168
169 switch (len) {
170 case 1:
171 *((u8 *)buf) = (u8)val;
172 break;
173 case 2:
174 *((u16 *)buf) = (u16)val;
175 break;
176 case 4:
177 *((u32 *)buf) = (u32)val;
178 break;
179 }
180 err = 0;
181 unmap:
182 iounmap(mmio);
183 out:
184 return err;
185 }
186
187 static int ssb_extpci_write_config(struct ssb_pcicore *pc,
188 unsigned int bus, unsigned int dev,
189 unsigned int func, unsigned int off,
190 const void *buf, int len)
191 {
192 int err = -EINVAL;
193 u32 addr, val = 0;
194 void __iomem *mmio;
195
196 assert(pc->hostmode);
197 if (unlikely(len != 1 && len != 2 && len != 4))
198 goto out;
199 addr = get_cfgspace_addr(pc, bus, dev, func, off);
200 if (unlikely(!addr))
201 goto out;
202 err = -ENOMEM;
203 mmio = ioremap_nocache(addr, len);
204 if (!mmio)
205 goto out;
206
207 if (mips_busprobe(val, (u32 *) mmio)) {
208 val = 0xffffffff;
209 goto unmap;
210 }
211
212 switch (len) {
213 case 1:
214 val = readl(mmio);
215 val &= ~(0xFF << (8 * (off & 3)));
216 val |= *((const u8 *)buf) << (8 * (off & 3));
217 break;
218 case 2:
219 val = readl(mmio);
220 val &= ~(0xFFFF << (8 * (off & 3)));
221 val |= *((const u16 *)buf) << (8 * (off & 3));
222 break;
223 case 4:
224 val = *((const u32 *)buf);
225 break;
226 }
227 writel(*((const u32 *)buf), mmio);
228
229 err = 0;
230 unmap:
231 iounmap(mmio);
232 out:
233 return err;
234 }
235
236 static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
237 int reg, int size, u32 *val)
238 {
239 unsigned long flags;
240 int err;
241
242 spin_lock_irqsave(&cfgspace_lock, flags);
243 err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
244 PCI_FUNC(devfn), reg, val, size);
245 spin_unlock_irqrestore(&cfgspace_lock, flags);
246
247 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
248 }
249
250 static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
251 int reg, int size, u32 val)
252 {
253 unsigned long flags;
254 int err;
255
256 spin_lock_irqsave(&cfgspace_lock, flags);
257 err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
258 PCI_FUNC(devfn), reg, &val, size);
259 spin_unlock_irqrestore(&cfgspace_lock, flags);
260
261 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
262 }
263
264 static struct pci_ops ssb_pcicore_pciops = {
265 .read = ssb_pcicore_read_config,
266 .write = ssb_pcicore_write_config,
267 };
268
269 static struct resource ssb_pcicore_mem_resource = {
270 .name = "SSB PCIcore external memory",
271 .start = SSB_PCI_DMA,
272 .end = (u32)SSB_PCI_DMA + (u32)SSB_PCI_DMA_SZ - 1,
273 .flags = IORESOURCE_MEM,
274 };
275
276 static struct resource ssb_pcicore_io_resource = {
277 .name = "SSB PCIcore external I/O",
278 .start = 0x100,
279 .end = 0x7FF,
280 .flags = IORESOURCE_IO,
281 };
282
283 static struct pci_controller ssb_pcicore_controller = {
284 .pci_ops = &ssb_pcicore_pciops,
285 .io_resource = &ssb_pcicore_io_resource,
286 .mem_resource = &ssb_pcicore_mem_resource,
287 .mem_offset = 0x24000000,
288 };
289
290 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
291 {
292 u32 val;
293
294 if (extpci_core) {
295 WARN_ON(1);
296 return;
297 }
298 extpci_core = pc;
299
300 ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
301 /* Reset devices on the external PCI bus */
302 val = SSB_PCICORE_CTL_RST_OE;
303 val |= SSB_PCICORE_CTL_CLK_OE;
304 pcicore_write32(pc, SSB_PCICORE_CTL, val);
305 val |= SSB_PCICORE_CTL_CLK; /* Clock on */
306 pcicore_write32(pc, SSB_PCICORE_CTL, val);
307 udelay(150);
308 val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
309 pcicore_write32(pc, SSB_PCICORE_CTL, val);
310 udelay(1);
311
312 //TODO cardbus mode
313
314 /* 64MB I/O window */
315 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
316 SSB_PCICORE_SBTOPCI_IO);
317 /* 64MB config space */
318 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
319 SSB_PCICORE_SBTOPCI_CFG0);
320 /* 1GB memory window */
321 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
322 SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
323
324 /* Enable PCI bridge BAR0 prefetch and burst */
325 val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
326 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
327 /* Clear error conditions */
328 val = 0;
329 ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
330
331 /* Enable PCI interrupts */
332 pcicore_write32(pc, SSB_PCICORE_IMASK,
333 SSB_PCICORE_IMASK_INTA);
334
335 /* Ok, ready to run, register it to the system.
336 * The following needs change, if we want to port hostmode
337 * to non-MIPS platform. */
338 set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
339 register_pci_controller(&ssb_pcicore_controller);
340 }
341
342 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
343 {
344 struct ssb_bus *bus = pc->dev->bus;
345 u16 chipid_top;
346 u32 tmp;
347
348 chipid_top = (bus->chip_id & 0xFF00);
349 if (chipid_top != 0x4700 &&
350 chipid_top != 0x5300)
351 return 0;
352
353 if (bus->sprom.r1.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
354 return 0;
355
356 /* The 200-pin BCM4712 package does not bond out PCI. Even when
357 * PCI is bonded out, some boards may leave the pins floating. */
358 if (bus->chip_id == 0x4712) {
359 if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
360 return 0;
361 if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
362 return 0;
363 }
364 if (bus->chip_id == 0x5350)
365 return 0;
366
367 return !mips_busprobe(tmp, (u32 *) (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
368 }
369 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
370
371
372 /**************************************************
373 * Generic and Clientmode operation code.
374 **************************************************/
375
376 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
377 {
378 /* Disable PCI interrupts. */
379 ssb_write32(pc->dev, SSB_INTVEC, 0);
380 }
381
382 void ssb_pcicore_init(struct ssb_pcicore *pc)
383 {
384 struct ssb_device *dev = pc->dev;
385 struct ssb_bus *bus;
386
387 if (!dev)
388 return;
389 bus = dev->bus;
390 if (!ssb_device_is_enabled(dev))
391 ssb_device_enable(dev, 0);
392
393 #ifdef CONFIG_SSB_PCICORE_HOSTMODE
394 pc->hostmode = pcicore_is_in_hostmode(pc);
395 if (pc->hostmode)
396 ssb_pcicore_init_hostmode(pc);
397 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
398 if (!pc->hostmode)
399 ssb_pcicore_init_clientmode(pc);
400 }
401
402 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
403 {
404 pcicore_write32(pc, 0x130, address);
405 return pcicore_read32(pc, 0x134);
406 }
407
408 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
409 {
410 pcicore_write32(pc, 0x130, address);
411 pcicore_write32(pc, 0x134, data);
412 }
413
414 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
415 u8 address, u16 data)
416 {
417 const u16 mdio_control = 0x128;
418 const u16 mdio_data = 0x12C;
419 u32 v;
420 int i;
421
422 v = 0x80; /* Enable Preamble Sequence */
423 v |= 0x2; /* MDIO Clock Divisor */
424 pcicore_write32(pc, mdio_control, v);
425
426 v = (1 << 30); /* Start of Transaction */
427 v |= (1 << 28); /* Write Transaction */
428 v |= (1 << 17); /* Turnaround */
429 v |= (u32)device << 22;
430 v |= (u32)address << 18;
431 v |= data;
432 pcicore_write32(pc, mdio_data, v);
433 udelay(10);
434 for (i = 0; i < 10; i++) {
435 v = pcicore_read32(pc, mdio_control);
436 if (v & 0x100 /* Trans complete */)
437 break;
438 msleep(1);
439 }
440 pcicore_write32(pc, mdio_control, 0);
441 }
442
443 static void ssb_broadcast_value(struct ssb_device *dev,
444 u32 address, u32 data)
445 {
446 /* This is used for both, PCI and ChipCommon core, so be careful. */
447 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
448 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
449
450 ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
451 ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
452 ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
453 ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
454 }
455
456 static void ssb_commit_settings(struct ssb_bus *bus)
457 {
458 struct ssb_device *dev;
459
460 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
461 assert(dev);
462 /* This forces an update of the cached registers. */
463 ssb_broadcast_value(dev, 0xFD8, 0);
464 }
465
466 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
467 struct ssb_device *dev)
468 {
469 struct ssb_device *pdev = pc->dev;
470 struct ssb_bus *bus;
471 int err = 0;
472 u32 tmp;
473
474 might_sleep();
475
476 if (!pdev)
477 goto out;
478 bus = pdev->bus;
479
480 /* Enable interrupts for this device. */
481 if (bus->host_pci &&
482 ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
483 u32 coremask;
484
485 /* Calculate the "coremask" for the device. */
486 coremask = (1 << dev->core_index);
487
488 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
489 if (err)
490 goto out;
491 tmp |= coremask << 8;
492 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
493 if (err)
494 goto out;
495 } else {
496 u32 intvec;
497
498 intvec = ssb_read32(pdev, SSB_INTVEC);
499 tmp = ssb_read32(dev, SSB_TPSFLAG);
500 tmp &= SSB_TPSFLAG_BPFLAG;
501 intvec |= tmp;
502 ssb_write32(pdev, SSB_INTVEC, intvec);
503 }
504
505 /* Setup PCIcore operation. */
506 if (pc->setup_done)
507 goto out;
508 if (pdev->id.coreid == SSB_DEV_PCI) {
509 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
510 tmp |= SSB_PCICORE_SBTOPCI_PREF;
511 tmp |= SSB_PCICORE_SBTOPCI_BURST;
512 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
513
514 if (pdev->id.revision < 5) {
515 tmp = ssb_read32(pdev, SSB_IMCFGLO);
516 tmp &= ~SSB_IMCFGLO_SERTO;
517 tmp |= 2;
518 tmp &= ~SSB_IMCFGLO_REQTO;
519 tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
520 ssb_write32(pdev, SSB_IMCFGLO, tmp);
521 ssb_commit_settings(bus);
522 } else if (pdev->id.revision >= 11) {
523 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
524 tmp |= SSB_PCICORE_SBTOPCI_MRM;
525 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
526 }
527 } else {
528 assert(pdev->id.coreid == SSB_DEV_PCIE);
529 //TODO: Better make defines for all these magic PCIE values.
530 if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
531 /* TLP Workaround register. */
532 tmp = ssb_pcie_read(pc, 0x4);
533 tmp |= 0x8;
534 ssb_pcie_write(pc, 0x4, tmp);
535 }
536 if (pdev->id.revision == 0) {
537 const u8 serdes_rx_device = 0x1F;
538
539 ssb_pcie_mdio_write(pc, serdes_rx_device,
540 2 /* Timer */, 0x8128);
541 ssb_pcie_mdio_write(pc, serdes_rx_device,
542 6 /* CDR */, 0x0100);
543 ssb_pcie_mdio_write(pc, serdes_rx_device,
544 7 /* CDR BW */, 0x1466);
545 } else if (pdev->id.revision == 1) {
546 /* DLLP Link Control register. */
547 tmp = ssb_pcie_read(pc, 0x100);
548 tmp |= 0x40;
549 ssb_pcie_write(pc, 0x100, tmp);
550 }
551 }
552 pc->setup_done = 1;
553 out:
554 return err;
555 }
556 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);
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