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mediatek: add support for Ubiquiti UniFi 6 LR v3
[openwrt/staging/dangole.git] / target / linux / generic / pending-6.1 / 737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch
1 From 661bacf4363ca68939c15e20056b5f72fbd034e7 Mon Sep 17 00:00:00 2001
2 From: Lorenzo Bianconi <lorenzo@kernel.org>
3 Date: Sat, 25 Feb 2023 00:08:24 +0100
4 Subject: [PATCH 6/7] net: ethernet: mtk_eth_soc: add support for MT7988 SoC
5
6 Introduce support for ethernet chip available in MT7988 SoC to
7 mtk_eth_soc driver.
8 ---
9 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 153 ++++++++++++++--
10 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 193 ++++++++++++++------
11 2 files changed, 279 insertions(+), 67 deletions(-)
12
13 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
14 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
15 @@ -152,6 +152,54 @@ static const struct mtk_reg_map mt7986_r
16 .pse_oq_sta = 0x01a0,
17 };
18
19 +static const struct mtk_reg_map mt7988_reg_map = {
20 + .tx_irq_mask = 0x461c,
21 + .tx_irq_status = 0x4618,
22 + .pdma = {
23 + .rx_ptr = 0x6900,
24 + .rx_cnt_cfg = 0x6904,
25 + .pcrx_ptr = 0x6908,
26 + .glo_cfg = 0x6a04,
27 + .rst_idx = 0x6a08,
28 + .delay_irq = 0x6a0c,
29 + .irq_status = 0x6a20,
30 + .irq_mask = 0x6a28,
31 + .adma_rx_dbg0 = 0x6a38,
32 + .int_grp = 0x6a50,
33 + },
34 + .qdma = {
35 + .qtx_cfg = 0x4400,
36 + .qtx_sch = 0x4404,
37 + .rx_ptr = 0x4500,
38 + .rx_cnt_cfg = 0x4504,
39 + .qcrx_ptr = 0x4508,
40 + .glo_cfg = 0x4604,
41 + .rst_idx = 0x4608,
42 + .delay_irq = 0x460c,
43 + .fc_th = 0x4610,
44 + .int_grp = 0x4620,
45 + .hred = 0x4644,
46 + .ctx_ptr = 0x4700,
47 + .dtx_ptr = 0x4704,
48 + .crx_ptr = 0x4710,
49 + .drx_ptr = 0x4714,
50 + .fq_head = 0x4720,
51 + .fq_tail = 0x4724,
52 + .fq_count = 0x4728,
53 + .fq_blen = 0x472c,
54 + .tx_sch_rate = 0x4798,
55 + },
56 + .gdm1_cnt = 0x1c00,
57 + .gdma_to_ppe = 0x3333,
58 + .ppe_base = 0x2200,
59 + .wdma_base = {
60 + [0] = 0x4800,
61 + [1] = 0x4c00,
62 + },
63 + .pse_iq_sta = 0x0180,
64 + .pse_oq_sta = 0x01a0,
65 +};
66 +
67 /* strings used by ethtool */
68 static const struct mtk_ethtool_stats {
69 char str[ETH_GSTRING_LEN];
70 @@ -179,10 +227,54 @@ static const struct mtk_ethtool_stats {
71 };
72
73 static const char * const mtk_clks_source_name[] = {
74 - "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll",
75 - "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb",
76 - "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb",
77 - "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1"
78 + "ethif",
79 + "sgmiitop",
80 + "esw",
81 + "gp0",
82 + "gp1",
83 + "gp2",
84 + "gp3",
85 + "xgp1",
86 + "xgp2",
87 + "xgp3",
88 + "crypto",
89 + "fe",
90 + "trgpll",
91 + "sgmii_tx250m",
92 + "sgmii_rx250m",
93 + "sgmii_cdr_ref",
94 + "sgmii_cdr_fb",
95 + "sgmii2_tx250m",
96 + "sgmii2_rx250m",
97 + "sgmii2_cdr_ref",
98 + "sgmii2_cdr_fb",
99 + "sgmii_ck",
100 + "eth2pll",
101 + "wocpu0",
102 + "wocpu1",
103 + "netsys0",
104 + "netsys1",
105 + "ethwarp_wocpu2",
106 + "ethwarp_wocpu1",
107 + "ethwarp_wocpu0",
108 + "top_usxgmii0_sel",
109 + "top_usxgmii1_sel",
110 + "top_sgm0_sel",
111 + "top_sgm1_sel",
112 + "top_xfi_phy0_xtal_sel",
113 + "top_xfi_phy1_xtal_sel",
114 + "top_eth_gmii_sel",
115 + "top_eth_refck_50m_sel",
116 + "top_eth_sys_200m_sel",
117 + "top_eth_sys_sel",
118 + "top_eth_xgmii_sel",
119 + "top_eth_mii_sel",
120 + "top_netsys_sel",
121 + "top_netsys_500m_sel",
122 + "top_netsys_pao_2x_sel",
123 + "top_netsys_sync_250m_sel",
124 + "top_netsys_ppefb_250m_sel",
125 + "top_netsys_warp_sel",
126 };
127
128 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
129 @@ -1253,10 +1345,19 @@ static void mtk_tx_set_dma_desc_v2(struc
130 data |= TX_DMA_LS0;
131 WRITE_ONCE(desc->txd3, data);
132
133 - if (mac->id == MTK_GMAC3_ID)
134 - data = PSE_GDM3_PORT;
135 - else
136 - data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
137 + /* set forward port */
138 + switch (mac->id) {
139 + case MTK_GMAC1_ID:
140 + data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2;
141 + break;
142 + case MTK_GMAC2_ID:
143 + data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2;
144 + break;
145 + case MTK_GMAC3_ID:
146 + data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2;
147 + break;
148 + }
149 +
150 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
151 WRITE_ONCE(desc->txd4, data);
152
153 @@ -5010,6 +5111,25 @@ static const struct mtk_soc_data mt7986_
154 },
155 };
156
157 +static const struct mtk_soc_data mt7988_data = {
158 + .reg_map = &mt7988_reg_map,
159 + .ana_rgc3 = 0x128,
160 + .caps = MT7988_CAPS,
161 + .hw_features = MTK_HW_FEATURES,
162 + .required_clks = MT7988_CLKS_BITMAP,
163 + .required_pctl = false,
164 + .num_devs = 3,
165 + .txrx = {
166 + .txd_size = sizeof(struct mtk_tx_dma_v2),
167 + .rxd_size = sizeof(struct mtk_rx_dma_v2),
168 + .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
169 + .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
170 + .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
171 + .dma_len_offset = 8,
172 + },
173 +};
174 +
175 +
176 static const struct mtk_soc_data rt5350_data = {
177 .reg_map = &mt7628_reg_map,
178 .caps = MT7628_CAPS,
179 @@ -5028,14 +5148,15 @@ static const struct mtk_soc_data rt5350_
180 };
181
182 const struct of_device_id of_mtk_match[] = {
183 - { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
184 - { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
185 - { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
186 - { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
187 - { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
188 - { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data},
189 - { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
190 - { .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
191 + { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data },
192 + { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
193 + { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data },
194 + { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data },
195 + { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data },
196 + { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data },
197 + { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data },
198 + { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data },
199 + { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
200 {},
201 };
202 MODULE_DEVICE_TABLE(of, of_mtk_match);
203 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
204 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
205 @@ -116,7 +116,8 @@
206 #define MTK_CDMP_EG_CTRL 0x404
207
208 /* GDM Exgress Control Register */
209 -#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
210 +#define MTK_GDMA_FWD_CFG(x) ((x == MTK_GMAC3_ID) ? \
211 + 0x540 : 0x500 + (x * 0x1000))
212 #define MTK_GDMA_SPECIAL_TAG BIT(24)
213 #define MTK_GDMA_ICS_EN BIT(22)
214 #define MTK_GDMA_TCS_EN BIT(21)
215 @@ -653,6 +654,11 @@ enum mtk_clks_map {
216 MTK_CLK_GP0,
217 MTK_CLK_GP1,
218 MTK_CLK_GP2,
219 + MTK_CLK_GP3,
220 + MTK_CLK_XGP1,
221 + MTK_CLK_XGP2,
222 + MTK_CLK_XGP3,
223 + MTK_CLK_CRYPTO,
224 MTK_CLK_FE,
225 MTK_CLK_TRGPLL,
226 MTK_CLK_SGMII_TX_250M,
227 @@ -669,57 +675,108 @@ enum mtk_clks_map {
228 MTK_CLK_WOCPU1,
229 MTK_CLK_NETSYS0,
230 MTK_CLK_NETSYS1,
231 + MTK_CLK_ETHWARP_WOCPU2,
232 + MTK_CLK_ETHWARP_WOCPU1,
233 + MTK_CLK_ETHWARP_WOCPU0,
234 + MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
235 + MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
236 + MTK_CLK_TOP_SGM_0_SEL,
237 + MTK_CLK_TOP_SGM_1_SEL,
238 + MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
239 + MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
240 + MTK_CLK_TOP_ETH_GMII_SEL,
241 + MTK_CLK_TOP_ETH_REFCK_50M_SEL,
242 + MTK_CLK_TOP_ETH_SYS_200M_SEL,
243 + MTK_CLK_TOP_ETH_SYS_SEL,
244 + MTK_CLK_TOP_ETH_XGMII_SEL,
245 + MTK_CLK_TOP_ETH_MII_SEL,
246 + MTK_CLK_TOP_NETSYS_SEL,
247 + MTK_CLK_TOP_NETSYS_500M_SEL,
248 + MTK_CLK_TOP_NETSYS_PAO_2X_SEL,
249 + MTK_CLK_TOP_NETSYS_SYNC_250M_SEL,
250 + MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL,
251 + MTK_CLK_TOP_NETSYS_WARP_SEL,
252 MTK_CLK_MAX
253 };
254
255 -#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
256 - BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
257 - BIT(MTK_CLK_TRGPLL))
258 -#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
259 - BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
260 - BIT(MTK_CLK_GP2) | \
261 - BIT(MTK_CLK_SGMII_TX_250M) | \
262 - BIT(MTK_CLK_SGMII_RX_250M) | \
263 - BIT(MTK_CLK_SGMII_CDR_REF) | \
264 - BIT(MTK_CLK_SGMII_CDR_FB) | \
265 - BIT(MTK_CLK_SGMII_CK) | \
266 - BIT(MTK_CLK_ETH2PLL))
267 +#define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
268 + BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
269 + BIT_ULL(MTK_CLK_TRGPLL))
270 +#define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
271 + BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
272 + BIT_ULL(MTK_CLK_GP2) | \
273 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
274 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
275 + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
276 + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
277 + BIT_ULL(MTK_CLK_SGMII_CK) | \
278 + BIT_ULL(MTK_CLK_ETH2PLL))
279 #define MT7621_CLKS_BITMAP (0)
280 #define MT7628_CLKS_BITMAP (0)
281 -#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
282 - BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
283 - BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
284 - BIT(MTK_CLK_SGMII_TX_250M) | \
285 - BIT(MTK_CLK_SGMII_RX_250M) | \
286 - BIT(MTK_CLK_SGMII_CDR_REF) | \
287 - BIT(MTK_CLK_SGMII_CDR_FB) | \
288 - BIT(MTK_CLK_SGMII2_TX_250M) | \
289 - BIT(MTK_CLK_SGMII2_RX_250M) | \
290 - BIT(MTK_CLK_SGMII2_CDR_REF) | \
291 - BIT(MTK_CLK_SGMII2_CDR_FB) | \
292 - BIT(MTK_CLK_SGMII_CK) | \
293 - BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
294 -#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
295 - BIT(MTK_CLK_WOCPU0) | \
296 - BIT(MTK_CLK_SGMII_TX_250M) | \
297 - BIT(MTK_CLK_SGMII_RX_250M) | \
298 - BIT(MTK_CLK_SGMII_CDR_REF) | \
299 - BIT(MTK_CLK_SGMII_CDR_FB) | \
300 - BIT(MTK_CLK_SGMII2_TX_250M) | \
301 - BIT(MTK_CLK_SGMII2_RX_250M) | \
302 - BIT(MTK_CLK_SGMII2_CDR_REF) | \
303 - BIT(MTK_CLK_SGMII2_CDR_FB) | \
304 - BIT(MTK_CLK_SGMII_CK))
305 -#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
306 - BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
307 - BIT(MTK_CLK_SGMII_TX_250M) | \
308 - BIT(MTK_CLK_SGMII_RX_250M) | \
309 - BIT(MTK_CLK_SGMII_CDR_REF) | \
310 - BIT(MTK_CLK_SGMII_CDR_FB) | \
311 - BIT(MTK_CLK_SGMII2_TX_250M) | \
312 - BIT(MTK_CLK_SGMII2_RX_250M) | \
313 - BIT(MTK_CLK_SGMII2_CDR_REF) | \
314 - BIT(MTK_CLK_SGMII2_CDR_FB))
315 +#define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \
316 + BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \
317 + BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \
318 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
319 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
320 + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
321 + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
322 + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
323 + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
324 + BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
325 + BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
326 + BIT_ULL(MTK_CLK_SGMII_CK) | \
327 + BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP))
328 +#define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP1) | \
329 + BIT_ULL(MTK_CLK_WOCPU0) | \
330 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
331 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
332 + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
333 + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
334 + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
335 + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
336 + BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
337 + BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \
338 + BIT_ULL(MTK_CLK_SGMII_CK))
339 +#define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP1) | \
340 + BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \
341 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
342 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
343 + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \
344 + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \
345 + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
346 + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
347 + BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \
348 + BIT_ULL(MTK_CLK_SGMII2_CDR_FB))
349 +#define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \
350 + BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \
351 + BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
352 + BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
353 + BIT_ULL(MTK_CLK_CRYPTO) | \
354 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
355 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
356 + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
357 + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
358 + BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
359 + BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
360 + BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
361 + BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
362 + BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
363 + BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
364 + BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
365 + BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
366 + BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
367 + BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
368 + BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
369 + BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
370 + BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \
371 + BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \
372 + BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \
373 + BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \
374 + BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \
375 + BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \
376 + BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \
377 + BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \
378 + BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL))
379
380 enum mtk_dev_state {
381 MTK_HW_INIT,
382 @@ -847,6 +904,7 @@ enum mkt_eth_capabilities {
383 MTK_RGMII_BIT = 0,
384 MTK_TRGMII_BIT,
385 MTK_SGMII_BIT,
386 + MTK_USXGMII_BIT,
387 MTK_ESW_BIT,
388 MTK_GEPHY_BIT,
389 MTK_MUX_BIT,
390 @@ -869,6 +927,8 @@ enum mkt_eth_capabilities {
391 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
392 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
393 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
394 + MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT,
395 + MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT,
396
397 /* PATH BITS */
398 MTK_ETH_PATH_GMAC1_RGMII_BIT,
399 @@ -877,13 +937,18 @@ enum mkt_eth_capabilities {
400 MTK_ETH_PATH_GMAC2_RGMII_BIT,
401 MTK_ETH_PATH_GMAC2_SGMII_BIT,
402 MTK_ETH_PATH_GMAC2_GEPHY_BIT,
403 + MTK_ETH_PATH_GMAC3_SGMII_BIT,
404 MTK_ETH_PATH_GDM1_ESW_BIT,
405 + MTK_ETH_PATH_GMAC1_USXGMII_BIT,
406 + MTK_ETH_PATH_GMAC2_USXGMII_BIT,
407 + MTK_ETH_PATH_GMAC3_USXGMII_BIT,
408 };
409
410 /* Supported hardware group on SoCs */
411 #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT)
412 #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
413 #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
414 +#define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT)
415 #define MTK_ESW BIT_ULL(MTK_ESW_BIT)
416 #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
417 #define MTK_MUX BIT_ULL(MTK_MUX_BIT)
418 @@ -910,6 +975,10 @@ enum mkt_eth_capabilities {
419 BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
420 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
421 BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
422 +#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII \
423 + BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT)
424 +#define MTK_ETH_MUX_GMAC123_TO_USXGMII \
425 + BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT)
426
427 /* Supported path present on SoCs */
428 #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
429 @@ -918,7 +987,11 @@ enum mkt_eth_capabilities {
430 #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
431 #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
432 #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
433 +#define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT)
434 #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
435 +#define MTK_ETH_PATH_GMAC1_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT)
436 +#define MTK_ETH_PATH_GMAC2_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT)
437 +#define MTK_ETH_PATH_GMAC3_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT)
438
439 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
440 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
441 @@ -926,7 +999,11 @@ enum mkt_eth_capabilities {
442 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
443 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
444 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
445 +#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
446 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
447 +#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
448 +#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII)
449 +#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII)
450
451 /* MUXes present on SoCs */
452 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
453 @@ -949,6 +1026,12 @@ enum mkt_eth_capabilities {
454 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
455 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
456
457 +#define MTK_MUX_GMAC123_TO_GEPHY_SGMII \
458 + (MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX)
459 +
460 +#define MTK_MUX_GMAC123_TO_USXGMII \
461 + (MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA)
462 +
463 #ifdef CONFIG_SOC_MT7621
464 #define MTK_CAP_MASK MTK_NETSYS_V2
465 #else
466 @@ -987,9 +1070,17 @@ enum mkt_eth_capabilities {
467 MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
468 MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
469
470 -#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
471 - MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
472 - MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
473 +#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
474 + MTK_MUX_GMAC12_TO_GEPHY_SGMII | \
475 + MTK_QDMA | MTK_NETSYS_V2 | \
476 + MTK_RSTCTRL_PPE1)
477 +
478 +#define MT7988_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
479 + MTK_GMAC3_SGMII | MTK_QDMA | \
480 + MTK_MUX_GMAC123_TO_GEPHY_SGMII | \
481 + MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 | \
482 + MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII | \
483 + MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII)
484
485 struct mtk_tx_dma_desc_info {
486 dma_addr_t addr;
487 @@ -1075,7 +1166,7 @@ struct mtk_soc_data {
488 const struct mtk_reg_map *reg_map;
489 u32 ana_rgc3;
490 u64 caps;
491 - u32 required_clks;
492 + u64 required_clks;
493 bool required_pctl;
494 u8 offload_version;
495 u8 hash_offset;
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