target/linux/generic/pending-6.1/713-02-net-mdio-ipq4019-add-support-for-clock-frequency-pro.patch

   1 From eacf1d2505dfecd3599d558cdade1a2da47fe06d Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Wed, 24 Jan 2024 18:52:33 +0100
   4 Subject: [PATCH 2/3] net: mdio: ipq4019: add support for clock-frequency
   5  property
   6
   7 The IPQ4019 MDIO internally divide the clock feed by AHB based on the
   8 MDIO_MODE reg. On reset or power up, the default value for the
   9 divider is 0xff that reflect the divider set to /256.
  10
  11 This makes the MDC run at a very low rate, that is, considering AHB is
  12 always fixed to 100Mhz, a value of 390KHz.
  13
  14 This hasn't have been a problem as MDIO wasn't used for time sensitive
  15 operation, it is now that on IPQ807x is usually mounted with PHY that
  16 requires MDIO to load their firmware (example Aquantia PHY).
  17
  18 To handle this problem and permit to set the correct designed MDC
  19 frequency for the SoC add support for the standard "clock-frequency"
  20 property for the MDIO node.
  21
  22 The divider supports value from /1 to /256 and the common value are to
  23 set it to /16 to reflect 6.25Mhz or to /8 on newer platform to reflect
  24 12.5Mhz.
  25
  26 To scan if the requested rate is supported by the divider, loop with
  27 each supported divider and stop when the requested rate match the final
  28 rate with the current divider. An error is returned if the rate doesn't
  29 match any value.
  30
  31 On MDIO reset, the divider is restored to the requested value to prevent
  32 any kind of downclocking caused by the divider reverting to a default
  33 value.
  34
  35 To follow 802.3 spec of 2.5MHz of default value, if divider is set at
  36 /256 and "clock-frequency" is not set in DT, assume nobody set the
  37 divider and try to find the closest MDC rate to 2.5MHz. (in the case of
  38 AHB set to 100MHz, it's 1.5625MHz)
  39
  40 While at is also document other bits of the MDIO_MODE reg to have a
  41 clear idea of what is actually applied there.
  42
  43 Documentation of some BITs is skipped as they are marked as reserved and
  44 their usage is not clear (RES 11:9 GENPHY 16:13 RES1 19:17)
  45
  46 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  47 ---
  48  drivers/net/mdio/mdio-ipq4019.c | 109 ++++++++++++++++++++++++++++++--
  49  1 file changed, 103 insertions(+), 6 deletions(-)
  50
  51 --- a/drivers/net/mdio/mdio-ipq4019.c
  52 +++ b/drivers/net/mdio/mdio-ipq4019.c
  53 @@ -14,6 +14,20 @@
  54  #include <linux/clk.h>
  55
  56  #define MDIO_MODE_REG                          0x40
  57 +#define   MDIO_MODE_MDC_MODE                   BIT(12)
  58 +/* 0 = Clause 22, 1 = Clause 45 */
  59 +#define   MDIO_MODE_C45                                BIT(8)
  60 +#define   MDIO_MODE_DIV_MASK                   GENMASK(7, 0)
  61 +#define     MDIO_MODE_DIV(x)                   FIELD_PREP(MDIO_MODE_DIV_MASK, (x) - 1)
  62 +#define     MDIO_MODE_DIV_1                    0x0
  63 +#define     MDIO_MODE_DIV_2                    0x1
  64 +#define     MDIO_MODE_DIV_4                    0x3
  65 +#define     MDIO_MODE_DIV_8                    0x7
  66 +#define     MDIO_MODE_DIV_16                   0xf
  67 +#define     MDIO_MODE_DIV_32                   0x1f
  68 +#define     MDIO_MODE_DIV_64                   0x3f
  69 +#define     MDIO_MODE_DIV_128                  0x7f
  70 +#define     MDIO_MODE_DIV_256                  0xff
  71  #define MDIO_ADDR_REG                          0x44
  72  #define MDIO_DATA_WRITE_REG                    0x48
  73  #define MDIO_DATA_READ_REG                     0x4c
  74 @@ -26,9 +40,6 @@
  75  #define MDIO_CMD_ACCESS_CODE_C45_WRITE 1
  76  #define MDIO_CMD_ACCESS_CODE_C45_READ  2
  77
  78 -/* 0 = Clause 22, 1 = Clause 45 */
  79 -#define MDIO_MODE_C45                          BIT(8)
  80 -
  81  #define IPQ4019_MDIO_TIMEOUT   10000
  82  #define IPQ4019_MDIO_SLEEP             10
  83
  84 @@ -41,6 +52,7 @@ struct ipq4019_mdio_data {
  85         void __iomem    *membase;
  86         void __iomem *eth_ldo_rdy;
  87         struct clk *mdio_clk;
  88 +       unsigned int mdc_rate;
  89  };
  90
  91  static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
  92 @@ -179,6 +191,38 @@ static int ipq4019_mdio_write(struct mii
  93         return 0;
  94  }
  95
  96 +static int ipq4019_mdio_set_div(struct ipq4019_mdio_data *priv)
  97 +{
  98 +       unsigned long ahb_rate;
  99 +       int div;
 100 +       u32 val;
 101 +
 102 +       /* If we don't have a clock for AHB use the fixed value */
 103 +       ahb_rate = IPQ_MDIO_CLK_RATE;
 104 +       if (priv->mdio_clk)
 105 +               ahb_rate = clk_get_rate(priv->mdio_clk);
 106 +
 107 +       /* MDC rate is ahb_rate/(MDIO_MODE_DIV + 1)
 108 +        * While supported, internal documentation doesn't
 109 +        * assure correct functionality of the MDIO bus
 110 +        * with divider of 1, 2 or 4.
 111 +        */
 112 +       for (div = 8; div <= 256; div *= 2) {
 113 +               /* The requested rate is supported by the div */
 114 +               if (priv->mdc_rate == DIV_ROUND_UP(ahb_rate, div)) {
 115 +                       val = readl(priv->membase + MDIO_MODE_REG);
 116 +                       val &= ~MDIO_MODE_DIV_MASK;
 117 +                       val |= MDIO_MODE_DIV(div);
 118 +                       writel(val, priv->membase + MDIO_MODE_REG);
 119 +
 120 +                       return 0;
 121 +               }
 122 +       }
 123 +
 124 +       /* The requested rate is not supported */
 125 +       return -EINVAL;
 126 +}
 127 +
 128  static int ipq_mdio_reset(struct mii_bus *bus)
 129  {
 130         struct ipq4019_mdio_data *priv = bus->priv;
 131 @@ -201,10 +245,58 @@ static int ipq_mdio_reset(struct mii_bus
 132                 return ret;
 133
 134         ret = clk_prepare_enable(priv->mdio_clk);
 135 -       if (ret == 0)
 136 -               mdelay(10);
 137 +       if (ret)
 138 +               return ret;
 139 +
 140 +       mdelay(10);
 141
 142 -       return ret;
 143 +       /* Restore MDC rate */
 144 +       return ipq4019_mdio_set_div(priv);
 145 +}
 146 +
 147 +static void ipq4019_mdio_select_mdc_rate(struct platform_device *pdev,
 148 +                                        struct ipq4019_mdio_data *priv)
 149 +{
 150 +       unsigned long ahb_rate;
 151 +       int div;
 152 +       u32 val;
 153 +
 154 +       /* MDC rate defined in DT, we don't have to decide a default value */
 155 +       if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 156 +                                 &priv->mdc_rate))
 157 +               return;
 158 +
 159 +       /* If we don't have a clock for AHB use the fixed value */
 160 +       ahb_rate = IPQ_MDIO_CLK_RATE;
 161 +       if (priv->mdio_clk)
 162 +               ahb_rate = clk_get_rate(priv->mdio_clk);
 163 +
 164 +       /* Check what is the current div set */
 165 +       val = readl(priv->membase + MDIO_MODE_REG);
 166 +       div = FIELD_GET(MDIO_MODE_DIV_MASK, val);
 167 +
 168 +       /* div is not set to the default value of /256
 169 +        * Probably someone changed that (bootloader, other drivers)
 170 +        * Keep this and doesn't overwrite it.
 171 +        */
 172 +       if (div != MDIO_MODE_DIV_256) {
 173 +               priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div + 1);
 174 +               return;
 175 +       }
 176 +
 177 +       /* If div is /256 assume nobody have set this value and
 178 +        * try to find one MDC rate that is close the 802.3 spec of
 179 +        * 2.5MHz
 180 +        */
 181 +       for (div = 256; div >= 8; div /= 2) {
 182 +               /* Stop as soon as we found a divider that
 183 +                * reached the closest value to 2.5MHz
 184 +                */
 185 +               if (DIV_ROUND_UP(ahb_rate, div) > 2500000)
 186 +                       break;
 187 +
 188 +               priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div);
 189 +       }
 190  }
 191
 192  static int ipq4019_mdio_probe(struct platform_device *pdev)
 193 @@ -228,6 +320,11 @@ static int ipq4019_mdio_probe(struct pla
 194         if (IS_ERR(priv->mdio_clk))
 195                 return PTR_ERR(priv->mdio_clk);
 196
 197 +       ipq4019_mdio_select_mdc_rate(pdev, priv);
 198 +       ret = ipq4019_mdio_set_div(priv);
 199 +       if (ret)
 200 +               return ret;
 201 +
 202         /* The platform resource is provided on the chipset IPQ5018 */
 203         /* This resource is optional */
 204         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);