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generic: add support for MediaTek NETSYS v3
[openwrt/staging/hauke.git] / target / linux / generic / pending-5.15 / 737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
1 From 20ac14fedba025b6b336a821ea60660afe2d46cd Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Wed, 1 Mar 2023 11:56:04 +0000
4 Subject: [PATCH 7/7] net: ethernet: mtk_eth_soc: add paths and SerDes modes
5 for MT7988
6
7 MT7988 comes with a built-in 2.5G PHY as well as USXGMII or 10Base-KR
8 compatible SerDes lanes for external PHYs.
9 Add support for configuring the MAC and SerDes parts for the new paths.
10
11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
12 ---
13 drivers/net/ethernet/mediatek/Makefile | 2 +-
14 drivers/net/ethernet/mediatek/mtk_eth_path.c | 154 ++++-
15 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 291 +++++++-
16 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 162 ++++-
17 drivers/net/ethernet/mediatek/mtk_usxgmii.c | 659 +++++++++++++++++++
18 5 files changed, 1236 insertions(+), 32 deletions(-)
19 create mode 100644 drivers/net/ethernet/mediatek/mtk_usxgmii.c
20
21 --- a/drivers/net/ethernet/mediatek/Makefile
22 +++ b/drivers/net/ethernet/mediatek/Makefile
23 @@ -5,6 +5,7 @@
24
25 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
26 mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
27 +mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_USXGMII) += mtk_usxgmii.o
28 mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o
29 ifdef CONFIG_DEBUG_FS
30 mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
31 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
32 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
33 @@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64
34 return "gmac2_rgmii";
35 case MTK_ETH_PATH_GMAC2_SGMII:
36 return "gmac2_sgmii";
37 + case MTK_ETH_PATH_GMAC2_2P5GPHY:
38 + return "gmac2_2p5gphy";
39 case MTK_ETH_PATH_GMAC2_GEPHY:
40 return "gmac2_gephy";
41 + case MTK_ETH_PATH_GMAC3_SGMII:
42 + return "gmac3_sgmii";
43 case MTK_ETH_PATH_GDM1_ESW:
44 return "gdm1_esw";
45 + case MTK_ETH_PATH_GMAC1_USXGMII:
46 + return "gmac1_usxgmii";
47 + case MTK_ETH_PATH_GMAC2_USXGMII:
48 + return "gmac2_usxgmii";
49 + case MTK_ETH_PATH_GMAC3_USXGMII:
50 + return "gmac3_usxgmii";
51 default:
52 return "unknown path";
53 }
54 @@ -42,8 +52,8 @@ static const char *mtk_eth_path_name(u64
55
56 static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path)
57 {
58 + u32 val, mask, set, reg;
59 bool updated = true;
60 - u32 val, mask, set;
61
62 switch (path) {
63 case MTK_ETH_PATH_GMAC1_SGMII:
64 @@ -59,10 +69,15 @@ static int set_mux_gdm1_to_gmac1_esw(str
65 break;
66 }
67
68 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
69 + reg = MTK_MAC_MISC_V3;
70 + else
71 + reg = MTK_MAC_MISC;
72 +
73 if (updated) {
74 - val = mtk_r32(eth, MTK_MAC_MISC);
75 + val = mtk_r32(eth, reg);
76 val = (val & mask) | set;
77 - mtk_w32(eth, val, MTK_MAC_MISC);
78 + mtk_w32(eth, val, reg);
79 }
80
81 dev_dbg(eth->dev, "path %s in %s updated = %d\n",
82 @@ -125,6 +140,31 @@ static int set_mux_u3_gmac2_to_qphy(stru
83 return 0;
84 }
85
86 +static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path)
87 +{
88 + unsigned int val = 0;
89 + bool updated = true;
90 + int mac_id = 0;
91 +
92 + regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
93 +
94 + switch (path) {
95 + case MTK_ETH_PATH_GMAC2_2P5GPHY:
96 + val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;
97 + mac_id = MTK_GMAC2_ID;
98 + break;
99 + default:
100 + updated = false;
101 + break;
102 + };
103 +
104 + if (updated)
105 + regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
106 + SYSCFG0_SGMII_MASK, val);
107 +
108 + return 0;
109 +}
110 +
111 static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
112 {
113 unsigned int val = 0;
114 @@ -163,7 +203,61 @@ static int set_mux_gmac1_gmac2_to_sgmii_
115 return 0;
116 }
117
118 -static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
119 +static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path)
120 +{
121 + unsigned int val = 0;
122 + bool updated = true;
123 + int mac_id = 0;
124 +
125 + dev_dbg(eth->dev, "path %s in %s updated = %d\n",
126 + mtk_eth_path_name(path), __func__, updated);
127 +
128 + /* Disable SYSCFG1 SGMII */
129 + regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
130 +
131 + switch (path) {
132 + case MTK_ETH_PATH_GMAC1_USXGMII:
133 + val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2;
134 + mac_id = MTK_GMAC1_ID;
135 + break;
136 + case MTK_ETH_PATH_GMAC2_USXGMII:
137 + val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;
138 + mac_id = MTK_GMAC2_ID;
139 + break;
140 + case MTK_ETH_PATH_GMAC3_USXGMII:
141 + val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2;
142 + mac_id = MTK_GMAC3_ID;
143 + break;
144 + default:
145 + updated = false;
146 + };
147 +
148 + if (updated) {
149 + regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
150 + SYSCFG0_SGMII_MASK, val);
151 +
152 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) &&
153 + mac_id == MTK_GMAC2_ID) {
154 + regmap_update_bits(eth->infra,
155 + TOP_MISC_NETSYS_PCS_MUX,
156 + NETSYS_PCS_MUX_MASK,
157 + MUX_G2_USXGMII_SEL);
158 + }
159 + }
160 +
161 + /* Enable XGDM Path */
162 + val = mtk_r32(eth, MTK_GDMA_EG_CTRL(mac_id));
163 + val |= MTK_GDMA_XGDM_SEL;
164 + mtk_w32(eth, val, MTK_GDMA_EG_CTRL(mac_id));
165 +
166 + dev_dbg(eth->dev, "path %s in %s updated = %d\n",
167 + mtk_eth_path_name(path), __func__, updated);
168 +
169 +
170 + return 0;
171 +}
172 +
173 +static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
174 {
175 unsigned int val = 0;
176 bool updated = true;
177 @@ -180,6 +274,9 @@ static int set_mux_gmac12_to_gephy_sgmii
178 case MTK_ETH_PATH_GMAC2_SGMII:
179 val |= SYSCFG0_SGMII_GMAC2_V2;
180 break;
181 + case MTK_ETH_PATH_GMAC3_SGMII:
182 + val |= SYSCFG0_SGMII_GMAC3_V2;
183 + break;
184 default:
185 updated = false;
186 }
187 @@ -208,13 +305,25 @@ static const struct mtk_eth_muxc mtk_eth
188 .cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY,
189 .set_path = set_mux_u3_gmac2_to_qphy,
190 }, {
191 + .name = "mux_gmac2_to_2p5gphy",
192 + .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY,
193 + .set_path = set_mux_gmac2_to_2p5gphy,
194 + }, {
195 .name = "mux_gmac1_gmac2_to_sgmii_rgmii",
196 .cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII,
197 .set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii,
198 }, {
199 .name = "mux_gmac12_to_gephy_sgmii",
200 .cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII,
201 - .set_path = set_mux_gmac12_to_gephy_sgmii,
202 + .set_path = set_mux_gmac123_to_gephy_sgmii,
203 + }, {
204 + .name = "mux_gmac123_to_gephy_sgmii",
205 + .cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII,
206 + .set_path = set_mux_gmac123_to_gephy_sgmii,
207 + }, {
208 + .name = "mux_gmac123_to_usxgmii",
209 + .cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII,
210 + .set_path = set_mux_gmac123_to_usxgmii,
211 },
212 };
213
214 @@ -243,16 +352,46 @@ static int mtk_eth_mux_setup(struct mtk_
215 }
216 }
217
218 + dev_dbg(eth->dev, "leaving mux_setup %s\n",
219 + mtk_eth_path_name(path));
220 +
221 out:
222 return err;
223 }
224
225 +int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id)
226 +{
227 + u64 path;
228 +
229 + path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_USXGMII :
230 + (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_USXGMII :
231 + MTK_ETH_PATH_GMAC3_USXGMII;
232 +
233 + /* Setup proper MUXes along the path */
234 + return mtk_eth_mux_setup(eth, path);
235 +}
236 +
237 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
238 {
239 u64 path;
240
241 - path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII :
242 - MTK_ETH_PATH_GMAC2_SGMII;
243 + path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII :
244 + (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII :
245 + MTK_ETH_PATH_GMAC3_SGMII;
246 +
247 + /* Setup proper MUXes along the path */
248 + return mtk_eth_mux_setup(eth, path);
249 +}
250 +
251 +int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id)
252 +{
253 + u64 path = 0;
254 +
255 + if (mac_id == MTK_GMAC2_ID)
256 + path = MTK_ETH_PATH_GMAC2_2P5GPHY;
257 +
258 + if (!path)
259 + return -EINVAL;
260
261 /* Setup proper MUXes along the path */
262 return mtk_eth_mux_setup(eth, path);
263 @@ -282,4 +421,3 @@ int mtk_gmac_rgmii_path_setup(struct mtk
264 /* Setup proper MUXes along the path */
265 return mtk_eth_mux_setup(eth, path);
266 }
267 -
268 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
269 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
270 @@ -437,6 +437,23 @@ static void mtk_gmac0_rgmii_adjust(struc
271 mtk_w32(eth, val, TRGMII_TCK_CTRL);
272 }
273
274 +static void mtk_setup_bridge_switch(struct mtk_eth *eth)
275 +{
276 + int val;
277 +
278 + /* Force Port1 XGMAC Link Up */
279 + val = mtk_r32(eth, MTK_XGMAC_STS(MTK_GMAC1_ID));
280 + mtk_w32(eth, val | MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID),
281 + MTK_XGMAC_STS(MTK_GMAC1_ID));
282 +
283 + /* Adjust GSW bridge IPG to 11*/
284 + val = mtk_r32(eth, MTK_GSW_CFG);
285 + val &= ~(GSWTX_IPG_MASK | GSWRX_IPG_MASK);
286 + val |= (GSW_IPG_11 << GSWTX_IPG_SHIFT) |
287 + (GSW_IPG_11 << GSWRX_IPG_SHIFT);
288 + mtk_w32(eth, val, MTK_GSW_CFG);
289 +}
290 +
291 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
292 phy_interface_t interface)
293 {
294 @@ -462,7 +479,7 @@ static void mtk_mac_config(struct phylin
295 struct mtk_mac *mac = container_of(config, struct mtk_mac,
296 phylink_config);
297 struct mtk_eth *eth = mac->hw;
298 - int val, ge_mode, err = 0;
299 + int val, ge_mode, force_link, err = 0;
300 u32 i;
301
302 /* MT76x8 has no hardware settings between for the MAC */
303 @@ -506,6 +523,23 @@ static void mtk_mac_config(struct phylin
304 goto init_err;
305 }
306 break;
307 + case PHY_INTERFACE_MODE_USXGMII:
308 + case PHY_INTERFACE_MODE_10GKR:
309 + case PHY_INTERFACE_MODE_5GBASER:
310 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
311 + err = mtk_gmac_usxgmii_path_setup(eth, mac->id);
312 + if (err)
313 + goto init_err;
314 + }
315 + break;
316 + case PHY_INTERFACE_MODE_INTERNAL:
317 + if (mac->id == MTK_GMAC2_ID &&
318 + MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) {
319 + err = mtk_gmac_2p5gphy_path_setup(eth, mac->id);
320 + if (err)
321 + goto init_err;
322 + }
323 + break;
324 default:
325 goto err_phy;
326 }
327 @@ -584,14 +618,92 @@ static void mtk_mac_config(struct phylin
328 SYSCFG0_SGMII_MASK,
329 ~(u32)SYSCFG0_SGMII_MASK);
330
331 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
332 + mtk_xfi_pll_enable(eth);
333 + mtk_sgmii_reset(eth, mac->id);
334 + if (phylink_autoneg_inband(mode))
335 + mtk_sgmii_setup_phya_gen1(eth, mac->id);
336 + else
337 + mtk_sgmii_setup_phya_gen2(eth, mac->id);
338 + }
339 /* Save the syscfg0 value for mac_finish */
340 mac->syscfg0 = val;
341 + } else if (state->interface == PHY_INTERFACE_MODE_USXGMII ||
342 + state->interface == PHY_INTERFACE_MODE_10GKR ||
343 + state->interface == PHY_INTERFACE_MODE_5GBASER) {
344 +
345 + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
346 + err = -EINVAL;
347 + goto init_err;
348 + }
349 + if (phylink_autoneg_inband(mode))
350 + err = mtk_usxgmii_setup_mode_force(eth, mac->id,
351 + state);
352 + else
353 + err = mtk_usxgmii_setup_mode_an(eth, mac->id,
354 + SPEED_10000);
355 +
356 + if (err)
357 + goto init_err;
358 } else if (phylink_autoneg_inband(mode)) {
359 dev_err(eth->dev,
360 "In-band mode not supported in non SGMII mode!\n");
361 return;
362 }
363
364 + /* Setup gmac */
365 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) &&
366 + (mtk_interface_mode_is_xgmii(state->interface) ||
367 + mac->interface == PHY_INTERFACE_MODE_INTERNAL)) {
368 + mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
369 + mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
370 +
371 + switch (mac->id) {
372 + case MTK_GMAC1_ID:
373 + mtk_setup_bridge_switch(eth);
374 + break;
375 + case MTK_GMAC2_ID:
376 + force_link = (mac->interface ==
377 + PHY_INTERFACE_MODE_INTERNAL) ?
378 + MTK_XGMAC_FORCE_LINK(mac->id) : 0;
379 + val = mtk_r32(eth, MTK_XGMAC_STS(mac->id));
380 + mtk_w32(eth, val | force_link,
381 + MTK_XGMAC_STS(mac->id));
382 + break;
383 + case MTK_GMAC3_ID:
384 + val = mtk_r32(eth, MTK_XGMAC_STS(mac->id));
385 + mtk_w32(eth, val | MTK_XGMAC_FORCE_LINK(mac->id),
386 + MTK_XGMAC_STS(mac->id));
387 + break;
388 + }
389 + } else {
390 + val = mtk_r32(eth, MTK_GDMA_EG_CTRL(mac->id));
391 + mtk_w32(eth, val & ~MTK_GDMA_XGDM_SEL,
392 + MTK_GDMA_EG_CTRL(mac->id));
393 +
394 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
395 + switch (mac->id) {
396 + case MTK_GMAC2_ID:
397 + case MTK_GMAC3_ID:
398 + val = mtk_r32(eth, MTK_XGMAC_STS(mac->id));
399 + mtk_w32(eth,
400 + val & ~MTK_XGMAC_FORCE_LINK(mac->id),
401 + MTK_XGMAC_STS(mac->id));
402 + break;
403 + }
404 + }
405 +
406 +/*
407 + if (mac->type != mac_type) {
408 + if (atomic_read(&reset_pending) == 0) {
409 + atomic_inc(&force);
410 + schedule_work(&eth->pending_work);
411 + atomic_inc(&reset_pending);
412 + } else
413 + atomic_dec(&reset_pending);
414 + }
415 +*/
416 + }
417 return;
418
419 err_phy:
420 @@ -632,11 +744,37 @@ static int mtk_mac_finish(struct phylink
421 return 0;
422 }
423
424 -static void mtk_mac_pcs_get_state(struct phylink_config *config,
425 +static void mtk_xgdm_pcs_get_state(struct mtk_mac *mac,
426 + struct phylink_link_state *state)
427 +{
428 + u32 sts = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id));
429 +
430 + if (mac->id == MTK_GMAC2_ID)
431 + sts = sts >> 16;
432 +
433 + state->duplex = 1;
434 +
435 + switch (FIELD_GET(MTK_USXGMII_PCS_MODE, sts)) {
436 + case 0:
437 + state->speed = SPEED_10000;
438 + break;
439 + case 1:
440 + state->speed = SPEED_5000;
441 + break;
442 + case 2:
443 + state->speed = SPEED_2500;
444 + break;
445 + case 3:
446 + state->speed = SPEED_1000;
447 + break;
448 + }
449 +
450 + state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, sts);
451 +}
452 +
453 +static void mtk_gdm_pcs_get_state(struct mtk_mac *mac,
454 struct phylink_link_state *state)
455 {
456 - struct mtk_mac *mac = container_of(config, struct mtk_mac,
457 - phylink_config);
458 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id));
459
460 state->link = (pmsr & MAC_MSR_LINK);
461 @@ -664,15 +802,35 @@ static void mtk_mac_pcs_get_state(struct
462 state->pause |= MLO_PAUSE_TX;
463 }
464
465 +static void mtk_mac_pcs_get_state(struct phylink_config *config,
466 + struct phylink_link_state *state)
467 +{
468 + struct mtk_mac *mac = container_of(config, struct mtk_mac,
469 + phylink_config);
470 +
471 + if (mtk_interface_mode_is_xgmii(state->interface))
472 + mtk_xgdm_pcs_get_state(mac, state);
473 + else
474 + mtk_gdm_pcs_get_state(mac, state);
475 +}
476 +
477 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
478 phy_interface_t interface)
479 {
480 struct mtk_mac *mac = container_of(config, struct mtk_mac,
481 phylink_config);
482 - u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
483 + u32 mcr;
484
485 - mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
486 - mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
487 + if (!mtk_interface_mode_is_xgmii(interface)) {
488 + mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
489 + mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN);
490 + mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
491 + } else if (mac->id != MTK_GMAC1_ID) {
492 + mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
493 + mcr &= 0xfffffff0;
494 + mcr |= XMAC_MCR_TRX_DISABLE;
495 + mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
496 + }
497 }
498
499 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
500 @@ -744,13 +902,11 @@ static void mtk_set_queue_speed(struct m
501 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
502 }
503
504 -static void mtk_mac_link_up(struct phylink_config *config,
505 - struct phy_device *phy,
506 - unsigned int mode, phy_interface_t interface,
507 - int speed, int duplex, bool tx_pause, bool rx_pause)
508 +static void mtk_gdm_mac_link_up(struct mtk_mac *mac,
509 + struct phy_device *phy,
510 + unsigned int mode, phy_interface_t interface,
511 + int speed, int duplex, bool tx_pause, bool rx_pause)
512 {
513 - struct mtk_mac *mac = container_of(config, struct mtk_mac,
514 - phylink_config);
515 u32 mcr;
516
517 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
518 @@ -784,6 +940,47 @@ static void mtk_mac_link_up(struct phyli
519 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
520 }
521
522 +static void mtk_xgdm_mac_link_up(struct mtk_mac *mac,
523 + struct phy_device *phy,
524 + unsigned int mode, phy_interface_t interface,
525 + int speed, int duplex, bool tx_pause, bool rx_pause)
526 +{
527 + u32 mcr;
528 +
529 + if (mac->id == MTK_GMAC1_ID)
530 + return;
531 +
532 + mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
533 +
534 + mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC);
535 + /* Configure pause modes -
536 + * phylink will avoid these for half duplex
537 + */
538 + if (tx_pause)
539 + mcr |= XMAC_MCR_FORCE_TX_FC;
540 + if (rx_pause)
541 + mcr |= XMAC_MCR_FORCE_RX_FC;
542 +
543 + mcr &= ~(XMAC_MCR_TRX_DISABLE);
544 + mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
545 +}
546 +
547 +static void mtk_mac_link_up(struct phylink_config *config,
548 + struct phy_device *phy,
549 + unsigned int mode, phy_interface_t interface,
550 + int speed, int duplex, bool tx_pause, bool rx_pause)
551 +{
552 + struct mtk_mac *mac = container_of(config, struct mtk_mac,
553 + phylink_config);
554 +
555 + if (mtk_interface_mode_is_xgmii(interface))
556 + mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
557 + tx_pause, rx_pause);
558 + else
559 + mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
560 + tx_pause, rx_pause);
561 +}
562 +
563 static const struct phylink_mac_ops mtk_phylink_ops = {
564 .validate = phylink_generic_validate,
565 .mac_select_pcs = mtk_mac_select_pcs,
566 @@ -836,10 +1033,21 @@ static int mtk_mdio_init(struct mtk_eth
567 }
568 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
569
570 + /* Configure MDC Turbo Mode */
571 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
572 + val = mtk_r32(eth, MTK_MAC_MISC_V3);
573 + val |= MISC_MDC_TURBO;
574 + mtk_w32(eth, val, MTK_MAC_MISC_V3);
575 + } else {
576 + val = mtk_r32(eth, MTK_PPSC);
577 + val |= PPSC_MDC_TURBO;
578 + mtk_w32(eth, val, MTK_PPSC);
579 + }
580 +
581 /* Configure MDC Divider */
582 val = mtk_r32(eth, MTK_PPSC);
583 val &= ~PPSC_MDC_CFG;
584 - val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO;
585 + val |= FIELD_PREP(PPSC_MDC_CFG, divider);
586 mtk_w32(eth, val, MTK_PPSC);
587
588 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
589 @@ -4433,8 +4641,8 @@ static int mtk_add_mac(struct mtk_eth *e
590 const __be32 *_id = of_get_property(np, "reg", NULL);
591 phy_interface_t phy_mode;
592 struct phylink *phylink;
593 - struct mtk_mac *mac;
594 int id, err;
595 + struct mtk_mac *mac;
596 int txqs = 1;
597
598 if (!_id) {
599 @@ -4525,6 +4733,32 @@ static int mtk_add_mac(struct mtk_eth *e
600 mac->phylink_config.supported_interfaces);
601 }
602
603 + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) {
604 + if (id == MTK_GMAC1_ID) {
605 + mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
606 + MAC_SYM_PAUSE |
607 + MAC_10000FD;
608 + phy_interface_zero(
609 + mac->phylink_config.supported_interfaces);
610 + __set_bit(PHY_INTERFACE_MODE_INTERNAL,
611 + mac->phylink_config.supported_interfaces);
612 + } else {
613 + mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD;
614 + __set_bit(PHY_INTERFACE_MODE_5GBASER,
615 + mac->phylink_config.supported_interfaces);
616 + __set_bit(PHY_INTERFACE_MODE_10GKR,
617 + mac->phylink_config.supported_interfaces);
618 + __set_bit(PHY_INTERFACE_MODE_USXGMII,
619 + mac->phylink_config.supported_interfaces);
620 + }
621 + }
622 +
623 + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY)) {
624 + if (id == MTK_GMAC2_ID)
625 + __set_bit(PHY_INTERFACE_MODE_INTERNAL,
626 + mac->phylink_config.supported_interfaces);
627 + }
628 +
629 phylink = phylink_create(&mac->phylink_config,
630 of_fwnode_handle(mac->of_node),
631 phy_mode, &mtk_phylink_ops);
632 @@ -4714,6 +4948,33 @@ static int mtk_probe(struct platform_dev
633 return err;
634 }
635
636 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
637 + eth->xgmii = devm_kzalloc(eth->dev, sizeof(*eth->xgmii), GFP_KERNEL);
638 + err = mtk_usxgmii_init(eth);
639 + if (err) {
640 + dev_err(&pdev->dev, "usxgmii init failed\n");
641 + return err;
642 + }
643 +
644 + err = mtk_xfi_pextp_init(eth);
645 + if (err) {
646 + dev_err(&pdev->dev, "pextp init failed\n");
647 + return err;
648 + }
649 +
650 + err = mtk_xfi_pll_init(eth);
651 + if (err) {
652 + dev_err(&pdev->dev, "xfi pll init failed\n");
653 + return err;
654 + }
655 +
656 + err = mtk_toprgu_init(eth);
657 + if (err) {
658 + dev_err(&pdev->dev, "toprgu init failed\n");
659 + return err;
660 + }
661 + }
662 +
663 if (eth->soc->required_pctl) {
664 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
665 "mediatek,pctl");
666 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
667 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
668 @@ -126,6 +126,11 @@
669 #define MTK_GDMA_TO_PDMA 0x0
670 #define MTK_GDMA_DROP_ALL 0x7777
671
672 +/* GDM Egress Control Register */
673 +#define MTK_GDMA_EG_CTRL(x) ((x == MTK_GMAC3_ID) ? \
674 + 0x544 : 0x504 + (x * 0x1000))
675 +#define MTK_GDMA_XGDM_SEL BIT(31)
676 +
677 /* Unicast Filter MAC Address Register - Low */
678 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
679
680 @@ -386,7 +391,26 @@
681 #define PHY_IAC_TIMEOUT HZ
682
683 #define MTK_MAC_MISC 0x1000c
684 +#define MTK_MAC_MISC_V3 0x10010
685 #define MTK_MUX_TO_ESW BIT(0)
686 +#define MISC_MDC_TURBO BIT(4)
687 +
688 +/* XMAC status registers */
689 +#define MTK_XGMAC_STS(x) ((x == MTK_GMAC3_ID) ? 0x1001C : 0x1000C)
690 +#define MTK_XGMAC_FORCE_LINK(x) ((x == MTK_GMAC2_ID) ? BIT(31) : BIT(15))
691 +#define MTK_USXGMII_PCS_LINK BIT(8)
692 +#define MTK_XGMAC_RX_FC BIT(5)
693 +#define MTK_XGMAC_TX_FC BIT(4)
694 +#define MTK_USXGMII_PCS_MODE GENMASK(3, 1)
695 +#define MTK_XGMAC_LINK_STS BIT(0)
696 +
697 +/* GSW bridge registers */
698 +#define MTK_GSW_CFG (0x10080)
699 +#define GSWTX_IPG_MASK GENMASK(19, 16)
700 +#define GSWTX_IPG_SHIFT 16
701 +#define GSWRX_IPG_MASK GENMASK(3, 0)
702 +#define GSWRX_IPG_SHIFT 0
703 +#define GSW_IPG_11 11
704
705 /* Mac control registers */
706 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
707 @@ -411,6 +435,17 @@
708 #define MAC_MCR_FORCE_LINK BIT(0)
709 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE)
710
711 +/* Mac EEE control registers */
712 +#define MTK_MAC_EEE(x) (0x10104 + (x * 0x100))
713 +#define MAC_EEE_WAKEUP_TIME_1000 GENMASK(31, 24)
714 +#define MAC_EEE_WAKEUP_TIME_100 GENMASK(23, 16)
715 +#define MAC_EEE_LPI_TXIDLE_THD GENMASK(15, 8)
716 +#define MAC_EEE_RESV0 GENMASK(7, 4)
717 +#define MAC_EEE_CKG_TXILDE BIT(3)
718 +#define MAC_EEE_CKG_RXLPI BIT(2)
719 +#define MAC_EEE_TX_DOWN_REQ BIT(1)
720 +#define MAC_EEE_LPI_MODE BIT(0)
721 +
722 /* Mac status registers */
723 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
724 #define MAC_MSR_EEE1G BIT(7)
725 @@ -455,6 +490,12 @@
726 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
727 #define INTF_MODE_RGMII_10_100 0
728
729 +/* XFI Mac control registers */
730 +#define MTK_XMAC_MCR(x) (0x12000 + ((x - 1) * 0x1000))
731 +#define XMAC_MCR_TRX_DISABLE 0xf
732 +#define XMAC_MCR_FORCE_TX_FC BIT(5)
733 +#define XMAC_MCR_FORCE_RX_FC BIT(4)
734 +
735 /* GPIO port control registers for GMAC 2*/
736 #define GPIO_OD33_CTRL8 0x4c0
737 #define GPIO_BIAS_CTRL 0xed0
738 @@ -480,6 +521,7 @@
739 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
740 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
741 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
742 +#define SYSCFG0_SGMII_GMAC3_V2 BIT(7)
743
744
745 /* ethernet subsystem clock register */
746 @@ -506,16 +548,69 @@
747 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
748 #define ETHSYS_DMA_AG_MAP_PPE BIT(2)
749
750 +/* USXGMII subsystem config registers */
751 +/* Register to control speed */
752 +#define RG_PHY_TOP_SPEED_CTRL1 0x80C
753 +#define RG_USXGMII_RATE_UPDATE_MODE BIT(31)
754 +#define RG_MAC_CK_GATED BIT(29)
755 +#define RG_IF_FORCE_EN BIT(28)
756 +#define RG_RATE_ADAPT_MODE GENMASK(10, 8)
757 +#define RG_RATE_ADAPT_MODE_X1 0
758 +#define RG_RATE_ADAPT_MODE_X2 1
759 +#define RG_RATE_ADAPT_MODE_X4 2
760 +#define RG_RATE_ADAPT_MODE_X10 3
761 +#define RG_RATE_ADAPT_MODE_X100 4
762 +#define RG_RATE_ADAPT_MODE_X5 5
763 +#define RG_RATE_ADAPT_MODE_X50 6
764 +#define RG_XFI_RX_MODE GENMASK(6, 4)
765 +#define RG_XFI_RX_MODE_10G 0
766 +#define RG_XFI_RX_MODE_5G 1
767 +#define RG_XFI_TX_MODE GENMASK(2, 0)
768 +#define RG_XFI_TX_MODE_10G 0
769 +#define RG_XFI_TX_MODE_5G 1
770 +
771 +/* Register to control PCS AN */
772 +#define RG_PCS_AN_CTRL0 0x810
773 +#define RG_AN_ENABLE BIT(0)
774 +
775 +/* Register to control USXGMII XFI PLL digital */
776 +#define XFI_PLL_DIG_GLB8 0x08
777 +#define RG_XFI_PLL_EN BIT(31)
778 +
779 +/* Register to control USXGMII XFI PLL analog */
780 +#define XFI_PLL_ANA_GLB8 0x108
781 +#define RG_XFI_PLL_ANA_SWWA 0x02283248
782 +
783 /* Infrasys subsystem config registers */
784 #define INFRA_MISC2 0x70c
785 #define CO_QPHY_SEL BIT(0)
786 #define GEPHY_MAC_SEL BIT(1)
787
788 +/* Toprgu subsystem config registers */
789 +#define TOPRGU_SWSYSRST 0x18
790 +#define SWSYSRST_UNLOCK_KEY GENMASK(31, 24)
791 +#define SWSYSRST_XFI_PLL_GRST BIT(16)
792 +#define SWSYSRST_XFI_PEXPT1_GRST BIT(15)
793 +#define SWSYSRST_XFI_PEXPT0_GRST BIT(14)
794 +#define SWSYSRST_SGMII1_GRST BIT(2)
795 +#define SWSYSRST_SGMII0_GRST BIT(1)
796 +#define TOPRGU_SWSYSRST_EN 0xFC
797 +
798 /* Top misc registers */
799 +#define TOP_MISC_NETSYS_PCS_MUX 0x84
800 +#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
801 +#define MUX_G2_USXGMII_SEL BIT(1)
802 +#define MUX_HSGMII1_G1_SEL BIT(0)
803 +
804 #define USB_PHY_SWITCH_REG 0x218
805 #define QPHY_SEL_MASK GENMASK(1, 0)
806 #define SGMII_QPHY_SEL 0x2
807
808 +/* MDIO control */
809 +#define MII_MMD_ACC_CTL_REG 0x0d
810 +#define MII_MMD_ADDR_DATA_REG 0x0e
811 +#define MMD_OP_MODE_DATA BIT(14)
812 +
813 /* MT7628/88 specific stuff */
814 #define MT7628_PDMA_OFFSET 0x0800
815 #define MT7628_SDM_OFFSET 0x0c00
816 @@ -809,13 +904,6 @@ enum mtk_gmac_id {
817 MTK_GMAC_ID_MAX
818 };
819
820 -/* GDM Type */
821 -enum mtk_gdm_type {
822 - MTK_GDM_TYPE = 0,
823 - MTK_XGDM_TYPE,
824 - MTK_GDM_TYPE_MAX
825 -};
826 -
827 enum mtk_tx_buf_type {
828 MTK_TYPE_SKB,
829 MTK_TYPE_XDP_TX,
830 @@ -902,6 +990,7 @@ enum mkt_eth_capabilities {
831 MTK_TRGMII_BIT,
832 MTK_SGMII_BIT,
833 MTK_USXGMII_BIT,
834 + MTK_2P5GPHY_BIT,
835 MTK_ESW_BIT,
836 MTK_GEPHY_BIT,
837 MTK_MUX_BIT,
838 @@ -922,6 +1011,7 @@ enum mkt_eth_capabilities {
839 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
840 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
841 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
842 + MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT,
843 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
844 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
845 MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT,
846 @@ -933,6 +1023,7 @@ enum mkt_eth_capabilities {
847 MTK_ETH_PATH_GMAC1_SGMII_BIT,
848 MTK_ETH_PATH_GMAC2_RGMII_BIT,
849 MTK_ETH_PATH_GMAC2_SGMII_BIT,
850 + MTK_ETH_PATH_GMAC2_2P5GPHY_BIT,
851 MTK_ETH_PATH_GMAC2_GEPHY_BIT,
852 MTK_ETH_PATH_GMAC3_SGMII_BIT,
853 MTK_ETH_PATH_GDM1_ESW_BIT,
854 @@ -946,6 +1037,7 @@ enum mkt_eth_capabilities {
855 #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
856 #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
857 #define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT)
858 +#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT)
859 #define MTK_ESW BIT_ULL(MTK_ESW_BIT)
860 #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
861 #define MTK_MUX BIT_ULL(MTK_MUX_BIT)
862 @@ -968,6 +1060,8 @@ enum mkt_eth_capabilities {
863 BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
864 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
865 BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
866 +#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \
867 + BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT)
868 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
869 BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
870 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
871 @@ -983,6 +1077,7 @@ enum mkt_eth_capabilities {
872 #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
873 #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
874 #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
875 +#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT)
876 #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
877 #define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT)
878 #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
879 @@ -996,6 +1091,7 @@ enum mkt_eth_capabilities {
880 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
881 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
882 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
883 +#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY)
884 #define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
885 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
886 #define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
887 @@ -1019,6 +1115,10 @@ enum mkt_eth_capabilities {
888 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
889 MTK_SHARED_SGMII)
890
891 +/* 2: GMAC2 -> XGMII */
892 +#define MTK_MUX_GMAC2_TO_2P5GPHY \
893 + (MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA)
894 +
895 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
896 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
897 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
898 @@ -1077,7 +1177,8 @@ enum mkt_eth_capabilities {
899 MTK_MUX_GMAC123_TO_GEPHY_SGMII | \
900 MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 | \
901 MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII | \
902 - MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII)
903 + MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII | \
904 + MTK_GMAC2_2P5GPHY | MTK_MUX_GMAC2_TO_2P5GPHY)
905
906 struct mtk_tx_dma_desc_info {
907 dma_addr_t addr;
908 @@ -1183,6 +1284,19 @@ struct mtk_soc_data {
909
910 #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000)
911
912 +/* struct mtk_xgmii - This is the structure holding sgmii/usxgmii regmap and
913 + * its characteristics
914 + * @regmap: The register map pointing at the range used to setup
915 + * SGMII/USXGMII modes
916 + * @flags: The enum refers to which mode the sgmii wants to run on
917 + * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
918 + */
919 +struct mtk_xgmii {
920 + struct regmap **regmap_usxgmii;
921 + struct regmap **regmap_pextp;
922 + struct regmap *regmap_pll;
923 +};
924 +
925 /* struct mtk_eth - This is the main datasructure for holding the state
926 * of the driver
927 * @dev: The device pointer
928 @@ -1244,7 +1358,9 @@ struct mtk_eth {
929 unsigned long sysclk;
930 struct regmap *ethsys;
931 struct regmap *infra;
932 + struct regmap *toprgu;
933 struct phylink_pcs **sgmii_pcs;
934 + struct mtk_xgmii *xgmii;
935 struct regmap *pctl;
936 bool hwlro;
937 refcount_t dma_refcnt;
938 @@ -1400,6 +1516,19 @@ static inline u32 mtk_get_ib2_multicast_
939 return MTK_FOE_IB2_MULTICAST;
940 }
941
942 +static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface)
943 +{
944 + switch (interface) {
945 + case PHY_INTERFACE_MODE_USXGMII:
946 + case PHY_INTERFACE_MODE_10GKR:
947 + case PHY_INTERFACE_MODE_5GBASER:
948 + return true;
949 + break;
950 + default:
951 + return false;
952 + }
953 +}
954 +
955 /* read the hardware status register */
956 void mtk_stats_update_mac(struct mtk_mac *mac);
957
958 @@ -1407,8 +1536,10 @@ void mtk_w32(struct mtk_eth *eth, u32 va
959 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
960
961 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
962 +int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id);
963 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
964 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
965 +int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id);
966
967 int mtk_eth_offload_init(struct mtk_eth *eth);
968 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
969 @@ -1418,5 +1549,36 @@ int mtk_flow_offload_cmd(struct mtk_eth
970 void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list);
971 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);
972
973 +#ifdef CONFIG_NET_MEDIATEK_SOC_USXGMII
974 +int mtk_usxgmii_init(struct mtk_eth *eth);
975 +int mtk_xfi_pextp_init(struct mtk_eth *eth);
976 +int mtk_xfi_pll_init(struct mtk_eth *eth);
977 +int mtk_toprgu_init(struct mtk_eth *eth);
978 +int mtk_xfi_pll_enable(struct mtk_eth *eth);
979 +int mtk_usxgmii_setup_mode_an(struct mtk_eth *eth, int mac_id,
980 + int max_speed);
981 +int mtk_usxgmii_setup_mode_force(struct mtk_eth *eth, int mac_id,
982 + const struct phylink_link_state *state);
983 +void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth *eth, int mac_id);
984 +void mtk_usxgmii_reset(struct mtk_eth *eth, int mac_id);
985 +void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id);
986 +void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id);
987 +void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id);
988 +#else
989 +static inline int mtk_usxgmii_init(struct mtk_eth *eth) { return 0; };
990 +static inline int mtk_xfi_pextp_init(struct mtk_eth *eth) { return 0; };
991 +static inline int mtk_xfi_pll_init(struct mtk_eth *eth) { return 0; };
992 +static inline int mtk_toprgu_init(struct mtk_eth *eth) { return 0; };
993 +static inline int mtk_xfi_pll_enable(struct mtk_eth *eth) { return 0; };
994 +static inline int mtk_usxgmii_setup_mode_an(struct mtk_eth *eth, int mac_id,
995 + int max_speed) { return 0; };
996 +static inline int mtk_usxgmii_setup_mode_force(struct mtk_eth *eth, int mac_id,
997 + const struct phylink_link_state *state) { return 0; };
998 +static inline void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth *eth, int mac_id) { };
999 +static inline void mtk_usxgmii_reset(struct mtk_eth *eth, int mac_id) { };
1000 +static inline void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id) { };
1001 +static inline void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id) { };
1002 +static inline void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id) { };
1003 +#endif
1004
1005 #endif /* MTK_ETH_H */
1006 --- /dev/null
1007 +++ b/drivers/net/ethernet/mediatek/mtk_usxgmii.c
1008 @@ -0,0 +1,646 @@
1009 +/* SPDX-License-Identifier: GPL-2.0
1010 + *
1011 + * Copyright (c) 2022 MediaTek Inc.
1012 + * Author: Henry Yen <henry.yen@mediatek.com>
1013 + */
1014 +
1015 +#include <linux/mfd/syscon.h>
1016 +#include <linux/of.h>
1017 +#include <linux/regmap.h>
1018 +#include "mtk_eth_soc.h"
1019 +
1020 +int mtk_usxgmii_init(struct mtk_eth *eth)
1021 +{
1022 + struct device_node *r = eth->dev->of_node;
1023 + struct mtk_xgmii *xs = eth->xgmii;
1024 + struct device *dev = eth->dev;
1025 + struct device_node *np;
1026 + int i;
1027 +
1028 + xs->regmap_usxgmii = devm_kzalloc(dev, sizeof(*xs->regmap_usxgmii) *
1029 + eth->soc->num_devs, GFP_KERNEL);
1030 + if (!xs->regmap_usxgmii)
1031 + return -ENOMEM;
1032 +
1033 + for (i = 0; i < eth->soc->num_devs; i++) {
1034 + np = of_parse_phandle(r, "mediatek,usxgmiisys", i);
1035 + if (!np)
1036 + break;
1037 +
1038 + xs->regmap_usxgmii[i] = syscon_node_to_regmap(np);
1039 + if (IS_ERR(xs->regmap_usxgmii[i]))
1040 + return PTR_ERR(xs->regmap_usxgmii[i]);
1041 + }
1042 +
1043 + return 0;
1044 +}
1045 +
1046 +int mtk_xfi_pextp_init(struct mtk_eth *eth)
1047 +{
1048 + struct device *dev = eth->dev;
1049 + struct device_node *r = dev->of_node;
1050 + struct mtk_xgmii *xs = eth->xgmii;
1051 + struct device_node *np;
1052 + int i;
1053 +
1054 + xs->regmap_pextp = devm_kzalloc(dev, sizeof(*xs->regmap_pextp) *
1055 + eth->soc->num_devs, GFP_KERNEL);
1056 + if (!xs->regmap_pextp)
1057 + return -ENOMEM;
1058 +
1059 + for (i = 0; i < eth->soc->num_devs; i++) {
1060 + np = of_parse_phandle(r, "mediatek,xfi_pextp", i);
1061 + if (!np)
1062 + break;
1063 +
1064 + xs->regmap_pextp[i] = syscon_node_to_regmap(np);
1065 + if (IS_ERR(xs->regmap_pextp[i]))
1066 + return PTR_ERR(xs->regmap_pextp[i]);
1067 + }
1068 +
1069 + return 0;
1070 +}
1071 +
1072 +int mtk_xfi_pll_init(struct mtk_eth *eth)
1073 +{
1074 + struct device_node *r = eth->dev->of_node;
1075 + struct mtk_xgmii *xs = eth->xgmii;
1076 + struct device_node *np;
1077 +
1078 + np = of_parse_phandle(r, "mediatek,xfi_pll", 0);
1079 + if (!np)
1080 + return -1;
1081 +
1082 + xs->regmap_pll = syscon_node_to_regmap(np);
1083 + if (IS_ERR(xs->regmap_pll))
1084 + return PTR_ERR(xs->regmap_pll);
1085 +
1086 + return 0;
1087 +}
1088 +
1089 +int mtk_toprgu_init(struct mtk_eth *eth)
1090 +{
1091 + struct device_node *r = eth->dev->of_node;
1092 + struct device_node *np;
1093 +
1094 + np = of_parse_phandle(r, "mediatek,toprgu", 0);
1095 + if (!np)
1096 + return -1;
1097 +
1098 + eth->toprgu = syscon_node_to_regmap(np);
1099 + if (IS_ERR(eth->toprgu))
1100 + return PTR_ERR(eth->toprgu);
1101 +
1102 + return 0;
1103 +}
1104 +
1105 +int mtk_xfi_pll_enable(struct mtk_eth *eth)
1106 +{
1107 + struct mtk_xgmii *xs = eth->xgmii;
1108 + u32 val = 0;
1109 +
1110 + if (!xs->regmap_pll)
1111 + return -EINVAL;
1112 +
1113 + /* Add software workaround for USXGMII PLL TCL issue */
1114 + regmap_write(xs->regmap_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA);
1115 +
1116 + regmap_read(xs->regmap_pll, XFI_PLL_DIG_GLB8, &val);
1117 + val |= RG_XFI_PLL_EN;
1118 + regmap_write(xs->regmap_pll, XFI_PLL_DIG_GLB8, val);
1119 +
1120 + return 0;
1121 +}
1122 +
1123 +static int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id)
1124 +{
1125 + int xgmii_id = mac_id;
1126 +
1127 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
1128 + switch (mac_id) {
1129 + case MTK_GMAC1_ID:
1130 + case MTK_GMAC2_ID:
1131 + xgmii_id = 1;
1132 + break;
1133 + case MTK_GMAC3_ID:
1134 + xgmii_id = 0;
1135 + break;
1136 + default:
1137 + xgmii_id = -1;
1138 + }
1139 + }
1140 +
1141 + return xgmii_id;
1142 +}
1143 +
1144 +void mtk_usxgmii_setup_phya_an_10000(struct mtk_eth *eth, int mac_id)
1145 +{
1146 + struct mtk_xgmii *xs = eth->xgmii;
1147 + u32 id = mtk_mac2xgmii_id(eth, mac_id);
1148 +
1149 + if (id >= eth->soc->num_devs ||
1150 + !xs->regmap_usxgmii[id] || !xs->regmap_pextp[id])
1151 + return;
1152 +
1153 + regmap_write(xs->regmap_usxgmii[id], RG_PCS_AN_CTRL0, 0x000FFE6D);
1154 + regmap_write(xs->regmap_usxgmii[id], 0x818, 0x07B1EC7B);
1155 + regmap_write(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, 0x30000000);
1156 + ndelay(1020);
1157 + regmap_write(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, 0x10000000);
1158 + ndelay(1020);
1159 + regmap_write(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, 0x00000000);
1160 +
1161 + regmap_write(xs->regmap_pextp[id], 0x9024, 0x00C9071C);
1162 + regmap_write(xs->regmap_pextp[id], 0x2020, 0xAA8585AA);
1163 + regmap_write(xs->regmap_pextp[id], 0x2030, 0x0C020707);
1164 + regmap_write(xs->regmap_pextp[id], 0x2034, 0x0E050F0F);
1165 + regmap_write(xs->regmap_pextp[id], 0x2040, 0x00140032);
1166 + regmap_write(xs->regmap_pextp[id], 0x50F0, 0x00C014AA);
1167 + regmap_write(xs->regmap_pextp[id], 0x50E0, 0x3777C12B);
1168 + regmap_write(xs->regmap_pextp[id], 0x506C, 0x005F9CFF);
1169 + regmap_write(xs->regmap_pextp[id], 0x5070, 0x9D9DFAFA);
1170 + regmap_write(xs->regmap_pextp[id], 0x5074, 0x27273F3F);
1171 + regmap_write(xs->regmap_pextp[id], 0x5078, 0xA7883C68);
1172 + regmap_write(xs->regmap_pextp[id], 0x507C, 0x11661166);
1173 + regmap_write(xs->regmap_pextp[id], 0x5080, 0x0E000AAF);
1174 + regmap_write(xs->regmap_pextp[id], 0x5084, 0x08080D0D);
1175 + regmap_write(xs->regmap_pextp[id], 0x5088, 0x02030909);
1176 + regmap_write(xs->regmap_pextp[id], 0x50E4, 0x0C0C0000);
1177 + regmap_write(xs->regmap_pextp[id], 0x50E8, 0x04040000);
1178 + regmap_write(xs->regmap_pextp[id], 0x50EC, 0x0F0F0C06);
1179 + regmap_write(xs->regmap_pextp[id], 0x50A8, 0x506E8C8C);
1180 + regmap_write(xs->regmap_pextp[id], 0x6004, 0x18190000);
1181 + regmap_write(xs->regmap_pextp[id], 0x00F8, 0x01423342);
1182 + regmap_write(xs->regmap_pextp[id], 0x00F4, 0x80201F20);
1183 + regmap_write(xs->regmap_pextp[id], 0x0030, 0x00050C00);
1184 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x02002800);
1185 + ndelay(1020);
1186 + regmap_write(xs->regmap_pextp[id], 0x30B0, 0x00000020);
1187 + regmap_write(xs->regmap_pextp[id], 0x3028, 0x00008A01);
1188 + regmap_write(xs->regmap_pextp[id], 0x302C, 0x0000A884);
1189 + regmap_write(xs->regmap_pextp[id], 0x3024, 0x00083002);
1190 + regmap_write(xs->regmap_pextp[id], 0x3010, 0x00022220);
1191 + regmap_write(xs->regmap_pextp[id], 0x5064, 0x0F020A01);
1192 + regmap_write(xs->regmap_pextp[id], 0x50B4, 0x06100600);
1193 + regmap_write(xs->regmap_pextp[id], 0x3048, 0x40704000);
1194 + regmap_write(xs->regmap_pextp[id], 0x3050, 0xA8000000);
1195 + regmap_write(xs->regmap_pextp[id], 0x3054, 0x000000AA);
1196 + regmap_write(xs->regmap_pextp[id], 0x306C, 0x00000F00);
1197 + regmap_write(xs->regmap_pextp[id], 0xA060, 0x00040000);
1198 + regmap_write(xs->regmap_pextp[id], 0x90D0, 0x00000001);
1199 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200E800);
1200 + udelay(150);
1201 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200C111);
1202 + ndelay(1020);
1203 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200C101);
1204 + udelay(15);
1205 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0202C111);
1206 + ndelay(1020);
1207 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0202C101);
1208 + udelay(100);
1209 + regmap_write(xs->regmap_pextp[id], 0x30B0, 0x00000030);
1210 + regmap_write(xs->regmap_pextp[id], 0x00F4, 0x80201F00);
1211 + regmap_write(xs->regmap_pextp[id], 0x3040, 0x30000000);
1212 + udelay(400);
1213 +}
1214 +
1215 +void mtk_usxgmii_setup_phya_force_5000(struct mtk_eth *eth, int mac_id)
1216 +{
1217 + unsigned int val;
1218 + struct mtk_xgmii *xs = eth->xgmii;
1219 + u32 id = mtk_mac2xgmii_id(eth, mac_id);
1220 +
1221 + if (id >= eth->soc->num_devs ||
1222 + !xs->regmap_usxgmii[id] || !xs->regmap_pextp[id])
1223 + return;
1224 +
1225 + /* Setup USXGMII speed */
1226 + val = FIELD_PREP(RG_XFI_RX_MODE, RG_XFI_RX_MODE_5G) |
1227 + FIELD_PREP(RG_XFI_TX_MODE, RG_XFI_TX_MODE_5G);
1228 + regmap_write(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
1229 +
1230 + /* Disable USXGMII AN mode */
1231 + regmap_read(xs->regmap_usxgmii[id], RG_PCS_AN_CTRL0, &val);
1232 + val &= ~RG_AN_ENABLE;
1233 + regmap_write(xs->regmap_usxgmii[id], RG_PCS_AN_CTRL0, val);
1234 +
1235 + /* Gated USXGMII */
1236 + regmap_read(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
1237 + val |= RG_MAC_CK_GATED;
1238 + regmap_write(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
1239 +
1240 + ndelay(1020);
1241 +
1242 + /* USXGMII force mode setting */
1243 + regmap_read(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
1244 + val |= RG_USXGMII_RATE_UPDATE_MODE;
1245 + val |= RG_IF_FORCE_EN;
1246 + val |= FIELD_PREP(RG_RATE_ADAPT_MODE, RG_RATE_ADAPT_MODE_X1);
1247 + regmap_write(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
1248 +
1249 + /* Un-gated USXGMII */
1250 + regmap_read(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
1251 + val &= ~RG_MAC_CK_GATED;
1252 + regmap_write(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
1253 +
1254 + ndelay(1020);
1255 +
1256 + regmap_write(xs->regmap_pextp[id], 0x9024, 0x00D9071C);
1257 + regmap_write(xs->regmap_pextp[id], 0x2020, 0xAAA5A5AA);
1258 + regmap_write(xs->regmap_pextp[id], 0x2030, 0x0C020707);
1259 + regmap_write(xs->regmap_pextp[id], 0x2034, 0x0E050F0F);
1260 + regmap_write(xs->regmap_pextp[id], 0x2040, 0x00140032);
1261 + regmap_write(xs->regmap_pextp[id], 0x50F0, 0x00C018AA);
1262 + regmap_write(xs->regmap_pextp[id], 0x50E0, 0x3777812B);
1263 + regmap_write(xs->regmap_pextp[id], 0x506C, 0x005C9CFF);
1264 + regmap_write(xs->regmap_pextp[id], 0x5070, 0x9DFAFAFA);
1265 + regmap_write(xs->regmap_pextp[id], 0x5074, 0x273F3F3F);
1266 + regmap_write(xs->regmap_pextp[id], 0x5078, 0xA8883868);
1267 + regmap_write(xs->regmap_pextp[id], 0x507C, 0x14661466);
1268 + regmap_write(xs->regmap_pextp[id], 0x5080, 0x0E001ABF);
1269 + regmap_write(xs->regmap_pextp[id], 0x5084, 0x080B0D0D);
1270 + regmap_write(xs->regmap_pextp[id], 0x5088, 0x02050909);
1271 + regmap_write(xs->regmap_pextp[id], 0x50E4, 0x0C000000);
1272 + regmap_write(xs->regmap_pextp[id], 0x50E8, 0x04000000);
1273 + regmap_write(xs->regmap_pextp[id], 0x50EC, 0x0F0F0C06);
1274 + regmap_write(xs->regmap_pextp[id], 0x50A8, 0x50808C8C);
1275 + regmap_write(xs->regmap_pextp[id], 0x6004, 0x18000000);
1276 + regmap_write(xs->regmap_pextp[id], 0x00F8, 0x00A132A1);
1277 + regmap_write(xs->regmap_pextp[id], 0x00F4, 0x80201F20);
1278 + regmap_write(xs->regmap_pextp[id], 0x0030, 0x00050C00);
1279 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x02002800);
1280 + ndelay(1020);
1281 + regmap_write(xs->regmap_pextp[id], 0x30B0, 0x00000020);
1282 + regmap_write(xs->regmap_pextp[id], 0x3028, 0x00008A01);
1283 + regmap_write(xs->regmap_pextp[id], 0x302C, 0x0000A884);
1284 + regmap_write(xs->regmap_pextp[id], 0x3024, 0x00083002);
1285 + regmap_write(xs->regmap_pextp[id], 0x3010, 0x00022220);
1286 + regmap_write(xs->regmap_pextp[id], 0x5064, 0x0F020A01);
1287 + regmap_write(xs->regmap_pextp[id], 0x50B4, 0x06100600);
1288 + regmap_write(xs->regmap_pextp[id], 0x3048, 0x40704000);
1289 + regmap_write(xs->regmap_pextp[id], 0x3050, 0xA8000000);
1290 + regmap_write(xs->regmap_pextp[id], 0x3054, 0x000000AA);
1291 + regmap_write(xs->regmap_pextp[id], 0x306C, 0x00000F00);
1292 + regmap_write(xs->regmap_pextp[id], 0xA060, 0x00040000);
1293 + regmap_write(xs->regmap_pextp[id], 0x90D0, 0x00000003);
1294 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200E800);
1295 + udelay(150);
1296 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200C111);
1297 + ndelay(1020);
1298 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200C101);
1299 + udelay(15);
1300 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0202C111);
1301 + ndelay(1020);
1302 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0202C101);
1303 + udelay(100);
1304 + regmap_write(xs->regmap_pextp[id], 0x30B0, 0x00000030);
1305 + regmap_write(xs->regmap_pextp[id], 0x00F4, 0x80201F00);
1306 + regmap_write(xs->regmap_pextp[id], 0x3040, 0x30000000);
1307 + udelay(400);
1308 +}
1309 +
1310 +void mtk_usxgmii_setup_phya_force_10000(struct mtk_eth *eth, int mac_id)
1311 +{
1312 + struct mtk_xgmii *xs = eth->xgmii;
1313 + unsigned int val;
1314 + u32 id = mtk_mac2xgmii_id(eth, mac_id);
1315 +
1316 + if (id >= eth->soc->num_devs ||
1317 + !xs->regmap_usxgmii[id] || !xs->regmap_pextp[id])
1318 + return;
1319 +
1320 + /* Setup USXGMII speed */
1321 + val = FIELD_PREP(RG_XFI_RX_MODE, RG_XFI_RX_MODE_10G) |
1322 + FIELD_PREP(RG_XFI_TX_MODE, RG_XFI_TX_MODE_10G);
1323 + regmap_write(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
1324 +
1325 + /* Disable USXGMII AN mode */
1326 + regmap_read(xs->regmap_usxgmii[id], RG_PCS_AN_CTRL0, &val);
1327 + val &= ~RG_AN_ENABLE;
1328 + regmap_write(xs->regmap_usxgmii[id], RG_PCS_AN_CTRL0, val);
1329 +
1330 + /* Gated USXGMII */
1331 + regmap_read(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
1332 + val |= RG_MAC_CK_GATED;
1333 + regmap_write(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
1334 +
1335 + ndelay(1020);
1336 +
1337 + /* USXGMII force mode setting */
1338 + regmap_read(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
1339 + val |= RG_USXGMII_RATE_UPDATE_MODE;
1340 + val |= RG_IF_FORCE_EN;
1341 + val |= FIELD_PREP(RG_RATE_ADAPT_MODE, RG_RATE_ADAPT_MODE_X1);
1342 + regmap_write(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
1343 +
1344 + /* Un-gated USXGMII */
1345 + regmap_read(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, &val);
1346 + val &= ~RG_MAC_CK_GATED;
1347 + regmap_write(xs->regmap_usxgmii[id], RG_PHY_TOP_SPEED_CTRL1, val);
1348 +
1349 + ndelay(1020);
1350 +
1351 + regmap_write(xs->regmap_pextp[id], 0x9024, 0x00C9071C);
1352 + regmap_write(xs->regmap_pextp[id], 0x2020, 0xAA8585AA);
1353 + regmap_write(xs->regmap_pextp[id], 0x2030, 0x0C020707);
1354 + regmap_write(xs->regmap_pextp[id], 0x2034, 0x0E050F0F);
1355 + regmap_write(xs->regmap_pextp[id], 0x2040, 0x00140032);
1356 + regmap_write(xs->regmap_pextp[id], 0x50F0, 0x00C014AA);
1357 + regmap_write(xs->regmap_pextp[id], 0x50E0, 0x3777C12B);
1358 + regmap_write(xs->regmap_pextp[id], 0x506C, 0x005F9CFF);
1359 + regmap_write(xs->regmap_pextp[id], 0x5070, 0x9D9DFAFA);
1360 + regmap_write(xs->regmap_pextp[id], 0x5074, 0x27273F3F);
1361 + regmap_write(xs->regmap_pextp[id], 0x5078, 0xA7883C68);
1362 + regmap_write(xs->regmap_pextp[id], 0x507C, 0x11661166);
1363 + regmap_write(xs->regmap_pextp[id], 0x5080, 0x0E000AAF);
1364 + regmap_write(xs->regmap_pextp[id], 0x5084, 0x08080D0D);
1365 + regmap_write(xs->regmap_pextp[id], 0x5088, 0x02030909);
1366 + regmap_write(xs->regmap_pextp[id], 0x50E4, 0x0C0C0000);
1367 + regmap_write(xs->regmap_pextp[id], 0x50E8, 0x04040000);
1368 + regmap_write(xs->regmap_pextp[id], 0x50EC, 0x0F0F0C06);
1369 + regmap_write(xs->regmap_pextp[id], 0x50A8, 0x506E8C8C);
1370 + regmap_write(xs->regmap_pextp[id], 0x6004, 0x18190000);
1371 + regmap_write(xs->regmap_pextp[id], 0x00F8, 0x01423342);
1372 + regmap_write(xs->regmap_pextp[id], 0x00F4, 0x80201F20);
1373 + regmap_write(xs->regmap_pextp[id], 0x0030, 0x00050C00);
1374 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x02002800);
1375 + ndelay(1020);
1376 + regmap_write(xs->regmap_pextp[id], 0x30B0, 0x00000020);
1377 + regmap_write(xs->regmap_pextp[id], 0x3028, 0x00008A01);
1378 + regmap_write(xs->regmap_pextp[id], 0x302C, 0x0000A884);
1379 + regmap_write(xs->regmap_pextp[id], 0x3024, 0x00083002);
1380 + regmap_write(xs->regmap_pextp[id], 0x3010, 0x00022220);
1381 + regmap_write(xs->regmap_pextp[id], 0x5064, 0x0F020A01);
1382 + regmap_write(xs->regmap_pextp[id], 0x50B4, 0x06100600);
1383 + regmap_write(xs->regmap_pextp[id], 0x3048, 0x49664100);
1384 + regmap_write(xs->regmap_pextp[id], 0x3050, 0x00000000);
1385 + regmap_write(xs->regmap_pextp[id], 0x3054, 0x00000000);
1386 + regmap_write(xs->regmap_pextp[id], 0x306C, 0x00000F00);
1387 + regmap_write(xs->regmap_pextp[id], 0xA060, 0x00040000);
1388 + regmap_write(xs->regmap_pextp[id], 0x90D0, 0x00000001);
1389 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200E800);
1390 + udelay(150);
1391 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200C111);
1392 + ndelay(1020);
1393 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200C101);
1394 + udelay(15);
1395 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0202C111);
1396 + ndelay(1020);
1397 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0202C101);
1398 + udelay(100);
1399 + regmap_write(xs->regmap_pextp[id], 0x30B0, 0x00000030);
1400 + regmap_write(xs->regmap_pextp[id], 0x00F4, 0x80201F00);
1401 + regmap_write(xs->regmap_pextp[id], 0x3040, 0x30000000);
1402 + udelay(400);
1403 +}
1404 +
1405 +void mtk_usxgmii_reset(struct mtk_eth *eth, int mac_id)
1406 +{
1407 + u32 id = mtk_mac2xgmii_id(eth, mac_id);
1408 +
1409 + if (id >= eth->soc->num_devs || !eth->toprgu)
1410 + return;
1411 +
1412 + switch (mac_id) {
1413 + case MTK_GMAC2_ID:
1414 + regmap_write(eth->toprgu, 0xFC, 0x0000A004);
1415 + regmap_write(eth->toprgu, 0x18, 0x88F0A004);
1416 + regmap_write(eth->toprgu, 0xFC, 0x00000000);
1417 + regmap_write(eth->toprgu, 0x18, 0x88F00000);
1418 + regmap_write(eth->toprgu, 0x18, 0x00F00000);
1419 + break;
1420 + case MTK_GMAC3_ID:
1421 + regmap_write(eth->toprgu, 0xFC, 0x00005002);
1422 + regmap_write(eth->toprgu, 0x18, 0x88F05002);
1423 + regmap_write(eth->toprgu, 0xFC, 0x00000000);
1424 + regmap_write(eth->toprgu, 0x18, 0x88F00000);
1425 + regmap_write(eth->toprgu, 0x18, 0x00F00000);
1426 + break;
1427 + }
1428 +
1429 + mdelay(10);
1430 +}
1431 +
1432 +int mtk_usxgmii_setup_mode_an(struct mtk_eth *eth, int mac_id, int max_speed)
1433 +{
1434 + if (mac_id < 0 || mac_id >= eth->soc->num_devs)
1435 + return -EINVAL;
1436 +
1437 + if ((max_speed != SPEED_10000) && (max_speed != SPEED_5000))
1438 + return -EINVAL;
1439 +
1440 + mtk_xfi_pll_enable(eth);
1441 + mtk_usxgmii_reset(eth, mac_id);
1442 + mtk_usxgmii_setup_phya_an_10000(eth, mac_id);
1443 +
1444 + return 0;
1445 +}
1446 +
1447 +int mtk_usxgmii_setup_mode_force(struct mtk_eth *eth, int mac_id,
1448 + const struct phylink_link_state *state)
1449 +{
1450 + if (mac_id < 0 || mac_id >= eth->soc->num_devs)
1451 + return -EINVAL;
1452 +
1453 + mtk_xfi_pll_enable(eth);
1454 + mtk_usxgmii_reset(eth, mac_id);
1455 + if (state->interface == PHY_INTERFACE_MODE_5GBASER)
1456 + mtk_usxgmii_setup_phya_force_5000(eth, mac_id);
1457 + else
1458 + mtk_usxgmii_setup_phya_force_10000(eth, mac_id);
1459 +
1460 + return 0;
1461 +}
1462 +
1463 +void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id)
1464 +{
1465 + u32 id = mtk_mac2xgmii_id(eth, mac_id);
1466 + struct mtk_xgmii *xs = eth->xgmii;
1467 +
1468 + if (id >= eth->soc->num_devs || !xs->regmap_pextp[id])
1469 + return;
1470 +
1471 + regmap_write(xs->regmap_pextp[id], 0x9024, 0x00D9071C);
1472 + regmap_write(xs->regmap_pextp[id], 0x2020, 0xAA8585AA);
1473 + regmap_write(xs->regmap_pextp[id], 0x2030, 0x0C020207);
1474 + regmap_write(xs->regmap_pextp[id], 0x2034, 0x0E05050F);
1475 + regmap_write(xs->regmap_pextp[id], 0x2040, 0x00200032);
1476 + regmap_write(xs->regmap_pextp[id], 0x50F0, 0x00C014BA);
1477 + regmap_write(xs->regmap_pextp[id], 0x50E0, 0x3777C12B);
1478 + regmap_write(xs->regmap_pextp[id], 0x506C, 0x005F9CFF);
1479 + regmap_write(xs->regmap_pextp[id], 0x5070, 0x9D9DFAFA);
1480 + regmap_write(xs->regmap_pextp[id], 0x5074, 0x27273F3F);
1481 + regmap_write(xs->regmap_pextp[id], 0x5078, 0xA7883C68);
1482 + regmap_write(xs->regmap_pextp[id], 0x507C, 0x11661166);
1483 + regmap_write(xs->regmap_pextp[id], 0x5080, 0x0E000EAF);
1484 + regmap_write(xs->regmap_pextp[id], 0x5084, 0x08080E0D);
1485 + regmap_write(xs->regmap_pextp[id], 0x5088, 0x02030B09);
1486 + regmap_write(xs->regmap_pextp[id], 0x50E4, 0x0C0C0000);
1487 + regmap_write(xs->regmap_pextp[id], 0x50E8, 0x04040000);
1488 + regmap_write(xs->regmap_pextp[id], 0x50EC, 0x0F0F0606);
1489 + regmap_write(xs->regmap_pextp[id], 0x50A8, 0x506E8C8C);
1490 + regmap_write(xs->regmap_pextp[id], 0x6004, 0x18190000);
1491 + regmap_write(xs->regmap_pextp[id], 0x00F8, 0x00FA32FA);
1492 + regmap_write(xs->regmap_pextp[id], 0x00F4, 0x80201F21);
1493 + regmap_write(xs->regmap_pextp[id], 0x0030, 0x00050C00);
1494 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x02002800);
1495 + ndelay(1020);
1496 + regmap_write(xs->regmap_pextp[id], 0x30B0, 0x00000020);
1497 + regmap_write(xs->regmap_pextp[id], 0x3028, 0x00008A01);
1498 + regmap_write(xs->regmap_pextp[id], 0x302C, 0x0000A884);
1499 + regmap_write(xs->regmap_pextp[id], 0x3024, 0x00083002);
1500 + regmap_write(xs->regmap_pextp[id], 0x3010, 0x00011110);
1501 + regmap_write(xs->regmap_pextp[id], 0x3048, 0x40704000);
1502 + regmap_write(xs->regmap_pextp[id], 0x3064, 0x0000C000);
1503 + regmap_write(xs->regmap_pextp[id], 0x3050, 0xA8000000);
1504 + regmap_write(xs->regmap_pextp[id], 0x3054, 0x000000AA);
1505 + regmap_write(xs->regmap_pextp[id], 0x306C, 0x20200F00);
1506 + regmap_write(xs->regmap_pextp[id], 0xA060, 0x00050000);
1507 + regmap_write(xs->regmap_pextp[id], 0x90D0, 0x00000007);
1508 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200E800);
1509 + udelay(150);
1510 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200C111);
1511 + ndelay(1020);
1512 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200C101);
1513 + udelay(15);
1514 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0201C111);
1515 + ndelay(1020);
1516 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0201C101);
1517 + udelay(100);
1518 + regmap_write(xs->regmap_pextp[id], 0x30B0, 0x00000030);
1519 + regmap_write(xs->regmap_pextp[id], 0x00F4, 0x80201F01);
1520 + regmap_write(xs->regmap_pextp[id], 0x3040, 0x30000000);
1521 + udelay(400);
1522 +}
1523 +
1524 +void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id)
1525 +{
1526 + struct mtk_xgmii *xs = eth->xgmii;
1527 + u32 id = mtk_mac2xgmii_id(eth, mac_id);
1528 +
1529 + if (id >= eth->soc->num_devs || !xs->regmap_pextp[id])
1530 + return;
1531 +
1532 + regmap_write(xs->regmap_pextp[id], 0x9024, 0x00D9071C);
1533 + regmap_write(xs->regmap_pextp[id], 0x2020, 0xAA8585AA);
1534 + regmap_write(xs->regmap_pextp[id], 0x2030, 0x0C020707);
1535 + regmap_write(xs->regmap_pextp[id], 0x2034, 0x0E050F0F);
1536 + regmap_write(xs->regmap_pextp[id], 0x2040, 0x00140032);
1537 + regmap_write(xs->regmap_pextp[id], 0x50F0, 0x00C014AA);
1538 + regmap_write(xs->regmap_pextp[id], 0x50E0, 0x3777C12B);
1539 + regmap_write(xs->regmap_pextp[id], 0x506C, 0x005F9CFF);
1540 + regmap_write(xs->regmap_pextp[id], 0x5070, 0x9D9DFAFA);
1541 + regmap_write(xs->regmap_pextp[id], 0x5074, 0x27273F3F);
1542 + regmap_write(xs->regmap_pextp[id], 0x5078, 0xA7883C68);
1543 + regmap_write(xs->regmap_pextp[id], 0x507C, 0x11661166);
1544 + regmap_write(xs->regmap_pextp[id], 0x5080, 0x0E000AAF);
1545 + regmap_write(xs->regmap_pextp[id], 0x5084, 0x08080D0D);
1546 + regmap_write(xs->regmap_pextp[id], 0x5088, 0x02030909);
1547 + regmap_write(xs->regmap_pextp[id], 0x50E4, 0x0C0C0000);
1548 + regmap_write(xs->regmap_pextp[id], 0x50E8, 0x04040000);
1549 + regmap_write(xs->regmap_pextp[id], 0x50EC, 0x0F0F0C06);
1550 + regmap_write(xs->regmap_pextp[id], 0x50A8, 0x506E8C8C);
1551 + regmap_write(xs->regmap_pextp[id], 0x6004, 0x18190000);
1552 + regmap_write(xs->regmap_pextp[id], 0x00F8, 0x009C329C);
1553 + regmap_write(xs->regmap_pextp[id], 0x00F4, 0x80201F21);
1554 + regmap_write(xs->regmap_pextp[id], 0x0030, 0x00050C00);
1555 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x02002800);
1556 + ndelay(1020);
1557 + regmap_write(xs->regmap_pextp[id], 0x30B0, 0x00000020);
1558 + regmap_write(xs->regmap_pextp[id], 0x3028, 0x00008A01);
1559 + regmap_write(xs->regmap_pextp[id], 0x302C, 0x0000A884);
1560 + regmap_write(xs->regmap_pextp[id], 0x3024, 0x00083002);
1561 + regmap_write(xs->regmap_pextp[id], 0x3010, 0x00011110);
1562 + regmap_write(xs->regmap_pextp[id], 0x3048, 0x40704000);
1563 + regmap_write(xs->regmap_pextp[id], 0x3050, 0xA8000000);
1564 + regmap_write(xs->regmap_pextp[id], 0x3054, 0x000000AA);
1565 + regmap_write(xs->regmap_pextp[id], 0x306C, 0x22000F00);
1566 + regmap_write(xs->regmap_pextp[id], 0xA060, 0x00050000);
1567 + regmap_write(xs->regmap_pextp[id], 0x90D0, 0x00000005);
1568 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200E800);
1569 + udelay(150);
1570 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200C111);
1571 + ndelay(1020);
1572 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0200C101);
1573 + udelay(15);
1574 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0201C111);
1575 + ndelay(1020);
1576 + regmap_write(xs->regmap_pextp[id], 0x0070, 0x0201C101);
1577 + udelay(100);
1578 + regmap_write(xs->regmap_pextp[id], 0x30B0, 0x00000030);
1579 + regmap_write(xs->regmap_pextp[id], 0x00F4, 0x80201F01);
1580 + regmap_write(xs->regmap_pextp[id], 0x3040, 0x30000000);
1581 + udelay(400);
1582 +}
1583 +
1584 +void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id)
1585 +{
1586 + u32 id = mtk_mac2xgmii_id(eth, mac_id);
1587 + u32 val = 0;
1588 +
1589 + if (id >= eth->soc->num_devs || !eth->toprgu)
1590 + return;
1591 +
1592 + switch (mac_id) {
1593 + case MTK_GMAC2_ID:
1594 + /* Enable software reset */
1595 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
1596 + val |= SWSYSRST_XFI_PEXPT1_GRST |
1597 + SWSYSRST_SGMII1_GRST;
1598 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
1599 +
1600 + /* Assert SGMII reset */
1601 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
1602 + val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) |
1603 + SWSYSRST_XFI_PEXPT1_GRST |
1604 + SWSYSRST_SGMII1_GRST;
1605 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
1606 +
1607 + udelay(100);
1608 +
1609 + /* De-assert SGMII reset */
1610 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
1611 + val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88);
1612 + val &= ~(SWSYSRST_XFI_PEXPT1_GRST |
1613 + SWSYSRST_SGMII1_GRST);
1614 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
1615 +
1616 + /* Disable software reset */
1617 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
1618 + val &= ~(SWSYSRST_XFI_PEXPT1_GRST |
1619 + SWSYSRST_SGMII1_GRST);
1620 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
1621 + break;
1622 + case MTK_GMAC3_ID:
1623 + /* Enable Software reset */
1624 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
1625 + val |= SWSYSRST_XFI_PEXPT0_GRST |
1626 + SWSYSRST_SGMII0_GRST;
1627 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
1628 +
1629 + /* Assert SGMII reset */
1630 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
1631 + val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) |
1632 + SWSYSRST_XFI_PEXPT0_GRST |
1633 + SWSYSRST_SGMII0_GRST;
1634 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
1635 +
1636 + udelay(100);
1637 +
1638 + /* De-assert SGMII reset */
1639 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
1640 + val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88);
1641 + val &= ~(SWSYSRST_XFI_PEXPT0_GRST |
1642 + SWSYSRST_SGMII0_GRST);
1643 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
1644 +
1645 + /* Disable software reset */
1646 + regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val);
1647 + val &= ~(SWSYSRST_XFI_PEXPT0_GRST |
1648 + SWSYSRST_SGMII0_GRST);
1649 + regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val);
1650 + break;
1651 + }
1652 +
1653 + mdelay(1);
1654 +}
1655 --- a/drivers/net/ethernet/mediatek/Kconfig
1656 +++ b/drivers/net/ethernet/mediatek/Kconfig
1657 @@ -11,6 +11,14 @@ config NET_MEDIATEK_SOC_WED
1658 depends on ARCH_MEDIATEK || COMPILE_TEST
1659 def_bool NET_MEDIATEK_SOC != n
1660
1661 +config NET_MEDIATEK_SOC_USXGMII
1662 + bool "Support USXGMII SerDes on MT7988"
1663 + depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
1664 + def_bool NET_MEDIATEK_SOC != n
1665 + help
1666 + Include support for 10G USXGMII SerDes unit which can
1667 + be found on MT7988.
1668 +
1669 config NET_MEDIATEK_SOC
1670 tristate "MediaTek SoC Gigabit Ethernet support"
1671 depends on NET_DSA || !NET_DSA
Hauke Mehrtens staging tree