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generic: add support for MediaTek NETSYS v3
[openwrt/staging/hauke.git] / target / linux / generic / pending-5.15 / 737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch
1 From 663fa1b7e0cb2c929008482014a70c6625caad75 Mon Sep 17 00:00:00 2001
2 From: Lorenzo Bianconi <lorenzo@kernel.org>
3 Date: Tue, 7 Mar 2023 15:55:13 +0000
4 Subject: [PATCH 1/7] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V1 capability
5 bit
6
7 Introduce MTK_NETSYS_V1 bit in the device capabilities for
8 MT7621/MT7622/MT7623/MT7628/MT7629 SoCs.
9 Use !MTK_NETSYS_V1 instead of MTK_NETSYS_V2 in the driver codebase.
10 This is a preliminary patch to introduce support for MT7988 SoC.
11
12 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
13 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
14 ---
15 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 +++++++-------
16 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 45 ++++++++++++---------
17 2 files changed, 41 insertions(+), 34 deletions(-)
18
19 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
20 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
21 @@ -597,7 +597,7 @@ static void mtk_set_queue_speed(struct m
22 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
23 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
24 MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
25 - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
26 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
27 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
28
29 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
30 @@ -974,7 +974,7 @@ static bool mtk_rx_get_desc(struct mtk_e
31 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
32 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
33 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
34 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
35 + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
36 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
37 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
38 }
39 @@ -1032,7 +1032,7 @@ static int mtk_init_fq_dma(struct mtk_et
40
41 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
42 txd->txd4 = 0;
43 - if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
44 + if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) {
45 txd->txd5 = 0;
46 txd->txd6 = 0;
47 txd->txd7 = 0;
48 @@ -1221,7 +1221,7 @@ static void mtk_tx_set_dma_desc(struct n
49 struct mtk_mac *mac = netdev_priv(dev);
50 struct mtk_eth *eth = mac->hw;
51
52 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
53 + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
54 mtk_tx_set_dma_desc_v2(dev, txd, info);
55 else
56 mtk_tx_set_dma_desc_v1(dev, txd, info);
57 @@ -1902,7 +1902,7 @@ static int mtk_poll_rx(struct napi_struc
58 break;
59
60 /* find out which mac the packet come from. values start at 1 */
61 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
62 + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
63 mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
64 else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
65 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
66 @@ -1998,7 +1998,7 @@ static int mtk_poll_rx(struct napi_struc
67 skb->dev = netdev;
68 bytes += skb->len;
69
70 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
71 + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
72 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
73 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
74 if (hash != MTK_RXD5_FOE_ENTRY)
75 @@ -2023,7 +2023,7 @@ static int mtk_poll_rx(struct napi_struc
76 /* When using VLAN untagging in combination with DSA, the
77 * hardware treats the MTK special tag as a VLAN and untags it.
78 */
79 - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) &&
80 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1) &&
81 (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) {
82 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
83
84 @@ -2328,7 +2328,7 @@ static int mtk_tx_alloc(struct mtk_eth *
85 txd->txd2 = next_ptr;
86 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
87 txd->txd4 = 0;
88 - if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) {
89 + if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) {
90 txd->txd5 = 0;
91 txd->txd6 = 0;
92 txd->txd7 = 0;
93 @@ -2381,7 +2381,7 @@ static int mtk_tx_alloc(struct mtk_eth *
94 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
95 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
96 MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
97 - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
98 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
99 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
100 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
101 ofs += MTK_QTX_OFFSET;
102 @@ -2515,7 +2515,7 @@ static int mtk_rx_alloc(struct mtk_eth *
103
104 rxd->rxd3 = 0;
105 rxd->rxd4 = 0;
106 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
107 + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
108 rxd->rxd5 = 0;
109 rxd->rxd6 = 0;
110 rxd->rxd7 = 0;
111 @@ -3063,7 +3063,7 @@ static int mtk_start_dma(struct mtk_eth
112 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
113 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
114
115 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
116 + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
117 val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
118 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
119 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
120 @@ -3475,7 +3475,7 @@ static void mtk_hw_reset(struct mtk_eth
121 {
122 u32 val;
123
124 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
125 + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
126 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
127 val = RSTCTRL_PPE0_V2;
128 } else {
129 @@ -3487,7 +3487,7 @@ static void mtk_hw_reset(struct mtk_eth
130
131 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
132
133 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
134 + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1))
135 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
136 0x3ffffff);
137 }
138 @@ -3683,7 +3683,7 @@ static int mtk_hw_init(struct mtk_eth *e
139 else
140 mtk_hw_reset(eth);
141
142 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
143 + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
144 /* Set FE to PDMAv2 if necessary */
145 val = mtk_r32(eth, MTK_FE_GLO_MISC);
146 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
147 @@ -3720,7 +3720,7 @@ static int mtk_hw_init(struct mtk_eth *e
148 */
149 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
150 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
151 - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
152 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) {
153 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
154 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
155
156 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
157 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
158 @@ -816,6 +816,7 @@ enum mkt_eth_capabilities {
159 MTK_SHARED_INT_BIT,
160 MTK_TRGMII_MT7621_CLK_BIT,
161 MTK_QDMA_BIT,
162 + MTK_NETSYS_V1_BIT,
163 MTK_NETSYS_V2_BIT,
164 MTK_SOC_MT7628_BIT,
165 MTK_RSTCTRL_PPE1_BIT,
166 @@ -851,6 +852,7 @@ enum mkt_eth_capabilities {
167 #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT)
168 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
169 #define MTK_QDMA BIT(MTK_QDMA_BIT)
170 +#define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT)
171 #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
172 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
173 #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT)
174 @@ -913,25 +915,30 @@ enum mkt_eth_capabilities {
175
176 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x) & ~(MTK_CAP_MASK)) == (_x))
177
178 -#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
179 - MTK_GMAC2_RGMII | MTK_SHARED_INT | \
180 - MTK_TRGMII_MT7621_CLK | MTK_QDMA)
181 -
182 -#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
183 - MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
184 - MTK_MUX_GDM1_TO_GMAC1_ESW | \
185 - MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA)
186 -
187 -#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \
188 - MTK_QDMA)
189 -
190 -#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628)
191 -
192 -#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
193 - MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
194 - MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
195 - MTK_MUX_U3_GMAC2_TO_QPHY | \
196 - MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
197 +#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
198 + MTK_GMAC2_RGMII | MTK_SHARED_INT | \
199 + MTK_TRGMII_MT7621_CLK | MTK_QDMA | \
200 + MTK_NETSYS_V1)
201 +
202 +#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | \
203 + MTK_GMAC2_RGMII | MTK_GMAC2_SGMII | \
204 + MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW |\
205 + MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | \
206 + MTK_QDMA | MTK_NETSYS_V1)
207 +
208 +#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
209 + MTK_GMAC2_RGMII | MTK_QDMA | \
210 + MTK_NETSYS_V1)
211 +
212 +#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628 | \
213 + MTK_NETSYS_V1)
214 +
215 +#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
216 + MTK_GMAC2_GEPHY | MTK_GDM1_ESW | \
217 + MTK_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_QDMA | \
218 + MTK_MUX_U3_GMAC2_TO_QPHY | MTK_NETSYS_V1 |\
219 + MTK_MUX_GDM1_TO_GMAC1_ESW | \
220 + MTK_MUX_GMAC12_TO_GEPHY_SGMII)
221
222 #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
223 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
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