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kernel: backport SSB/BCMA changes in preparation for a compat-wireless update
[openwrt/staging/jow.git] / target / linux / generic / patches-3.6 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -48,12 +48,12 @@ config BCMA_DRIVER_MIPS
4
5 config BCMA_SFLASH
6 bool
7 - depends on BCMA_DRIVER_MIPS && BROKEN
8 + depends on BCMA_DRIVER_MIPS
9 default y
10
11 config BCMA_NFLASH
12 bool
13 - depends on BCMA_DRIVER_MIPS && BROKEN
14 + depends on BCMA_DRIVER_MIPS
15 default y
16
17 config BCMA_DRIVER_GMAC_CMN
18 @@ -65,6 +65,14 @@ config BCMA_DRIVER_GMAC_CMN
19
20 If unsure, say N
21
22 +config BCMA_DRIVER_GPIO
23 + bool "BCMA GPIO driver"
24 + depends on BCMA && GPIOLIB
25 + help
26 + Driver to provide access to the GPIO pins of the bcma bus.
27 +
28 + If unsure, say N
29 +
30 config BCMA_DEBUG
31 bool "BCMA debugging"
32 depends on BCMA
33 --- a/drivers/bcma/Makefile
34 +++ b/drivers/bcma/Makefile
35 @@ -6,6 +6,7 @@ bcma-y += driver_pci.o
36 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
37 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
38 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
39 +bcma-$(CONFIG_BCMA_DRIVER_GPIO) += driver_gpio.o
40 bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
41 bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
42 obj-$(CONFIG_BCMA) += bcma.o
43 --- a/drivers/bcma/bcma_private.h
44 +++ b/drivers/bcma/bcma_private.h
45 @@ -31,6 +31,8 @@ int __init bcma_bus_early_register(struc
46 int bcma_bus_suspend(struct bcma_bus *bus);
47 int bcma_bus_resume(struct bcma_bus *bus);
48 #endif
49 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
50 + u8 unit);
51
52 /* scan.c */
53 int bcma_bus_scan(struct bcma_bus *bus);
54 @@ -48,12 +50,13 @@ void bcma_chipco_serial_init(struct bcma
55 #endif /* CONFIG_BCMA_DRIVER_MIPS */
56
57 /* driver_chipcommon_pmu.c */
58 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
59 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
60 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
61 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
62
63 #ifdef CONFIG_BCMA_SFLASH
64 /* driver_chipcommon_sflash.c */
65 int bcma_sflash_init(struct bcma_drv_cc *cc);
66 +extern struct platform_device bcma_sflash_dev;
67 #else
68 static inline int bcma_sflash_init(struct bcma_drv_cc *cc)
69 {
70 @@ -65,6 +68,7 @@ static inline int bcma_sflash_init(struc
71 #ifdef CONFIG_BCMA_NFLASH
72 /* driver_chipcommon_nflash.c */
73 int bcma_nflash_init(struct bcma_drv_cc *cc);
74 +extern struct platform_device bcma_nflash_dev;
75 #else
76 static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
77 {
78 @@ -82,9 +86,21 @@ extern void __exit bcma_host_pci_exit(vo
79 /* driver_pci.c */
80 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
81
82 +extern int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc);
83 +
84 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
85 bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
86 void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
87 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
88
89 +#ifdef CONFIG_BCMA_DRIVER_GPIO
90 +/* driver_gpio.c */
91 +int bcma_gpio_init(struct bcma_drv_cc *cc);
92 +#else
93 +static inline int bcma_gpio_init(struct bcma_drv_cc *cc)
94 +{
95 + return -ENOTSUPP;
96 +}
97 +#endif /* CONFIG_BCMA_DRIVER_GPIO */
98 +
99 #endif
100 --- a/drivers/bcma/core.c
101 +++ b/drivers/bcma/core.c
102 @@ -65,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma
103 switch (clkmode) {
104 case BCMA_CLKMODE_FAST:
105 bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
106 - udelay(64);
107 + usleep_range(64, 300);
108 for (i = 0; i < 1500; i++) {
109 if (bcma_read32(core, BCMA_CLKCTLST) &
110 BCMA_CLKCTLST_HAVEHT) {
111 --- a/drivers/bcma/driver_chipcommon.c
112 +++ b/drivers/bcma/driver_chipcommon.c
113 @@ -4,12 +4,15 @@
114 *
115 * Copyright 2005, Broadcom Corporation
116 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
117 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
118 *
119 * Licensed under the GNU/GPL. See COPYING for details.
120 */
121
122 #include "bcma_private.h"
123 +#include <linux/bcm47xx_wdt.h>
124 #include <linux/export.h>
125 +#include <linux/platform_device.h>
126 #include <linux/bcma/bcma.h>
127
128 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
129 @@ -22,20 +25,120 @@ static inline u32 bcma_cc_write32_masked
130 return value;
131 }
132
133 -void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
134 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
135 {
136 - u32 leddc_on = 10;
137 - u32 leddc_off = 90;
138 + if (cc->capabilities & BCMA_CC_CAP_PMU)
139 + return bcma_pmu_get_alp_clock(cc);
140
141 - if (cc->setup_done)
142 + return 20000000;
143 +}
144 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
145 +
146 +static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
147 +{
148 + struct bcma_bus *bus = cc->core->bus;
149 + u32 nb;
150 +
151 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
152 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
153 + nb = 32;
154 + else if (cc->core->id.rev < 26)
155 + nb = 16;
156 + else
157 + nb = (cc->core->id.rev >= 37) ? 32 : 24;
158 + } else {
159 + nb = 28;
160 + }
161 + if (nb == 32)
162 + return 0xffffffff;
163 + else
164 + return (1 << nb) - 1;
165 +}
166 +
167 +static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
168 + u32 ticks)
169 +{
170 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
171 +
172 + return bcma_chipco_watchdog_timer_set(cc, ticks);
173 +}
174 +
175 +static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
176 + u32 ms)
177 +{
178 + struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
179 + u32 ticks;
180 +
181 + ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
182 + return ticks / cc->ticks_per_ms;
183 +}
184 +
185 +static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
186 +{
187 + struct bcma_bus *bus = cc->core->bus;
188 +
189 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
190 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
191 + /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */
192 + return bcma_chipco_get_alp_clock(cc) / 4000;
193 + else
194 + /* based on 32KHz ILP clock */
195 + return 32;
196 + } else {
197 + return bcma_chipco_get_alp_clock(cc) / 1000;
198 + }
199 +}
200 +
201 +int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
202 +{
203 + struct bcm47xx_wdt wdt = {};
204 + struct platform_device *pdev;
205 +
206 + wdt.driver_data = cc;
207 + wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
208 + wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
209 + wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
210 +
211 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
212 + cc->core->bus->num, &wdt,
213 + sizeof(wdt));
214 + if (IS_ERR(pdev))
215 + return PTR_ERR(pdev);
216 +
217 + cc->watchdog = pdev;
218 +
219 + return 0;
220 +}
221 +
222 +void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
223 +{
224 + if (cc->early_setup_done)
225 return;
226
227 + spin_lock_init(&cc->gpio_lock);
228 +
229 if (cc->core->id.rev >= 11)
230 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
231 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
232 if (cc->core->id.rev >= 35)
233 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
234
235 + if (cc->capabilities & BCMA_CC_CAP_PMU)
236 + bcma_pmu_early_init(cc);
237 +
238 + cc->early_setup_done = true;
239 +}
240 +
241 +void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
242 +{
243 + u32 leddc_on = 10;
244 + u32 leddc_off = 90;
245 +
246 + if (cc->setup_done)
247 + return;
248 +
249 + bcma_core_chipcommon_early_init(cc);
250 +
251 if (cc->core->id.rev >= 20) {
252 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
253 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
254 @@ -56,15 +159,33 @@ void bcma_core_chipcommon_init(struct bc
255 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
256 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
257 }
258 + cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
259
260 cc->setup_done = true;
261 }
262
263 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
264 -void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
265 +u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
266 {
267 - /* instant NMI */
268 - bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
269 + u32 maxt;
270 + enum bcma_clkmode clkmode;
271 +
272 + maxt = bcma_chipco_watchdog_get_max_timer(cc);
273 + if (cc->capabilities & BCMA_CC_CAP_PMU) {
274 + if (ticks == 1)
275 + ticks = 2;
276 + else if (ticks > maxt)
277 + ticks = maxt;
278 + bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
279 + } else {
280 + clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC;
281 + bcma_core_set_clockmode(cc->core, clkmode);
282 + if (ticks > maxt)
283 + ticks = maxt;
284 + /* instant NMI */
285 + bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
286 + }
287 + return ticks;
288 }
289
290 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
291 @@ -84,28 +205,99 @@ u32 bcma_chipco_gpio_in(struct bcma_drv_
292
293 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
294 {
295 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
296 + unsigned long flags;
297 + u32 res;
298 +
299 + spin_lock_irqsave(&cc->gpio_lock, flags);
300 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
301 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
302 +
303 + return res;
304 }
305 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
306
307 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
308 {
309 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
310 + unsigned long flags;
311 + u32 res;
312 +
313 + spin_lock_irqsave(&cc->gpio_lock, flags);
314 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
315 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
316 +
317 + return res;
318 }
319 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
320
321 +/*
322 + * If the bit is set to 0, chipcommon controlls this GPIO,
323 + * if the bit is set to 1, it is used by some part of the chip and not our code.
324 + */
325 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
326 {
327 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
328 + unsigned long flags;
329 + u32 res;
330 +
331 + spin_lock_irqsave(&cc->gpio_lock, flags);
332 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
333 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
334 +
335 + return res;
336 }
337 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
338
339 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
340 {
341 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
342 + unsigned long flags;
343 + u32 res;
344 +
345 + spin_lock_irqsave(&cc->gpio_lock, flags);
346 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
347 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
348 +
349 + return res;
350 }
351
352 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
353 {
354 - return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
355 + unsigned long flags;
356 + u32 res;
357 +
358 + spin_lock_irqsave(&cc->gpio_lock, flags);
359 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
360 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
361 +
362 + return res;
363 +}
364 +
365 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
366 +{
367 + unsigned long flags;
368 + u32 res;
369 +
370 + if (cc->core->id.rev < 20)
371 + return 0;
372 +
373 + spin_lock_irqsave(&cc->gpio_lock, flags);
374 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
375 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
376 +
377 + return res;
378 +}
379 +
380 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
381 +{
382 + unsigned long flags;
383 + u32 res;
384 +
385 + if (cc->core->id.rev < 20)
386 + return 0;
387 +
388 + spin_lock_irqsave(&cc->gpio_lock, flags);
389 + res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
390 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
391 +
392 + return res;
393 }
394
395 #ifdef CONFIG_BCMA_DRIVER_MIPS
396 @@ -118,8 +310,7 @@ void bcma_chipco_serial_init(struct bcma
397 struct bcma_serial_port *ports = cc->serial_ports;
398
399 if (ccrev >= 11 && ccrev != 15) {
400 - /* Fixed ALP clock */
401 - baud_base = bcma_pmu_alp_clock(cc);
402 + baud_base = bcma_chipco_get_alp_clock(cc);
403 if (ccrev >= 21) {
404 /* Turn off UART clock before switching clocksource. */
405 bcma_cc_write32(cc, BCMA_CC_CORECTL,
406 --- a/drivers/bcma/driver_chipcommon_nflash.c
407 +++ b/drivers/bcma/driver_chipcommon_nflash.c
408 @@ -5,15 +5,40 @@
409 * Licensed under the GNU/GPL. See COPYING for details.
410 */
411
412 +#include <linux/platform_device.h>
413 #include <linux/bcma/bcma.h>
414 -#include <linux/bcma/bcma_driver_chipcommon.h>
415 -#include <linux/delay.h>
416
417 #include "bcma_private.h"
418
419 +struct platform_device bcma_nflash_dev = {
420 + .name = "bcma_nflash",
421 + .num_resources = 0,
422 +};
423 +
424 /* Initialize NAND flash access */
425 int bcma_nflash_init(struct bcma_drv_cc *cc)
426 {
427 - bcma_err(cc->core->bus, "NAND flash support is broken\n");
428 + struct bcma_bus *bus = cc->core->bus;
429 +
430 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
431 + cc->core->id.rev != 0x38) {
432 + bcma_err(bus, "NAND flash on unsupported board!\n");
433 + return -ENOTSUPP;
434 + }
435 +
436 + if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) {
437 + bcma_err(bus, "NAND flash not present according to ChipCommon\n");
438 + return -ENODEV;
439 + }
440 +
441 + cc->nflash.present = true;
442 + if (cc->core->id.rev == 38 &&
443 + (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
444 + cc->nflash.boot = true;
445 +
446 + /* Prepare platform device, but don't register it yet. It's too early,
447 + * malloc (required by device_private_init) is not available yet. */
448 + bcma_nflash_dev.dev.platform_data = &cc->nflash;
449 +
450 return 0;
451 }
452 --- a/drivers/bcma/driver_chipcommon_pmu.c
453 +++ b/drivers/bcma/driver_chipcommon_pmu.c
454 @@ -13,12 +13,13 @@
455 #include <linux/export.h>
456 #include <linux/bcma/bcma.h>
457
458 -static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
459 +u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
460 {
461 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
462 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
463 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
464 }
465 +EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
466
467 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
468 {
469 @@ -76,7 +77,10 @@ static void bcma_pmu_resources_init(stru
470 if (max_msk)
471 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
472
473 - /* Add some delay; allow resources to come up and settle. */
474 + /*
475 + * Add some delay; allow resources to come up and settle.
476 + * Delay is required for SoC (early init).
477 + */
478 mdelay(2);
479 }
480
481 @@ -101,7 +105,7 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
482 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
483 }
484
485 -void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
486 +static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
487 {
488 struct bcma_bus *bus = cc->core->bus;
489
490 @@ -141,7 +145,7 @@ void bcma_pmu_workarounds(struct bcma_dr
491 }
492 }
493
494 -void bcma_pmu_init(struct bcma_drv_cc *cc)
495 +void bcma_pmu_early_init(struct bcma_drv_cc *cc)
496 {
497 u32 pmucap;
498
499 @@ -150,7 +154,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
500
501 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
502 cc->pmu.rev, pmucap);
503 +}
504
505 +void bcma_pmu_init(struct bcma_drv_cc *cc)
506 +{
507 if (cc->pmu.rev == 1)
508 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
509 ~BCMA_CC_PMU_CTL_NOILPONW);
510 @@ -162,24 +169,40 @@ void bcma_pmu_init(struct bcma_drv_cc *c
511 bcma_pmu_workarounds(cc);
512 }
513
514 -u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
515 +u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
516 {
517 struct bcma_bus *bus = cc->core->bus;
518
519 switch (bus->chipinfo.id) {
520 + case BCMA_CHIP_ID_BCM4313:
521 + case BCMA_CHIP_ID_BCM43224:
522 + case BCMA_CHIP_ID_BCM43225:
523 + case BCMA_CHIP_ID_BCM43227:
524 + case BCMA_CHIP_ID_BCM43228:
525 + case BCMA_CHIP_ID_BCM4331:
526 + case BCMA_CHIP_ID_BCM43421:
527 + case BCMA_CHIP_ID_BCM43428:
528 + case BCMA_CHIP_ID_BCM43431:
529 case BCMA_CHIP_ID_BCM4716:
530 - case BCMA_CHIP_ID_BCM4748:
531 case BCMA_CHIP_ID_BCM47162:
532 - case BCMA_CHIP_ID_BCM4313:
533 - case BCMA_CHIP_ID_BCM5357:
534 + case BCMA_CHIP_ID_BCM4748:
535 case BCMA_CHIP_ID_BCM4749:
536 + case BCMA_CHIP_ID_BCM5357:
537 case BCMA_CHIP_ID_BCM53572:
538 + case BCMA_CHIP_ID_BCM6362:
539 /* always 20Mhz */
540 return 20000 * 1000;
541 - case BCMA_CHIP_ID_BCM5356:
542 case BCMA_CHIP_ID_BCM4706:
543 + case BCMA_CHIP_ID_BCM5356:
544 /* always 25Mhz */
545 return 25000 * 1000;
546 + case BCMA_CHIP_ID_BCM43460:
547 + case BCMA_CHIP_ID_BCM4352:
548 + case BCMA_CHIP_ID_BCM4360:
549 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
550 + return 40000 * 1000;
551 + else
552 + return 20000 * 1000;
553 default:
554 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
555 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
556 @@ -190,7 +213,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
557 /* Find the output of the "m" pll divider given pll controls that start with
558 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
559 */
560 -static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
561 +static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
562 {
563 u32 tmp, div, ndiv, p1, p2, fc;
564 struct bcma_bus *bus = cc->core->bus;
565 @@ -219,14 +242,14 @@ static u32 bcma_pmu_clock(struct bcma_dr
566 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
567
568 /* Do calculation in Mhz */
569 - fc = bcma_pmu_alp_clock(cc) / 1000000;
570 + fc = bcma_pmu_get_alp_clock(cc) / 1000000;
571 fc = (p1 * ndiv * fc) / p2;
572
573 /* Return clock in Hertz */
574 return (fc / div) * 1000000;
575 }
576
577 -static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
578 +static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
579 {
580 u32 tmp, ndiv, p1div, p2div;
581 u32 clock;
582 @@ -257,7 +280,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
583 }
584
585 /* query bus clock frequency for PMU-enabled chipcommon */
586 -u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
587 +static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
588 {
589 struct bcma_bus *bus = cc->core->bus;
590
591 @@ -265,40 +288,42 @@ u32 bcma_pmu_get_clockcontrol(struct bcm
592 case BCMA_CHIP_ID_BCM4716:
593 case BCMA_CHIP_ID_BCM4748:
594 case BCMA_CHIP_ID_BCM47162:
595 - return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
596 - BCMA_CC_PMU5_MAINPLL_SSB);
597 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
598 + BCMA_CC_PMU5_MAINPLL_SSB);
599 case BCMA_CHIP_ID_BCM5356:
600 - return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
601 - BCMA_CC_PMU5_MAINPLL_SSB);
602 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
603 + BCMA_CC_PMU5_MAINPLL_SSB);
604 case BCMA_CHIP_ID_BCM5357:
605 case BCMA_CHIP_ID_BCM4749:
606 - return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
607 - BCMA_CC_PMU5_MAINPLL_SSB);
608 + return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
609 + BCMA_CC_PMU5_MAINPLL_SSB);
610 case BCMA_CHIP_ID_BCM4706:
611 - return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
612 - BCMA_CC_PMU5_MAINPLL_SSB);
613 + return bcma_pmu_pll_clock_bcm4706(cc,
614 + BCMA_CC_PMU4706_MAINPLL_PLL0,
615 + BCMA_CC_PMU5_MAINPLL_SSB);
616 case BCMA_CHIP_ID_BCM53572:
617 return 75000000;
618 default:
619 - bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
620 + bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
621 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
622 }
623 return BCMA_CC_PMU_HT_CLOCK;
624 }
625
626 /* query cpu clock frequency for PMU-enabled chipcommon */
627 -u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
628 +u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
629 {
630 struct bcma_bus *bus = cc->core->bus;
631
632 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
633 return 300000000;
634
635 + /* New PMUs can have different clock for bus and CPU */
636 if (cc->pmu.rev >= 5) {
637 u32 pll;
638 switch (bus->chipinfo.id) {
639 case BCMA_CHIP_ID_BCM4706:
640 - return bcma_pmu_clock_bcm4706(cc,
641 + return bcma_pmu_pll_clock_bcm4706(cc,
642 BCMA_CC_PMU4706_MAINPLL_PLL0,
643 BCMA_CC_PMU5_MAINPLL_CPU);
644 case BCMA_CHIP_ID_BCM5356:
645 @@ -313,10 +338,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
646 break;
647 }
648
649 - return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
650 + return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
651 }
652
653 - return bcma_pmu_get_clockcontrol(cc);
654 + /* On old PMUs CPU has the same clock as the bus */
655 + return bcma_pmu_get_bus_clock(cc);
656 }
657
658 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
659 @@ -362,7 +388,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
660 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
661 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
662
663 - tmp = 1 << 10;
664 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
665 break;
666
667 case BCMA_CHIP_ID_BCM4331:
668 @@ -383,7 +409,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
669 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
670 0x03000a08);
671 }
672 - tmp = 1 << 10;
673 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
674 break;
675
676 case BCMA_CHIP_ID_BCM43224:
677 @@ -416,7 +442,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
678 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
679 0x88888815);
680 }
681 - tmp = 1 << 10;
682 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
683 break;
684
685 case BCMA_CHIP_ID_BCM4716:
686 @@ -450,7 +476,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
687 0x88888815);
688 }
689
690 - tmp = 3 << 9;
691 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
692 break;
693
694 case BCMA_CHIP_ID_BCM43227:
695 @@ -486,7 +512,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
696 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
697 0x88888815);
698 }
699 - tmp = 1 << 10;
700 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
701 break;
702 default:
703 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
704 --- a/drivers/bcma/driver_chipcommon_sflash.c
705 +++ b/drivers/bcma/driver_chipcommon_sflash.c
706 @@ -5,15 +5,161 @@
707 * Licensed under the GNU/GPL. See COPYING for details.
708 */
709
710 +#include <linux/platform_device.h>
711 #include <linux/bcma/bcma.h>
712 -#include <linux/bcma/bcma_driver_chipcommon.h>
713 -#include <linux/delay.h>
714
715 #include "bcma_private.h"
716
717 +static struct resource bcma_sflash_resource = {
718 + .name = "bcma_sflash",
719 + .start = BCMA_SOC_FLASH2,
720 + .end = 0,
721 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
722 +};
723 +
724 +struct platform_device bcma_sflash_dev = {
725 + .name = "bcma_sflash",
726 + .resource = &bcma_sflash_resource,
727 + .num_resources = 1,
728 +};
729 +
730 +struct bcma_sflash_tbl_e {
731 + char *name;
732 + u32 id;
733 + u32 blocksize;
734 + u16 numblocks;
735 +};
736 +
737 +static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
738 + { "M25P20", 0x11, 0x10000, 4, },
739 + { "M25P40", 0x12, 0x10000, 8, },
740 +
741 + { "M25P16", 0x14, 0x10000, 32, },
742 + { "M25P32", 0x15, 0x10000, 64, },
743 + { "M25P64", 0x16, 0x10000, 128, },
744 + { "M25FL128", 0x17, 0x10000, 256, },
745 + { 0 },
746 +};
747 +
748 +static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
749 + { "SST25WF512", 1, 0x1000, 16, },
750 + { "SST25VF512", 0x48, 0x1000, 16, },
751 + { "SST25WF010", 2, 0x1000, 32, },
752 + { "SST25VF010", 0x49, 0x1000, 32, },
753 + { "SST25WF020", 3, 0x1000, 64, },
754 + { "SST25VF020", 0x43, 0x1000, 64, },
755 + { "SST25WF040", 4, 0x1000, 128, },
756 + { "SST25VF040", 0x44, 0x1000, 128, },
757 + { "SST25VF040B", 0x8d, 0x1000, 128, },
758 + { "SST25WF080", 5, 0x1000, 256, },
759 + { "SST25VF080B", 0x8e, 0x1000, 256, },
760 + { "SST25VF016", 0x41, 0x1000, 512, },
761 + { "SST25VF032", 0x4a, 0x1000, 1024, },
762 + { "SST25VF064", 0x4b, 0x1000, 2048, },
763 + { 0 },
764 +};
765 +
766 +static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
767 + { "AT45DB011", 0xc, 256, 512, },
768 + { "AT45DB021", 0x14, 256, 1024, },
769 + { "AT45DB041", 0x1c, 256, 2048, },
770 + { "AT45DB081", 0x24, 256, 4096, },
771 + { "AT45DB161", 0x2c, 512, 4096, },
772 + { "AT45DB321", 0x34, 512, 8192, },
773 + { "AT45DB642", 0x3c, 1024, 8192, },
774 + { 0 },
775 +};
776 +
777 +static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
778 +{
779 + int i;
780 + bcma_cc_write32(cc, BCMA_CC_FLASHCTL,
781 + BCMA_CC_FLASHCTL_START | opcode);
782 + for (i = 0; i < 1000; i++) {
783 + if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) &
784 + BCMA_CC_FLASHCTL_BUSY))
785 + return;
786 + cpu_relax();
787 + }
788 + bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
789 +}
790 +
791 /* Initialize serial flash access */
792 int bcma_sflash_init(struct bcma_drv_cc *cc)
793 {
794 - bcma_err(cc->core->bus, "Serial flash support is broken\n");
795 + struct bcma_bus *bus = cc->core->bus;
796 + struct bcma_sflash *sflash = &cc->sflash;
797 + struct bcma_sflash_tbl_e *e;
798 + u32 id, id2;
799 +
800 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
801 + case BCMA_CC_FLASHT_STSER:
802 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP);
803 +
804 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0);
805 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
806 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
807 +
808 + bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1);
809 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
810 + id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
811 +
812 + switch (id) {
813 + case 0xbf:
814 + for (e = bcma_sflash_sst_tbl; e->name; e++) {
815 + if (e->id == id2)
816 + break;
817 + }
818 + break;
819 + case 0x13:
820 + return -ENOTSUPP;
821 + default:
822 + for (e = bcma_sflash_st_tbl; e->name; e++) {
823 + if (e->id == id)
824 + break;
825 + }
826 + break;
827 + }
828 + if (!e->name) {
829 + bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2);
830 + return -ENOTSUPP;
831 + }
832 +
833 + break;
834 + case BCMA_CC_FLASHT_ATSER:
835 + bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
836 + id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c;
837 +
838 + for (e = bcma_sflash_at_tbl; e->name; e++) {
839 + if (e->id == id)
840 + break;
841 + }
842 + if (!e->name) {
843 + bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id);
844 + return -ENOTSUPP;
845 + }
846 +
847 + break;
848 + default:
849 + bcma_err(bus, "Unsupported flash type\n");
850 + return -ENOTSUPP;
851 + }
852 +
853 + sflash->window = BCMA_SOC_FLASH2;
854 + sflash->blocksize = e->blocksize;
855 + sflash->numblocks = e->numblocks;
856 + sflash->size = sflash->blocksize * sflash->numblocks;
857 + sflash->present = true;
858 +
859 + bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
860 + e->name, sflash->size / 1024, sflash->blocksize,
861 + sflash->numblocks);
862 +
863 + /* Prepare platform device, but don't register it yet. It's too early,
864 + * malloc (required by device_private_init) is not available yet. */
865 + bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start +
866 + sflash->size;
867 + bcma_sflash_dev.dev.platform_data = sflash;
868 +
869 return 0;
870 }
871 --- /dev/null
872 +++ b/drivers/bcma/driver_gpio.c
873 @@ -0,0 +1,98 @@
874 +/*
875 + * Broadcom specific AMBA
876 + * GPIO driver
877 + *
878 + * Copyright 2011, Broadcom Corporation
879 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
880 + *
881 + * Licensed under the GNU/GPL. See COPYING for details.
882 + */
883 +
884 +#include <linux/gpio.h>
885 +#include <linux/export.h>
886 +#include <linux/bcma/bcma.h>
887 +
888 +#include "bcma_private.h"
889 +
890 +static inline struct bcma_drv_cc *bcma_gpio_get_cc(struct gpio_chip *chip)
891 +{
892 + return container_of(chip, struct bcma_drv_cc, gpio);
893 +}
894 +
895 +static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
896 +{
897 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
898 +
899 + return !!bcma_chipco_gpio_in(cc, 1 << gpio);
900 +}
901 +
902 +static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
903 + int value)
904 +{
905 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
906 +
907 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
908 +}
909 +
910 +static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
911 +{
912 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
913 +
914 + bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
915 + return 0;
916 +}
917 +
918 +static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
919 + int value)
920 +{
921 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
922 +
923 + bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
924 + bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
925 + return 0;
926 +}
927 +
928 +static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
929 +{
930 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
931 +
932 + bcma_chipco_gpio_control(cc, 1 << gpio, 0);
933 + /* clear pulldown */
934 + bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
935 + /* Set pullup */
936 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
937 +
938 + return 0;
939 +}
940 +
941 +static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
942 +{
943 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
944 +
945 + /* clear pullup */
946 + bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
947 +}
948 +
949 +int bcma_gpio_init(struct bcma_drv_cc *cc)
950 +{
951 + struct gpio_chip *chip = &cc->gpio;
952 +
953 + chip->label = "bcma_gpio";
954 + chip->owner = THIS_MODULE;
955 + chip->request = bcma_gpio_request;
956 + chip->free = bcma_gpio_free;
957 + chip->get = bcma_gpio_get_value;
958 + chip->set = bcma_gpio_set_value;
959 + chip->direction_input = bcma_gpio_direction_input;
960 + chip->direction_output = bcma_gpio_direction_output;
961 + chip->ngpio = 16;
962 + /* There is just one SoC in one device and its GPIO addresses should be
963 + * deterministic to address them more easily. The other buses could get
964 + * a random base number. */
965 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
966 + chip->base = 0;
967 + else
968 + chip->base = -1;
969 +
970 + return gpiochip_add(chip);
971 +}
972 --- a/drivers/bcma/driver_mips.c
973 +++ b/drivers/bcma/driver_mips.c
974 @@ -74,11 +74,16 @@ static u32 bcma_core_mips_irqflag(struct
975 return dev->core_index;
976 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
977
978 - return flag & 0x1F;
979 + if (flag)
980 + return flag & 0x1F;
981 + else
982 + return 0x3f;
983 }
984
985 /* Get the MIPS IRQ assignment for a specified device.
986 * If unassigned, 0 is returned.
987 + * If disabled, 5 is returned.
988 + * If not supported, 6 is returned.
989 */
990 unsigned int bcma_core_mips_irq(struct bcma_device *dev)
991 {
992 @@ -87,13 +92,15 @@ unsigned int bcma_core_mips_irq(struct b
993 unsigned int irq;
994
995 irqflag = bcma_core_mips_irqflag(dev);
996 + if (irqflag == 0x3f)
997 + return 6;
998
999 - for (irq = 1; irq <= 4; irq++)
1000 + for (irq = 0; irq <= 4; irq++)
1001 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
1002 (1 << irqflag))
1003 return irq;
1004
1005 - return 0;
1006 + return 5;
1007 }
1008 EXPORT_SYMBOL(bcma_core_mips_irq);
1009
1010 @@ -114,8 +121,8 @@ static void bcma_core_mips_set_irq(struc
1011 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
1012 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
1013 ~(1 << irqflag));
1014 - else
1015 - bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
1016 + else if (oldirq != 5)
1017 + bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
1018
1019 /* assign the new one */
1020 if (irq == 0) {
1021 @@ -123,9 +130,9 @@ static void bcma_core_mips_set_irq(struc
1022 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
1023 (1 << irqflag));
1024 } else {
1025 - u32 oldirqflag = bcma_read32(mdev,
1026 - BCMA_MIPS_MIPS74K_INTMASK(irq));
1027 - if (oldirqflag) {
1028 + u32 irqinitmask = bcma_read32(mdev,
1029 + BCMA_MIPS_MIPS74K_INTMASK(irq));
1030 + if (irqinitmask) {
1031 struct bcma_device *core;
1032
1033 /* backplane irq line is in use, find out who uses
1034 @@ -133,7 +140,7 @@ static void bcma_core_mips_set_irq(struc
1035 */
1036 list_for_each_entry(core, &bus->cores, list) {
1037 if ((1 << bcma_core_mips_irqflag(core)) ==
1038 - oldirqflag) {
1039 + irqinitmask) {
1040 bcma_core_mips_set_irq(core, 0);
1041 break;
1042 }
1043 @@ -143,15 +150,31 @@ static void bcma_core_mips_set_irq(struc
1044 1 << irqflag);
1045 }
1046
1047 - bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1048 - dev->id.id, oldirq + 2, irq + 2);
1049 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
1050 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
1051 +}
1052 +
1053 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
1054 + u16 coreid, u8 unit)
1055 +{
1056 + struct bcma_device *core;
1057 +
1058 + core = bcma_find_core_unit(bus, coreid, unit);
1059 + if (!core) {
1060 + bcma_warn(bus,
1061 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
1062 + coreid, unit);
1063 + return;
1064 + }
1065 +
1066 + bcma_core_mips_set_irq(core, irq);
1067 }
1068
1069 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
1070 {
1071 int i;
1072 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1073 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1074 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
1075 for (i = 0; i <= 6; i++)
1076 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
1077 printk("\n");
1078 @@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
1079 struct bcma_bus *bus = mcore->core->bus;
1080
1081 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
1082 - return bcma_pmu_get_clockcpu(&bus->drv_cc);
1083 + return bcma_pmu_get_cpu_clock(&bus->drv_cc);
1084
1085 bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
1086 return 0;
1087 @@ -181,85 +204,109 @@ EXPORT_SYMBOL(bcma_cpu_clock);
1088 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
1089 {
1090 struct bcma_bus *bus = mcore->core->bus;
1091 + struct bcma_drv_cc *cc = &bus->drv_cc;
1092
1093 - switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
1094 + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
1095 case BCMA_CC_FLASHT_STSER:
1096 case BCMA_CC_FLASHT_ATSER:
1097 bcma_debug(bus, "Found serial flash\n");
1098 - bcma_sflash_init(&bus->drv_cc);
1099 + bcma_sflash_init(cc);
1100 break;
1101 case BCMA_CC_FLASHT_PARA:
1102 bcma_debug(bus, "Found parallel flash\n");
1103 - bus->drv_cc.pflash.window = 0x1c000000;
1104 - bus->drv_cc.pflash.window_size = 0x02000000;
1105 + cc->pflash.present = true;
1106 + cc->pflash.window = BCMA_SOC_FLASH2;
1107 + cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
1108
1109 - if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
1110 + if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
1111 BCMA_CC_FLASH_CFG_DS) == 0)
1112 - bus->drv_cc.pflash.buswidth = 1;
1113 + cc->pflash.buswidth = 1;
1114 else
1115 - bus->drv_cc.pflash.buswidth = 2;
1116 + cc->pflash.buswidth = 2;
1117 break;
1118 default:
1119 bcma_err(bus, "Flash type not supported\n");
1120 }
1121
1122 - if (bus->drv_cc.core->id.rev == 38 ||
1123 + if (cc->core->id.rev == 38 ||
1124 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
1125 - if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
1126 + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
1127 bcma_debug(bus, "Found NAND flash\n");
1128 - bcma_nflash_init(&bus->drv_cc);
1129 + bcma_nflash_init(cc);
1130 }
1131 }
1132 }
1133
1134 +void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
1135 +{
1136 + struct bcma_bus *bus = mcore->core->bus;
1137 +
1138 + if (mcore->early_setup_done)
1139 + return;
1140 +
1141 + bcma_chipco_serial_init(&bus->drv_cc);
1142 + bcma_core_mips_flash_detect(mcore);
1143 +
1144 + mcore->early_setup_done = true;
1145 +}
1146 +
1147 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
1148 {
1149 struct bcma_bus *bus;
1150 struct bcma_device *core;
1151 bus = mcore->core->bus;
1152
1153 - bcma_info(bus, "Initializing MIPS core...\n");
1154 + if (mcore->setup_done)
1155 + return;
1156
1157 - if (!mcore->setup_done)
1158 - mcore->assigned_irqs = 1;
1159 + bcma_debug(bus, "Initializing MIPS core...\n");
1160
1161 - /* Assign IRQs to all cores on the bus */
1162 - list_for_each_entry(core, &bus->cores, list) {
1163 - int mips_irq;
1164 - if (core->irq)
1165 - continue;
1166 -
1167 - mips_irq = bcma_core_mips_irq(core);
1168 - if (mips_irq > 4)
1169 - core->irq = 0;
1170 - else
1171 - core->irq = mips_irq + 2;
1172 - if (core->irq > 5)
1173 - continue;
1174 - switch (core->id.id) {
1175 - case BCMA_CORE_PCI:
1176 - case BCMA_CORE_PCIE:
1177 - case BCMA_CORE_ETHERNET:
1178 - case BCMA_CORE_ETHERNET_GBIT:
1179 - case BCMA_CORE_MAC_GBIT:
1180 - case BCMA_CORE_80211:
1181 - case BCMA_CORE_USB20_HOST:
1182 - /* These devices get their own IRQ line if available,
1183 - * the rest goes on IRQ0
1184 - */
1185 - if (mcore->assigned_irqs <= 4)
1186 - bcma_core_mips_set_irq(core,
1187 - mcore->assigned_irqs++);
1188 - break;
1189 + bcma_core_mips_early_init(mcore);
1190 +
1191 + switch (bus->chipinfo.id) {
1192 + case BCMA_CHIP_ID_BCM4716:
1193 + case BCMA_CHIP_ID_BCM4748:
1194 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1195 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1196 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1197 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
1198 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1199 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1200 + break;
1201 + case BCMA_CHIP_ID_BCM5356:
1202 + case BCMA_CHIP_ID_BCM47162:
1203 + case BCMA_CHIP_ID_BCM53572:
1204 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1205 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1206 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1207 + break;
1208 + case BCMA_CHIP_ID_BCM5357:
1209 + case BCMA_CHIP_ID_BCM4749:
1210 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
1211 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
1212 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
1213 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
1214 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
1215 + break;
1216 + case BCMA_CHIP_ID_BCM4706:
1217 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
1218 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
1219 + 0);
1220 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
1221 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
1222 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
1223 + 0);
1224 + break;
1225 + default:
1226 + list_for_each_entry(core, &bus->cores, list) {
1227 + core->irq = bcma_core_mips_irq(core) + 2;
1228 }
1229 + bcma_err(bus,
1230 + "Unknown device (0x%x) found, can not configure IRQs\n",
1231 + bus->chipinfo.id);
1232 }
1233 - bcma_info(bus, "IRQ reconfiguration done\n");
1234 + bcma_debug(bus, "IRQ reconfiguration done\n");
1235 bcma_core_mips_dump_irq(bus);
1236
1237 - if (mcore->setup_done)
1238 - return;
1239 -
1240 - bcma_chipco_serial_init(&bus->drv_cc);
1241 - bcma_core_mips_flash_detect(mcore);
1242 mcore->setup_done = true;
1243 }
1244 --- a/drivers/bcma/driver_pci.c
1245 +++ b/drivers/bcma/driver_pci.c
1246 @@ -51,7 +51,7 @@ static void bcma_pcie_mdio_set_phy(struc
1247 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1248 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1249 break;
1250 - msleep(1);
1251 + usleep_range(1000, 2000);
1252 }
1253 }
1254
1255 @@ -92,7 +92,7 @@ static u16 bcma_pcie_mdio_read(struct bc
1256 ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
1257 break;
1258 }
1259 - msleep(1);
1260 + usleep_range(1000, 2000);
1261 }
1262 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1263 return ret;
1264 @@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct
1265 v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
1266 if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
1267 break;
1268 - msleep(1);
1269 + usleep_range(1000, 2000);
1270 }
1271 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
1272 }
1273 --- a/drivers/bcma/driver_pci_host.c
1274 +++ b/drivers/bcma/driver_pci_host.c
1275 @@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
1276 chipid_top != 0x5300)
1277 return false;
1278
1279 - if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1280 - bcma_info(bus, "This PCI core is disabled and not working\n");
1281 - return false;
1282 - }
1283 -
1284 bcma_core_enable(pc->core, 0);
1285
1286 return !mips_busprobe32(tmp, pc->core->io_addr);
1287 @@ -396,6 +391,11 @@ void __devinit bcma_core_pci_hostmode_in
1288
1289 bcma_info(bus, "PCIEcore in host mode found\n");
1290
1291 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1292 + bcma_info(bus, "This PCIE core is disabled and not working\n");
1293 + return;
1294 + }
1295 +
1296 pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
1297 if (!pc_host) {
1298 bcma_err(bus, "can not allocate memory");
1299 @@ -425,9 +425,9 @@ void __devinit bcma_core_pci_hostmode_in
1300 pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
1301
1302 /* Reset RC */
1303 - udelay(3000);
1304 + usleep_range(3000, 5000);
1305 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
1306 - udelay(1000);
1307 + usleep_range(1000, 2000);
1308 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
1309 BCMA_CORE_PCI_CTL_RST_OE);
1310
1311 @@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_in
1312 pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1313 pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1314 BCMA_SOC_PCI_MEM_SZ - 1;
1315 + pc_host->io_resource.start = 0x100;
1316 + pc_host->io_resource.end = 0x47F;
1317 pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
1318 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1319 tmp | BCMA_SOC_PCI_MEM);
1320 @@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_in
1321 pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
1322 pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
1323 BCMA_SOC_PCI_MEM_SZ - 1;
1324 + pc_host->io_resource.start = 0x480;
1325 + pc_host->io_resource.end = 0x7FF;
1326 pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
1327 pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
1328 pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1329 @@ -481,7 +485,7 @@ void __devinit bcma_core_pci_hostmode_in
1330 * before issuing configuration requests to PCI Express
1331 * devices.
1332 */
1333 - udelay(100000);
1334 + msleep(100);
1335
1336 bcma_core_pci_enable_crs(pc);
1337
1338 @@ -501,7 +505,7 @@ void __devinit bcma_core_pci_hostmode_in
1339 set_io_port_base(pc_host->pci_controller.io_map_base);
1340 /* Give some time to the PCI controller to configure itself with the new
1341 * values. Not waiting at this point causes crashes of the machine. */
1342 - mdelay(10);
1343 + usleep_range(10000, 15000);
1344 register_pci_controller(&pc_host->pci_controller);
1345 return;
1346 }
1347 @@ -534,7 +538,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_
1348 static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
1349 {
1350 struct resource *res;
1351 - int pos;
1352 + int pos, err;
1353
1354 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1355 /* This is not a device on the PCI-core bridge. */
1356 @@ -547,8 +551,12 @@ static void bcma_core_pci_fixup_addresse
1357
1358 for (pos = 0; pos < 6; pos++) {
1359 res = &dev->resource[pos];
1360 - if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
1361 - pci_assign_resource(dev, pos);
1362 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
1363 + err = pci_assign_resource(dev, pos);
1364 + if (err)
1365 + pr_err("PCI: Problem fixing up the addresses on %s\n",
1366 + pci_name(dev));
1367 + }
1368 }
1369 }
1370 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
1371 --- a/drivers/bcma/host_pci.c
1372 +++ b/drivers/bcma/host_pci.c
1373 @@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
1374 }
1375
1376 #ifdef CONFIG_BCMA_BLOCKIO
1377 -void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
1378 - size_t count, u16 offset, u8 reg_width)
1379 +static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
1380 + size_t count, u16 offset, u8 reg_width)
1381 {
1382 void __iomem *addr = core->bus->mmio + offset;
1383 if (core->bus->mapped_core != core)
1384 @@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm
1385 }
1386 }
1387
1388 -void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
1389 - size_t count, u16 offset, u8 reg_width)
1390 +static void bcma_host_pci_block_write(struct bcma_device *core,
1391 + const void *buffer, size_t count,
1392 + u16 offset, u8 reg_width)
1393 {
1394 void __iomem *addr = core->bus->mmio + offset;
1395 if (core->bus->mapped_core != core)
1396 @@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc
1397 iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
1398 }
1399
1400 -const struct bcma_host_ops bcma_host_pci_ops = {
1401 +static const struct bcma_host_ops bcma_host_pci_ops = {
1402 .read8 = bcma_host_pci_read8,
1403 .read16 = bcma_host_pci_read16,
1404 .read32 = bcma_host_pci_read32,
1405 @@ -237,7 +238,7 @@ static void __devexit bcma_host_pci_remo
1406 pci_set_drvdata(dev, NULL);
1407 }
1408
1409 -#ifdef CONFIG_PM
1410 +#ifdef CONFIG_PM_SLEEP
1411 static int bcma_host_pci_suspend(struct device *dev)
1412 {
1413 struct pci_dev *pdev = to_pci_dev(dev);
1414 @@ -260,11 +261,11 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
1415 bcma_host_pci_resume);
1416 #define BCMA_PM_OPS (&bcma_pm_ops)
1417
1418 -#else /* CONFIG_PM */
1419 +#else /* CONFIG_PM_SLEEP */
1420
1421 #define BCMA_PM_OPS NULL
1422
1423 -#endif /* CONFIG_PM */
1424 +#endif /* CONFIG_PM_SLEEP */
1425
1426 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
1427 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
1428 @@ -272,6 +273,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
1429 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
1430 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
1431 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
1432 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
1433 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
1434 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
1435 { 0, },
1436 --- a/drivers/bcma/host_soc.c
1437 +++ b/drivers/bcma/host_soc.c
1438 @@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc
1439 writel(value, core->io_wrap + offset);
1440 }
1441
1442 -const struct bcma_host_ops bcma_host_soc_ops = {
1443 +static const struct bcma_host_ops bcma_host_soc_ops = {
1444 .read8 = bcma_host_soc_read8,
1445 .read16 = bcma_host_soc_read16,
1446 .read32 = bcma_host_soc_read32,
1447 --- a/drivers/bcma/main.c
1448 +++ b/drivers/bcma/main.c
1449 @@ -7,6 +7,7 @@
1450
1451 #include "bcma_private.h"
1452 #include <linux/module.h>
1453 +#include <linux/platform_device.h>
1454 #include <linux/bcma/bcma.h>
1455 #include <linux/slab.h>
1456
1457 @@ -80,6 +81,18 @@ struct bcma_device *bcma_find_core(struc
1458 }
1459 EXPORT_SYMBOL_GPL(bcma_find_core);
1460
1461 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1462 + u8 unit)
1463 +{
1464 + struct bcma_device *core;
1465 +
1466 + list_for_each_entry(core, &bus->cores, list) {
1467 + if (core->id.id == coreid && core->core_unit == unit)
1468 + return core;
1469 + }
1470 + return NULL;
1471 +}
1472 +
1473 static void bcma_release_core_dev(struct device *dev)
1474 {
1475 struct bcma_device *core = container_of(dev, struct bcma_device, dev);
1476 @@ -136,6 +149,33 @@ static int bcma_register_cores(struct bc
1477 dev_id++;
1478 }
1479
1480 +#ifdef CONFIG_BCMA_SFLASH
1481 + if (bus->drv_cc.sflash.present) {
1482 + err = platform_device_register(&bcma_sflash_dev);
1483 + if (err)
1484 + bcma_err(bus, "Error registering serial flash\n");
1485 + }
1486 +#endif
1487 +
1488 +#ifdef CONFIG_BCMA_NFLASH
1489 + if (bus->drv_cc.nflash.present) {
1490 + err = platform_device_register(&bcma_nflash_dev);
1491 + if (err)
1492 + bcma_err(bus, "Error registering NAND flash\n");
1493 + }
1494 +#endif
1495 + err = bcma_gpio_init(&bus->drv_cc);
1496 + if (err == -ENOTSUPP)
1497 + bcma_debug(bus, "GPIO driver not activated\n");
1498 + else if (err)
1499 + bcma_err(bus, "Error registering GPIO driver: %i\n", err);
1500 +
1501 + if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
1502 + err = bcma_chipco_watchdog_register(&bus->drv_cc);
1503 + if (err)
1504 + bcma_err(bus, "Error registering watchdog driver\n");
1505 + }
1506 +
1507 return 0;
1508 }
1509
1510 @@ -148,6 +188,8 @@ static void bcma_unregister_cores(struct
1511 if (core->dev_registered)
1512 device_unregister(&core->dev);
1513 }
1514 + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
1515 + platform_device_unregister(bus->drv_cc.watchdog);
1516 }
1517
1518 int __devinit bcma_bus_register(struct bcma_bus *bus)
1519 @@ -166,6 +208,20 @@ int __devinit bcma_bus_register(struct b
1520 return -1;
1521 }
1522
1523 + /* Early init CC core */
1524 + core = bcma_find_core(bus, bcma_cc_core_id(bus));
1525 + if (core) {
1526 + bus->drv_cc.core = core;
1527 + bcma_core_chipcommon_early_init(&bus->drv_cc);
1528 + }
1529 +
1530 + /* Try to get SPROM */
1531 + err = bcma_sprom_get(bus);
1532 + if (err == -ENOENT) {
1533 + bcma_err(bus, "No SPROM available\n");
1534 + } else if (err)
1535 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
1536 +
1537 /* Init CC core */
1538 core = bcma_find_core(bus, bcma_cc_core_id(bus));
1539 if (core) {
1540 @@ -181,10 +237,17 @@ int __devinit bcma_bus_register(struct b
1541 }
1542
1543 /* Init PCIE core */
1544 - core = bcma_find_core(bus, BCMA_CORE_PCIE);
1545 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
1546 + if (core) {
1547 + bus->drv_pci[0].core = core;
1548 + bcma_core_pci_init(&bus->drv_pci[0]);
1549 + }
1550 +
1551 + /* Init PCIE core */
1552 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
1553 if (core) {
1554 - bus->drv_pci.core = core;
1555 - bcma_core_pci_init(&bus->drv_pci);
1556 + bus->drv_pci[1].core = core;
1557 + bcma_core_pci_init(&bus->drv_pci[1]);
1558 }
1559
1560 /* Init GBIT MAC COMMON core */
1561 @@ -194,13 +257,6 @@ int __devinit bcma_bus_register(struct b
1562 bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
1563 }
1564
1565 - /* Try to get SPROM */
1566 - err = bcma_sprom_get(bus);
1567 - if (err == -ENOENT) {
1568 - bcma_err(bus, "No SPROM available\n");
1569 - } else if (err)
1570 - bcma_err(bus, "Failed to get SPROM: %d\n", err);
1571 -
1572 /* Register found cores */
1573 bcma_register_cores(bus);
1574
1575 @@ -211,7 +267,17 @@ int __devinit bcma_bus_register(struct b
1576
1577 void bcma_bus_unregister(struct bcma_bus *bus)
1578 {
1579 + struct bcma_device *cores[3];
1580 +
1581 + cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1582 + cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
1583 + cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
1584 +
1585 bcma_unregister_cores(bus);
1586 +
1587 + kfree(cores[2]);
1588 + kfree(cores[1]);
1589 + kfree(cores[0]);
1590 }
1591
1592 int __init bcma_bus_early_register(struct bcma_bus *bus,
1593 @@ -248,18 +314,18 @@ int __init bcma_bus_early_register(struc
1594 return -1;
1595 }
1596
1597 - /* Init CC core */
1598 + /* Early init CC core */
1599 core = bcma_find_core(bus, bcma_cc_core_id(bus));
1600 if (core) {
1601 bus->drv_cc.core = core;
1602 - bcma_core_chipcommon_init(&bus->drv_cc);
1603 + bcma_core_chipcommon_early_init(&bus->drv_cc);
1604 }
1605
1606 - /* Init MIPS core */
1607 + /* Early init MIPS core */
1608 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1609 if (core) {
1610 bus->drv_mips.core = core;
1611 - bcma_core_mips_init(&bus->drv_mips);
1612 + bcma_core_mips_early_init(&bus->drv_mips);
1613 }
1614
1615 bcma_info(bus, "Early bus registered\n");
1616 --- a/drivers/bcma/sprom.c
1617 +++ b/drivers/bcma/sprom.c
1618 @@ -507,7 +507,9 @@ static bool bcma_sprom_onchip_available(
1619 /* for these chips OTP is always available */
1620 present = true;
1621 break;
1622 + case BCMA_CHIP_ID_BCM43227:
1623 case BCMA_CHIP_ID_BCM43228:
1624 + case BCMA_CHIP_ID_BCM43428:
1625 present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
1626 break;
1627 default:
1628 @@ -593,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus)
1629 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
1630
1631 err = bcma_sprom_valid(sprom);
1632 - if (err)
1633 + if (err) {
1634 + bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
1635 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1636 goto out;
1637 + }
1638
1639 bcma_sprom_extract_r8(bus, sprom);
1640
1641 --- a/include/linux/bcma/bcma.h
1642 +++ b/include/linux/bcma/bcma.h
1643 @@ -10,7 +10,7 @@
1644 #include <linux/bcma/bcma_driver_gmac_cmn.h>
1645 #include <linux/ssb/ssb.h> /* SPROM sharing */
1646
1647 -#include "bcma_regs.h"
1648 +#include <linux/bcma/bcma_regs.h>
1649
1650 struct bcma_device;
1651 struct bcma_bus;
1652 @@ -157,6 +157,7 @@ struct bcma_host_ops {
1653
1654 /* Chip IDs of SoCs */
1655 #define BCMA_CHIP_ID_BCM4706 0x5300
1656 +#define BCMA_PKG_ID_BCM4706L 1
1657 #define BCMA_CHIP_ID_BCM4716 0x4716
1658 #define BCMA_PKG_ID_BCM4716 8
1659 #define BCMA_PKG_ID_BCM4717 9
1660 @@ -166,7 +167,11 @@ struct bcma_host_ops {
1661 #define BCMA_CHIP_ID_BCM4749 0x4749
1662 #define BCMA_CHIP_ID_BCM5356 0x5356
1663 #define BCMA_CHIP_ID_BCM5357 0x5357
1664 +#define BCMA_PKG_ID_BCM5358 9
1665 +#define BCMA_PKG_ID_BCM47186 10
1666 +#define BCMA_PKG_ID_BCM5357 11
1667 #define BCMA_CHIP_ID_BCM53572 53572
1668 +#define BCMA_PKG_ID_BCM47188 9
1669
1670 struct bcma_device {
1671 struct bcma_bus *bus;
1672 @@ -251,7 +256,7 @@ struct bcma_bus {
1673 u8 num;
1674
1675 struct bcma_drv_cc drv_cc;
1676 - struct bcma_drv_pci drv_pci;
1677 + struct bcma_drv_pci drv_pci[2];
1678 struct bcma_drv_mips drv_mips;
1679 struct bcma_drv_gmac_cmn drv_gmac_cmn;
1680
1681 @@ -345,6 +350,7 @@ extern void bcma_core_set_clockmode(stru
1682 enum bcma_clkmode clkmode);
1683 extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
1684 bool on);
1685 +extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
1686 #define BCMA_DMA_TRANSLATION_MASK 0xC0000000
1687 #define BCMA_DMA_TRANSLATION_NONE 0x00000000
1688 #define BCMA_DMA_TRANSLATION_DMA32_CMT 0x40000000 /* Client Mode Translation for 32-bit DMA */
1689 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1690 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1691 @@ -1,6 +1,9 @@
1692 #ifndef LINUX_BCMA_DRIVER_CC_H_
1693 #define LINUX_BCMA_DRIVER_CC_H_
1694
1695 +#include <linux/platform_device.h>
1696 +#include <linux/gpio.h>
1697 +
1698 /** ChipCommon core registers. **/
1699 #define BCMA_CC_ID 0x0000
1700 #define BCMA_CC_ID_ID 0x0000FFFF
1701 @@ -100,6 +103,8 @@
1702 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
1703 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
1704 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
1705 +#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
1706 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
1707 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
1708 #define BCMA_CC_JCMD_START 0x80000000
1709 #define BCMA_CC_JCMD_BUSY 0x80000000
1710 @@ -266,6 +271,29 @@
1711 #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
1712 #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
1713 #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
1714 +/* Block 0x140 - 0x190 registers are chipset specific */
1715 +#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
1716 +#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
1717 +#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
1718 +#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
1719 +#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
1720 +#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
1721 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
1722 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
1723 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
1724 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
1725 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
1726 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
1727 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
1728 +#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
1729 +/* NAND flash registers for BCM4706 (corerev = 31) */
1730 +#define BCMA_CC_NFLASH_CTL 0x01A0
1731 +#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
1732 +#define BCMA_CC_NFLASH_CONF 0x01A4
1733 +#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
1734 +#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
1735 +#define BCMA_CC_NFLASH_DATA 0x01B0
1736 +#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
1737 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
1738 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1739 #define BCMA_CC_UART0_DATA 0x0300
1740 @@ -325,6 +353,60 @@
1741 #define BCMA_CC_PLLCTL_ADDR 0x0660
1742 #define BCMA_CC_PLLCTL_DATA 0x0664
1743 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
1744 +/* NAND flash MLC controller registers (corerev >= 38) */
1745 +#define BCMA_CC_NAND_REVISION 0x0C00
1746 +#define BCMA_CC_NAND_CMD_START 0x0C04
1747 +#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
1748 +#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
1749 +#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
1750 +#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
1751 +#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
1752 +#define BCMA_CC_NAND_SPARE_RD0 0x0C20
1753 +#define BCMA_CC_NAND_SPARE_RD4 0x0C24
1754 +#define BCMA_CC_NAND_SPARE_RD8 0x0C28
1755 +#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
1756 +#define BCMA_CC_NAND_SPARE_WR0 0x0C30
1757 +#define BCMA_CC_NAND_SPARE_WR4 0x0C34
1758 +#define BCMA_CC_NAND_SPARE_WR8 0x0C38
1759 +#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
1760 +#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
1761 +#define BCMA_CC_NAND_CONFIG 0x0C48
1762 +#define BCMA_CC_NAND_TIMING_1 0x0C50
1763 +#define BCMA_CC_NAND_TIMING_2 0x0C54
1764 +#define BCMA_CC_NAND_SEMAPHORE 0x0C58
1765 +#define BCMA_CC_NAND_DEVID 0x0C60
1766 +#define BCMA_CC_NAND_DEVID_X 0x0C64
1767 +#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
1768 +#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
1769 +#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
1770 +#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
1771 +#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
1772 +#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
1773 +#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
1774 +#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
1775 +#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
1776 +#define BCMA_CC_NAND_READ_ADDR 0x0C94
1777 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
1778 +#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
1779 +#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
1780 +#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
1781 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
1782 +#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
1783 +#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
1784 +#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
1785 +#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
1786 +#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
1787 +#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
1788 +#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
1789 +#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
1790 +#define BCMA_CC_NAND_SPARE_RD16 0x0D30
1791 +#define BCMA_CC_NAND_SPARE_RD20 0x0D34
1792 +#define BCMA_CC_NAND_SPARE_RD24 0x0D38
1793 +#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
1794 +#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
1795 +#define BCMA_CC_NAND_CACHE_DATA 0x0D44
1796 +#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
1797 +#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
1798
1799 /* Divider allocation in 4716/47162/5356 */
1800 #define BCMA_CC_PMU5_MAINPLL_CPU 1
1801 @@ -415,6 +497,13 @@
1802 /* 4313 Chip specific ChipControl register bits */
1803 #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
1804
1805 +/* BCM5357 ChipControl register bits */
1806 +#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
1807 +#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
1808 +#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
1809 +#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
1810 +#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
1811 +
1812 /* Data for the PMU, if available.
1813 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
1814 */
1815 @@ -425,11 +514,35 @@ struct bcma_chipcommon_pmu {
1816
1817 #ifdef CONFIG_BCMA_DRIVER_MIPS
1818 struct bcma_pflash {
1819 + bool present;
1820 u8 buswidth;
1821 u32 window;
1822 u32 window_size;
1823 };
1824
1825 +#ifdef CONFIG_BCMA_SFLASH
1826 +struct bcma_sflash {
1827 + bool present;
1828 + u32 window;
1829 + u32 blocksize;
1830 + u16 numblocks;
1831 + u32 size;
1832 +
1833 + struct mtd_info *mtd;
1834 +};
1835 +#endif
1836 +
1837 +#ifdef CONFIG_BCMA_NFLASH
1838 +struct mtd_info;
1839 +
1840 +struct bcma_nflash {
1841 + bool present;
1842 + bool boot; /* This is the flash the SoC boots from */
1843 +
1844 + struct mtd_info *mtd;
1845 +};
1846 +#endif
1847 +
1848 struct bcma_serial_port {
1849 void *regs;
1850 unsigned long clockspeed;
1851 @@ -445,15 +558,30 @@ struct bcma_drv_cc {
1852 u32 capabilities;
1853 u32 capabilities_ext;
1854 u8 setup_done:1;
1855 + u8 early_setup_done:1;
1856 /* Fast Powerup Delay constant */
1857 u16 fast_pwrup_delay;
1858 struct bcma_chipcommon_pmu pmu;
1859 #ifdef CONFIG_BCMA_DRIVER_MIPS
1860 struct bcma_pflash pflash;
1861 +#ifdef CONFIG_BCMA_SFLASH
1862 + struct bcma_sflash sflash;
1863 +#endif
1864 +#ifdef CONFIG_BCMA_NFLASH
1865 + struct bcma_nflash nflash;
1866 +#endif
1867
1868 int nr_serial_ports;
1869 struct bcma_serial_port serial_ports[4];
1870 #endif /* CONFIG_BCMA_DRIVER_MIPS */
1871 + u32 ticks_per_ms;
1872 + struct platform_device *watchdog;
1873 +
1874 + /* Lock for GPIO register access. */
1875 + spinlock_t gpio_lock;
1876 +#ifdef CONFIG_BCMA_DRIVER_GPIO
1877 + struct gpio_chip gpio;
1878 +#endif
1879 };
1880
1881 /* Register access */
1882 @@ -470,14 +598,16 @@ struct bcma_drv_cc {
1883 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
1884
1885 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
1886 +extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
1887
1888 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
1889 extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
1890
1891 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
1892
1893 -extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc,
1894 - u32 ticks);
1895 +extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
1896 +
1897 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
1898
1899 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1900
1901 @@ -490,9 +620,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
1902 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
1903 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
1904 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
1905 +u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value);
1906 +u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value);
1907
1908 /* PMU support */
1909 extern void bcma_pmu_init(struct bcma_drv_cc *cc);
1910 +extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
1911
1912 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
1913 u32 value);
1914 --- a/include/linux/bcma/bcma_driver_mips.h
1915 +++ b/include/linux/bcma/bcma_driver_mips.h
1916 @@ -35,13 +35,15 @@ struct bcma_device;
1917 struct bcma_drv_mips {
1918 struct bcma_device *core;
1919 u8 setup_done:1;
1920 - unsigned int assigned_irqs;
1921 + u8 early_setup_done:1;
1922 };
1923
1924 #ifdef CONFIG_BCMA_DRIVER_MIPS
1925 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
1926 +extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
1927 #else
1928 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
1929 +static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
1930 #endif
1931
1932 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
1933 --- a/include/linux/bcma/bcma_regs.h
1934 +++ b/include/linux/bcma/bcma_regs.h
1935 @@ -11,11 +11,13 @@
1936 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1937 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1938 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
1939 +#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
1940 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1941 #define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1942 #define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
1943 #define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
1944 #define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
1945 +#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
1946 /* Is there any BCM4328 on BCMA bus? */
1947 #define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1948 #define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1949 @@ -83,4 +85,9 @@
1950 * (2 ZettaBytes), high 32 bits
1951 */
1952
1953 +#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
1954 +#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
1955 +#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
1956 +#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
1957 +
1958 #endif /* LINUX_BCMA_REGS_H_ */
1959 --- a/drivers/net/wireless/b43/main.c
1960 +++ b/drivers/net/wireless/b43/main.c
1961 @@ -4622,7 +4622,7 @@ static int b43_wireless_core_init(struct
1962 switch (dev->dev->bus_type) {
1963 #ifdef CONFIG_B43_BCMA
1964 case B43_BUS_BCMA:
1965 - bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
1966 + bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
1967 dev->dev->bdev, true);
1968 break;
1969 #endif
1970 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1971 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1972 @@ -695,7 +695,7 @@ void ai_pci_up(struct si_pub *sih)
1973 sii = container_of(sih, struct si_info, pub);
1974
1975 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1976 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
1977 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
1978 }
1979
1980 /* Unconfigure and/or apply various WARs when going down */
1981 @@ -706,7 +706,7 @@ void ai_pci_down(struct si_pub *sih)
1982 sii = container_of(sih, struct si_info, pub);
1983
1984 if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1985 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
1986 + bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
1987 }
1988
1989 /* Enable BT-COEX & Ex-PA for 4313 */
1990 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
1991 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
1992 @@ -5077,7 +5077,7 @@ static int brcms_b_up_prep(struct brcms_
1993 * Configure pci/pcmcia here instead of in brcms_c_attach()
1994 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1995 */
1996 - bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
1997 + bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
1998 true);
1999
2000 /*
Staging tree of Jo-Philipp Wich