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kernel: backport SSB/BCMA changes in preparation for a compat-wireless update
[openwrt/staging/jow.git] / target / linux / generic / patches-3.6 / 020-ssb_update.patch
1 --- a/arch/mips/bcm47xx/nvram.c
2 +++ b/arch/mips/bcm47xx/nvram.c
3 @@ -43,8 +43,8 @@ static void early_nvram_init(void)
4 #ifdef CONFIG_BCM47XX_SSB
5 case BCM47XX_BUS_TYPE_SSB:
6 mcore_ssb = &bcm47xx_bus.ssb.mipscore;
7 - base = mcore_ssb->flash_window;
8 - lim = mcore_ssb->flash_window_size;
9 + base = mcore_ssb->pflash.window;
10 + lim = mcore_ssb->pflash.window_size;
11 break;
12 #endif
13 #ifdef CONFIG_BCM47XX_BCMA
14 --- a/arch/mips/bcm47xx/wgt634u.c
15 +++ b/arch/mips/bcm47xx/wgt634u.c
16 @@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
17 SSB_CHIPCO_IRQ_GPIO);
18 }
19
20 - wgt634u_flash_data.width = mcore->flash_buswidth;
21 - wgt634u_flash_resource.start = mcore->flash_window;
22 - wgt634u_flash_resource.end = mcore->flash_window
23 - + mcore->flash_window_size
24 + wgt634u_flash_data.width = mcore->pflash.buswidth;
25 + wgt634u_flash_resource.start = mcore->pflash.window;
26 + wgt634u_flash_resource.end = mcore->pflash.window
27 + + mcore->pflash.window_size
28 - 1;
29 return platform_add_devices(wgt634u_devices,
30 ARRAY_SIZE(wgt634u_devices));
31 --- a/drivers/ssb/Kconfig
32 +++ b/drivers/ssb/Kconfig
33 @@ -136,6 +136,11 @@ config SSB_DRIVER_MIPS
34
35 If unsure, say N
36
37 +config SSB_SFLASH
38 + bool "SSB serial flash support"
39 + depends on SSB_DRIVER_MIPS && BROKEN
40 + default y
41 +
42 # Assumption: We are on embedded, if we compile the MIPS core.
43 config SSB_EMBEDDED
44 bool
45 @@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE
46
47 If unsure, say N
48
49 +config SSB_DRIVER_GPIO
50 + bool "SSB GPIO driver"
51 + depends on SSB && GPIOLIB
52 + help
53 + Driver to provide access to the GPIO pins on the bus.
54 +
55 + If unsure, say N
56 +
57 endmenu
58 --- a/drivers/ssb/Makefile
59 +++ b/drivers/ssb/Makefile
60 @@ -11,10 +11,12 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
61 # built-in drivers
62 ssb-y += driver_chipcommon.o
63 ssb-y += driver_chipcommon_pmu.o
64 +ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
65 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
66 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
67 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
68 ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o
69 +ssb-$(CONFIG_SSB_DRIVER_GPIO) += driver_gpio.o
70
71 # b43 pci-ssb-bridge driver
72 # Not strictly a part of SSB, but kept here for convenience
73 --- a/drivers/ssb/b43_pci_bridge.c
74 +++ b/drivers/ssb/b43_pci_bridge.c
75 @@ -37,6 +37,7 @@ static const struct pci_device_id b43_pc
76 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
77 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
78 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
79 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
80 { 0, },
81 };
82 MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
83 --- a/drivers/ssb/driver_chipcommon.c
84 +++ b/drivers/ssb/driver_chipcommon.c
85 @@ -4,6 +4,7 @@
86 *
87 * Copyright 2005, Broadcom Corporation
88 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
89 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
90 *
91 * Licensed under the GNU/GPL. See COPYING for details.
92 */
93 @@ -12,6 +13,7 @@
94 #include <linux/ssb/ssb_regs.h>
95 #include <linux/export.h>
96 #include <linux/pci.h>
97 +#include <linux/bcm47xx_wdt.h>
98
99 #include "ssb_private.h"
100
101 @@ -280,10 +282,76 @@ static void calc_fast_powerup_delay(stru
102 cc->fast_pwrup_delay = tmp;
103 }
104
105 +static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
106 +{
107 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
108 + return ssb_pmu_get_alp_clock(cc);
109 +
110 + return 20000000;
111 +}
112 +
113 +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
114 +{
115 + u32 nb;
116 +
117 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
118 + if (cc->dev->id.revision < 26)
119 + nb = 16;
120 + else
121 + nb = (cc->dev->id.revision >= 37) ? 32 : 24;
122 + } else {
123 + nb = 28;
124 + }
125 + if (nb == 32)
126 + return 0xffffffff;
127 + else
128 + return (1 << nb) - 1;
129 +}
130 +
131 +u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
132 +{
133 + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
134 +
135 + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
136 + return 0;
137 +
138 + return ssb_chipco_watchdog_timer_set(cc, ticks);
139 +}
140 +
141 +u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
142 +{
143 + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
144 + u32 ticks;
145 +
146 + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
147 + return 0;
148 +
149 + ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
150 + return ticks / cc->ticks_per_ms;
151 +}
152 +
153 +static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
154 +{
155 + struct ssb_bus *bus = cc->dev->bus;
156 +
157 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
158 + /* based on 32KHz ILP clock */
159 + return 32;
160 + } else {
161 + if (cc->dev->id.revision < 18)
162 + return ssb_clockspeed(bus) / 1000;
163 + else
164 + return ssb_chipco_alp_clock(cc) / 1000;
165 + }
166 +}
167 +
168 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
169 {
170 if (!cc->dev)
171 return; /* We don't have a ChipCommon */
172 +
173 + spin_lock_init(&cc->gpio_lock);
174 +
175 if (cc->dev->id.revision >= 11)
176 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
177 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
178 @@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip
179 chipco_powercontrol_init(cc);
180 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
181 calc_fast_powerup_delay(cc);
182 +
183 + if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
184 + cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
185 + cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
186 + }
187 }
188
189 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
190 @@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c
191 }
192
193 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
194 -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
195 +u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
196 {
197 - /* instant NMI */
198 - chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
199 + u32 maxt;
200 + enum ssb_clkmode clkmode;
201 +
202 + maxt = ssb_chipco_watchdog_get_max_timer(cc);
203 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
204 + if (ticks == 1)
205 + ticks = 2;
206 + else if (ticks > maxt)
207 + ticks = maxt;
208 + chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
209 + } else {
210 + clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
211 + ssb_chipco_set_clockmode(cc, clkmode);
212 + if (ticks > maxt)
213 + ticks = maxt;
214 + /* instant NMI */
215 + chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
216 + }
217 + return ticks;
218 }
219
220 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
221 @@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco
222
223 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
224 {
225 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
226 + unsigned long flags;
227 + u32 res = 0;
228 +
229 + spin_lock_irqsave(&cc->gpio_lock, flags);
230 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
231 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
232 +
233 + return res;
234 }
235
236 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
237 {
238 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
239 + unsigned long flags;
240 + u32 res = 0;
241 +
242 + spin_lock_irqsave(&cc->gpio_lock, flags);
243 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
244 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
245 +
246 + return res;
247 }
248
249 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
250 {
251 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
252 + unsigned long flags;
253 + u32 res = 0;
254 +
255 + spin_lock_irqsave(&cc->gpio_lock, flags);
256 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
257 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
258 +
259 + return res;
260 }
261 EXPORT_SYMBOL(ssb_chipco_gpio_control);
262
263 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
264 {
265 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
266 + unsigned long flags;
267 + u32 res = 0;
268 +
269 + spin_lock_irqsave(&cc->gpio_lock, flags);
270 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
271 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
272 +
273 + return res;
274 }
275
276 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
277 {
278 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
279 + unsigned long flags;
280 + u32 res = 0;
281 +
282 + spin_lock_irqsave(&cc->gpio_lock, flags);
283 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
284 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
285 +
286 + return res;
287 +}
288 +
289 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
290 +{
291 + unsigned long flags;
292 + u32 res = 0;
293 +
294 + if (cc->dev->id.revision < 20)
295 + return 0xffffffff;
296 +
297 + spin_lock_irqsave(&cc->gpio_lock, flags);
298 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
299 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
300 +
301 + return res;
302 +}
303 +
304 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
305 +{
306 + unsigned long flags;
307 + u32 res = 0;
308 +
309 + if (cc->dev->id.revision < 20)
310 + return 0xffffffff;
311 +
312 + spin_lock_irqsave(&cc->gpio_lock, flags);
313 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
314 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
315 +
316 + return res;
317 }
318
319 #ifdef CONFIG_SSB_SERIAL
320 @@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch
321 chipco_read32(cc, SSB_CHIPCO_CORECTL)
322 | SSB_CHIPCO_CORECTL_UARTCLK0);
323 } else if ((ccrev >= 11) && (ccrev != 15)) {
324 - /* Fixed ALP clock */
325 - baud_base = 20000000;
326 - if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
327 - /* FIXME: baud_base is different for devices with a PMU */
328 - SSB_WARN_ON(1);
329 - }
330 + baud_base = ssb_chipco_alp_clock(cc);
331 div = 1;
332 if (ccrev >= 21) {
333 /* Turn off UART clock before switching clocksource. */
334 --- a/drivers/ssb/driver_chipcommon_pmu.c
335 +++ b/drivers/ssb/driver_chipcommon_pmu.c
336 @@ -346,6 +346,8 @@ static void ssb_pmu_pll_init(struct ssb_
337 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
338 }
339 break;
340 + case 43222:
341 + break;
342 default:
343 ssb_printk(KERN_ERR PFX
344 "ERROR: PLL init unknown for device %04X\n",
345 @@ -434,6 +436,7 @@ static void ssb_pmu_resources_init(struc
346 min_msk = 0xCBB;
347 break;
348 case 0x4322:
349 + case 43222:
350 /* We keep the default settings:
351 * min_msk = 0xCBB
352 * max_msk = 0x7FFFF
353 @@ -615,6 +618,33 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
354 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
355 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
356
357 +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
358 +{
359 + u32 crystalfreq;
360 + const struct pmu0_plltab_entry *e = NULL;
361 +
362 + crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
363 + SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
364 + e = pmu0_plltab_find_entry(crystalfreq);
365 + BUG_ON(!e);
366 + return e->freq * 1000;
367 +}
368 +
369 +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
370 +{
371 + struct ssb_bus *bus = cc->dev->bus;
372 +
373 + switch (bus->chip_id) {
374 + case 0x5354:
375 + ssb_pmu_get_alp_clock_clk0(cc);
376 + default:
377 + ssb_printk(KERN_ERR PFX
378 + "ERROR: PMU alp clock unknown for device %04X\n",
379 + bus->chip_id);
380 + return 0;
381 + }
382 +}
383 +
384 u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
385 {
386 struct ssb_bus *bus = cc->dev->bus;
387 @@ -645,3 +675,32 @@ u32 ssb_pmu_get_controlclock(struct ssb_
388 return 0;
389 }
390 }
391 +
392 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
393 +{
394 + u32 pmu_ctl = 0;
395 +
396 + switch (cc->dev->bus->chip_id) {
397 + case 0x4322:
398 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
399 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
400 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
401 + if (spuravoid == 1)
402 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
403 + else
404 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
405 + pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
406 + break;
407 + case 43222:
408 + /* TODO: BCM43222 requires updating PLLs too */
409 + return;
410 + default:
411 + ssb_printk(KERN_ERR PFX
412 + "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
413 + cc->dev->bus->chip_id);
414 + return;
415 + }
416 +
417 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
418 +}
419 +EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
420 --- /dev/null
421 +++ b/drivers/ssb/driver_chipcommon_sflash.c
422 @@ -0,0 +1,18 @@
423 +/*
424 + * Sonics Silicon Backplane
425 + * ChipCommon serial flash interface
426 + *
427 + * Licensed under the GNU/GPL. See COPYING for details.
428 + */
429 +
430 +#include <linux/ssb/ssb.h>
431 +
432 +#include "ssb_private.h"
433 +
434 +/* Initialize serial flash access */
435 +int ssb_sflash_init(struct ssb_chipcommon *cc)
436 +{
437 + pr_err("Serial flash support is not implemented yet!\n");
438 +
439 + return -ENOTSUPP;
440 +}
441 --- a/drivers/ssb/driver_extif.c
442 +++ b/drivers/ssb/driver_extif.c
443 @@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s
444 *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
445 }
446
447 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
448 - u32 ticks)
449 +u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
450 {
451 + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
452 +
453 + return ssb_extif_watchdog_timer_set(extif, ticks);
454 +}
455 +
456 +u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
457 +{
458 + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
459 + u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
460 +
461 + ticks = ssb_extif_watchdog_timer_set(extif, ticks);
462 +
463 + return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
464 +}
465 +
466 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
467 +{
468 + if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
469 + ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
470 extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
471 +
472 + return ticks;
473 +}
474 +
475 +void ssb_extif_init(struct ssb_extif *extif)
476 +{
477 + if (!extif->dev)
478 + return; /* We don't have a Extif core */
479 + spin_lock_init(&extif->gpio_lock);
480 }
481
482 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
483 @@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif *
484
485 u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
486 {
487 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
488 + unsigned long flags;
489 + u32 res = 0;
490 +
491 + spin_lock_irqsave(&extif->gpio_lock, flags);
492 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
493 mask, value);
494 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
495 +
496 + return res;
497 }
498
499 u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
500 {
501 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
502 + unsigned long flags;
503 + u32 res = 0;
504 +
505 + spin_lock_irqsave(&extif->gpio_lock, flags);
506 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
507 mask, value);
508 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
509 +
510 + return res;
511 }
512
513 u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
514 {
515 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
516 + unsigned long flags;
517 + u32 res = 0;
518 +
519 + spin_lock_irqsave(&extif->gpio_lock, flags);
520 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
521 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
522 +
523 + return res;
524 }
525
526 u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
527 {
528 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
529 + unsigned long flags;
530 + u32 res = 0;
531 +
532 + spin_lock_irqsave(&extif->gpio_lock, flags);
533 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
534 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
535 +
536 + return res;
537 }
538 --- /dev/null
539 +++ b/drivers/ssb/driver_gpio.c
540 @@ -0,0 +1,176 @@
541 +/*
542 + * Sonics Silicon Backplane
543 + * GPIO driver
544 + *
545 + * Copyright 2011, Broadcom Corporation
546 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
547 + *
548 + * Licensed under the GNU/GPL. See COPYING for details.
549 + */
550 +
551 +#include <linux/gpio.h>
552 +#include <linux/export.h>
553 +#include <linux/ssb/ssb.h>
554 +
555 +#include "ssb_private.h"
556 +
557 +static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
558 +{
559 + return container_of(chip, struct ssb_bus, gpio);
560 +}
561 +
562 +static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
563 +{
564 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
565 +
566 + return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio);
567 +}
568 +
569 +static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio,
570 + int value)
571 +{
572 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
573 +
574 + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
575 +}
576 +
577 +static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip,
578 + unsigned gpio)
579 +{
580 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
581 +
582 + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0);
583 + return 0;
584 +}
585 +
586 +static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip,
587 + unsigned gpio, int value)
588 +{
589 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
590 +
591 + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio);
592 + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
593 + return 0;
594 +}
595 +
596 +static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio)
597 +{
598 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
599 +
600 + ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0);
601 + /* clear pulldown */
602 + ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0);
603 + /* Set pullup */
604 + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio);
605 +
606 + return 0;
607 +}
608 +
609 +static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio)
610 +{
611 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
612 +
613 + /* clear pullup */
614 + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
615 +}
616 +
617 +static int ssb_gpio_chipco_init(struct ssb_bus *bus)
618 +{
619 + struct gpio_chip *chip = &bus->gpio;
620 +
621 + chip->label = "ssb_chipco_gpio";
622 + chip->owner = THIS_MODULE;
623 + chip->request = ssb_gpio_chipco_request;
624 + chip->free = ssb_gpio_chipco_free;
625 + chip->get = ssb_gpio_chipco_get_value;
626 + chip->set = ssb_gpio_chipco_set_value;
627 + chip->direction_input = ssb_gpio_chipco_direction_input;
628 + chip->direction_output = ssb_gpio_chipco_direction_output;
629 + chip->ngpio = 16;
630 + /* There is just one SoC in one device and its GPIO addresses should be
631 + * deterministic to address them more easily. The other buses could get
632 + * a random base number. */
633 + if (bus->bustype == SSB_BUSTYPE_SSB)
634 + chip->base = 0;
635 + else
636 + chip->base = -1;
637 +
638 + return gpiochip_add(chip);
639 +}
640 +
641 +#ifdef CONFIG_SSB_DRIVER_EXTIF
642 +
643 +static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
644 +{
645 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
646 +
647 + return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio);
648 +}
649 +
650 +static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio,
651 + int value)
652 +{
653 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
654 +
655 + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
656 +}
657 +
658 +static int ssb_gpio_extif_direction_input(struct gpio_chip *chip,
659 + unsigned gpio)
660 +{
661 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
662 +
663 + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0);
664 + return 0;
665 +}
666 +
667 +static int ssb_gpio_extif_direction_output(struct gpio_chip *chip,
668 + unsigned gpio, int value)
669 +{
670 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
671 +
672 + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio);
673 + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
674 + return 0;
675 +}
676 +
677 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
678 +{
679 + struct gpio_chip *chip = &bus->gpio;
680 +
681 + chip->label = "ssb_extif_gpio";
682 + chip->owner = THIS_MODULE;
683 + chip->get = ssb_gpio_extif_get_value;
684 + chip->set = ssb_gpio_extif_set_value;
685 + chip->direction_input = ssb_gpio_extif_direction_input;
686 + chip->direction_output = ssb_gpio_extif_direction_output;
687 + chip->ngpio = 5;
688 + /* There is just one SoC in one device and its GPIO addresses should be
689 + * deterministic to address them more easily. The other buses could get
690 + * a random base number. */
691 + if (bus->bustype == SSB_BUSTYPE_SSB)
692 + chip->base = 0;
693 + else
694 + chip->base = -1;
695 +
696 + return gpiochip_add(chip);
697 +}
698 +
699 +#else
700 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
701 +{
702 + return -ENOTSUPP;
703 +}
704 +#endif
705 +
706 +int ssb_gpio_init(struct ssb_bus *bus)
707 +{
708 + if (ssb_chipco_available(&bus->chipco))
709 + return ssb_gpio_chipco_init(bus);
710 + else if (ssb_extif_available(&bus->extif))
711 + return ssb_gpio_extif_init(bus);
712 + else
713 + SSB_WARN_ON(1);
714 +
715 + return -1;
716 +}
717 --- a/drivers/ssb/driver_mipscore.c
718 +++ b/drivers/ssb/driver_mipscore.c
719 @@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
720 {
721 struct ssb_bus *bus = mcore->dev->bus;
722
723 - if (bus->extif.dev)
724 + if (ssb_extif_available(&bus->extif))
725 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
726 - else if (bus->chipco.dev)
727 + else if (ssb_chipco_available(&bus->chipco))
728 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
729 else
730 mcore->nr_serial_ports = 0;
731 @@ -190,16 +190,33 @@ static void ssb_mips_flash_detect(struct
732 {
733 struct ssb_bus *bus = mcore->dev->bus;
734
735 - mcore->flash_buswidth = 2;
736 - if (bus->chipco.dev) {
737 - mcore->flash_window = 0x1c000000;
738 - mcore->flash_window_size = 0x02000000;
739 + /* When there is no chipcommon on the bus there is 4MB flash */
740 + if (!ssb_chipco_available(&bus->chipco)) {
741 + mcore->pflash.present = true;
742 + mcore->pflash.buswidth = 2;
743 + mcore->pflash.window = SSB_FLASH1;
744 + mcore->pflash.window_size = SSB_FLASH1_SZ;
745 + return;
746 + }
747 +
748 + /* There is ChipCommon, so use it to read info about flash */
749 + switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
750 + case SSB_CHIPCO_FLASHT_STSER:
751 + case SSB_CHIPCO_FLASHT_ATSER:
752 + pr_debug("Found serial flash\n");
753 + ssb_sflash_init(&bus->chipco);
754 + break;
755 + case SSB_CHIPCO_FLASHT_PARA:
756 + pr_debug("Found parallel flash\n");
757 + mcore->pflash.present = true;
758 + mcore->pflash.window = SSB_FLASH2;
759 + mcore->pflash.window_size = SSB_FLASH2_SZ;
760 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
761 & SSB_CHIPCO_CFG_DS16) == 0)
762 - mcore->flash_buswidth = 1;
763 - } else {
764 - mcore->flash_window = 0x1fc00000;
765 - mcore->flash_window_size = 0x00400000;
766 + mcore->pflash.buswidth = 1;
767 + else
768 + mcore->pflash.buswidth = 2;
769 + break;
770 }
771 }
772
773 @@ -211,9 +228,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
774 if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
775 return ssb_pmu_get_cpu_clock(&bus->chipco);
776
777 - if (bus->extif.dev) {
778 + if (ssb_extif_available(&bus->extif)) {
779 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
780 - } else if (bus->chipco.dev) {
781 + } else if (ssb_chipco_available(&bus->chipco)) {
782 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
783 } else
784 return 0;
785 @@ -249,9 +266,9 @@ void ssb_mipscore_init(struct ssb_mipsco
786 hz = 100000000;
787 ns = 1000000000 / hz;
788
789 - if (bus->extif.dev)
790 + if (ssb_extif_available(&bus->extif))
791 ssb_extif_timing_init(&bus->extif, ns);
792 - else if (bus->chipco.dev)
793 + else if (ssb_chipco_available(&bus->chipco))
794 ssb_chipco_timing_init(&bus->chipco, ns);
795
796 /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
797 --- a/drivers/ssb/embedded.c
798 +++ b/drivers/ssb/embedded.c
799 @@ -4,11 +4,13 @@
800 *
801 * Copyright 2005-2008, Broadcom Corporation
802 * Copyright 2006-2008, Michael Buesch <m@bues.ch>
803 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
804 *
805 * Licensed under the GNU/GPL. See COPYING for details.
806 */
807
808 #include <linux/export.h>
809 +#include <linux/platform_device.h>
810 #include <linux/ssb/ssb.h>
811 #include <linux/ssb/ssb_embedded.h>
812 #include <linux/ssb/ssb_driver_pci.h>
813 @@ -32,6 +34,39 @@ int ssb_watchdog_timer_set(struct ssb_bu
814 }
815 EXPORT_SYMBOL(ssb_watchdog_timer_set);
816
817 +int ssb_watchdog_register(struct ssb_bus *bus)
818 +{
819 + struct bcm47xx_wdt wdt = {};
820 + struct platform_device *pdev;
821 +
822 + if (ssb_chipco_available(&bus->chipco)) {
823 + wdt.driver_data = &bus->chipco;
824 + wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
825 + wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
826 + wdt.max_timer_ms = bus->chipco.max_timer_ms;
827 + } else if (ssb_extif_available(&bus->extif)) {
828 + wdt.driver_data = &bus->extif;
829 + wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
830 + wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
831 + wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
832 + } else {
833 + return -ENODEV;
834 + }
835 +
836 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
837 + bus->busnumber, &wdt,
838 + sizeof(wdt));
839 + if (IS_ERR(pdev)) {
840 + ssb_dprintk(KERN_INFO PFX
841 + "can not register watchdog device, err: %li\n",
842 + PTR_ERR(pdev));
843 + return PTR_ERR(pdev);
844 + }
845 +
846 + bus->watchdog = pdev;
847 + return 0;
848 +}
849 +
850 u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
851 {
852 unsigned long flags;
853 --- a/drivers/ssb/main.c
854 +++ b/drivers/ssb/main.c
855 @@ -13,6 +13,7 @@
856 #include <linux/delay.h>
857 #include <linux/io.h>
858 #include <linux/module.h>
859 +#include <linux/platform_device.h>
860 #include <linux/ssb/ssb.h>
861 #include <linux/ssb/ssb_regs.h>
862 #include <linux/ssb/ssb_driver_gige.h>
863 @@ -433,6 +434,11 @@ static void ssb_devices_unregister(struc
864 if (sdev->dev)
865 device_unregister(sdev->dev);
866 }
867 +
868 +#ifdef CONFIG_SSB_EMBEDDED
869 + if (bus->bustype == SSB_BUSTYPE_SSB)
870 + platform_device_unregister(bus->watchdog);
871 +#endif
872 }
873
874 void ssb_bus_unregister(struct ssb_bus *bus)
875 @@ -561,6 +567,8 @@ static int __devinit ssb_attach_queued_b
876 if (err)
877 goto error;
878 ssb_pcicore_init(&bus->pcicore);
879 + if (bus->bustype == SSB_BUSTYPE_SSB)
880 + ssb_watchdog_register(bus);
881 ssb_bus_may_powerdown(bus);
882
883 err = ssb_devices_register(bus);
884 @@ -796,7 +804,14 @@ static int __devinit ssb_bus_register(st
885 if (err)
886 goto err_pcmcia_exit;
887 ssb_chipcommon_init(&bus->chipco);
888 + ssb_extif_init(&bus->extif);
889 ssb_mipscore_init(&bus->mipscore);
890 + err = ssb_gpio_init(bus);
891 + if (err == -ENOTSUPP)
892 + ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n");
893 + else if (err)
894 + ssb_dprintk(KERN_ERR PFX
895 + "Error registering GPIO driver: %i\n", err);
896 err = ssb_fetch_invariants(bus, get_invariants);
897 if (err) {
898 ssb_bus_may_powerdown(bus);
899 @@ -1118,8 +1133,7 @@ static u32 ssb_tmslow_reject_bitmask(str
900 case SSB_IDLOW_SSBREV_27: /* same here */
901 return SSB_TMSLOW_REJECT; /* this is a guess */
902 default:
903 - printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
904 - WARN_ON(1);
905 + WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
906 }
907 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
908 }
909 --- a/drivers/ssb/ssb_private.h
910 +++ b/drivers/ssb/ssb_private.h
911 @@ -3,6 +3,7 @@
912
913 #include <linux/ssb/ssb.h>
914 #include <linux/types.h>
915 +#include <linux/bcm47xx_wdt.h>
916
917
918 #define PFX "ssb: "
919 @@ -210,5 +211,63 @@ static inline void b43_pci_ssb_bridge_ex
920 /* driver_chipcommon_pmu.c */
921 extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
922 extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
923 +extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
924 +
925 +extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
926 + u32 ticks);
927 +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
928 +
929 +/* driver_chipcommon_sflash.c */
930 +#ifdef CONFIG_SSB_SFLASH
931 +int ssb_sflash_init(struct ssb_chipcommon *cc);
932 +#else
933 +static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
934 +{
935 + pr_err("Serial flash not supported\n");
936 + return 0;
937 +}
938 +#endif /* CONFIG_SSB_SFLASH */
939 +
940 +#ifdef CONFIG_SSB_DRIVER_EXTIF
941 +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
942 +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
943 +#else
944 +static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
945 + u32 ticks)
946 +{
947 + return 0;
948 +}
949 +static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
950 + u32 ms)
951 +{
952 + return 0;
953 +}
954 +#endif
955 +
956 +#ifdef CONFIG_SSB_EMBEDDED
957 +extern int ssb_watchdog_register(struct ssb_bus *bus);
958 +#else /* CONFIG_SSB_EMBEDDED */
959 +static inline int ssb_watchdog_register(struct ssb_bus *bus)
960 +{
961 + return 0;
962 +}
963 +#endif /* CONFIG_SSB_EMBEDDED */
964 +
965 +#ifdef CONFIG_SSB_DRIVER_EXTIF
966 +extern void ssb_extif_init(struct ssb_extif *extif);
967 +#else
968 +static inline void ssb_extif_init(struct ssb_extif *extif)
969 +{
970 +}
971 +#endif
972 +
973 +#ifdef CONFIG_SSB_DRIVER_GPIO
974 +extern int ssb_gpio_init(struct ssb_bus *bus);
975 +#else /* CONFIG_SSB_DRIVER_GPIO */
976 +static inline int ssb_gpio_init(struct ssb_bus *bus)
977 +{
978 + return -ENOTSUPP;
979 +}
980 +#endif /* CONFIG_SSB_DRIVER_GPIO */
981
982 #endif /* LINUX_SSB_PRIVATE_H_ */
983 --- a/include/linux/ssb/ssb.h
984 +++ b/include/linux/ssb/ssb.h
985 @@ -6,8 +6,10 @@
986 #include <linux/types.h>
987 #include <linux/spinlock.h>
988 #include <linux/pci.h>
989 +#include <linux/gpio.h>
990 #include <linux/mod_devicetable.h>
991 #include <linux/dma-mapping.h>
992 +#include <linux/platform_device.h>
993
994 #include <linux/ssb/ssb_regs.h>
995
996 @@ -432,7 +434,11 @@ struct ssb_bus {
997 #ifdef CONFIG_SSB_EMBEDDED
998 /* Lock for GPIO register access. */
999 spinlock_t gpio_lock;
1000 + struct platform_device *watchdog;
1001 #endif /* EMBEDDED */
1002 +#ifdef CONFIG_SSB_DRIVER_GPIO
1003 + struct gpio_chip gpio;
1004 +#endif /* DRIVER_GPIO */
1005
1006 /* Internal-only stuff follows. Do not touch. */
1007 struct list_head list;
1008 --- a/include/linux/ssb/ssb_driver_chipcommon.h
1009 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
1010 @@ -219,6 +219,7 @@
1011 #define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
1012 #define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
1013 #define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
1014 +#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400
1015 #define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
1016 #define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
1017 #define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
1018 @@ -504,7 +505,9 @@
1019 #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
1020 #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
1021 #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
1022 -#define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */
1023 +#define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
1024 +#define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
1025 +#define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
1026
1027 /* Status register bits for ST flashes */
1028 #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
1029 @@ -588,7 +591,10 @@ struct ssb_chipcommon {
1030 u32 status;
1031 /* Fast Powerup Delay constant */
1032 u16 fast_pwrup_delay;
1033 + spinlock_t gpio_lock;
1034 struct ssb_chipcommon_pmu pmu;
1035 + u32 ticks_per_ms;
1036 + u32 max_timer_ms;
1037 };
1038
1039 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
1040 @@ -628,8 +634,7 @@ enum ssb_clkmode {
1041 extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
1042 enum ssb_clkmode mode);
1043
1044 -extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
1045 - u32 ticks);
1046 +extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
1047
1048 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
1049
1050 @@ -642,6 +647,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi
1051 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
1052 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
1053 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
1054 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value);
1055 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value);
1056
1057 #ifdef CONFIG_SSB_SERIAL
1058 extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
1059 @@ -661,5 +668,6 @@ enum ssb_pmu_ldo_volt_id {
1060 void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
1061 enum ssb_pmu_ldo_volt_id id, u32 voltage);
1062 void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
1063 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
1064
1065 #endif /* LINUX_SSB_CHIPCO_H_ */
1066 --- a/include/linux/ssb/ssb_driver_extif.h
1067 +++ b/include/linux/ssb/ssb_driver_extif.h
1068 @@ -152,12 +152,16 @@
1069 /* watchdog */
1070 #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
1071
1072 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
1073 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
1074 + / (SSB_EXTIF_WATCHDOG_CLK / 1000))
1075
1076
1077 #ifdef CONFIG_SSB_DRIVER_EXTIF
1078
1079 struct ssb_extif {
1080 struct ssb_device *dev;
1081 + spinlock_t gpio_lock;
1082 };
1083
1084 static inline bool ssb_extif_available(struct ssb_extif *extif)
1085 @@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s
1086 extern void ssb_extif_timing_init(struct ssb_extif *extif,
1087 unsigned long ns);
1088
1089 -extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
1090 - u32 ticks);
1091 +extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
1092
1093 /* Extif GPIO pin access */
1094 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
1095 @@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s
1096 }
1097
1098 static inline
1099 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
1100 - u32 ticks)
1101 +void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
1102 {
1103 }
1104
1105 +static inline
1106 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
1107 +{
1108 + return 0;
1109 +}
1110 +
1111 +static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
1112 +{
1113 + return 0;
1114 +}
1115 +
1116 +static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
1117 + u32 value)
1118 +{
1119 + return 0;
1120 +}
1121 +
1122 +static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
1123 + u32 value)
1124 +{
1125 + return 0;
1126 +}
1127 +
1128 +static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
1129 + u32 value)
1130 +{
1131 + return 0;
1132 +}
1133 +
1134 +static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
1135 + u32 value)
1136 +{
1137 + return 0;
1138 +}
1139 +
1140 +#ifdef CONFIG_SSB_SERIAL
1141 +static inline int ssb_extif_serial_init(struct ssb_extif *extif,
1142 + struct ssb_serial_port *ports)
1143 +{
1144 + return 0;
1145 +}
1146 +#endif /* CONFIG_SSB_SERIAL */
1147 +
1148 #endif /* CONFIG_SSB_DRIVER_EXTIF */
1149 #endif /* LINUX_SSB_EXTIFCORE_H_ */
1150 --- a/include/linux/ssb/ssb_driver_mips.h
1151 +++ b/include/linux/ssb/ssb_driver_mips.h
1152 @@ -13,6 +13,12 @@ struct ssb_serial_port {
1153 unsigned int reg_shift;
1154 };
1155
1156 +struct ssb_pflash {
1157 + bool present;
1158 + u8 buswidth;
1159 + u32 window;
1160 + u32 window_size;
1161 +};
1162
1163 struct ssb_mipscore {
1164 struct ssb_device *dev;
1165 @@ -20,9 +26,7 @@ struct ssb_mipscore {
1166 int nr_serial_ports;
1167 struct ssb_serial_port serial_ports[4];
1168
1169 - u8 flash_buswidth;
1170 - u32 flash_window;
1171 - u32 flash_window_size;
1172 + struct ssb_pflash pflash;
1173 };
1174
1175 extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
1176 --- a/include/linux/ssb/ssb_regs.h
1177 +++ b/include/linux/ssb/ssb_regs.h
1178 @@ -289,11 +289,11 @@
1179 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
1180 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
1181 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
1182 -#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
1183 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
1184 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
1185 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
1186 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
1187 +#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */
1188 +#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1189 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0
1190 +#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1191 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8
1192 #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
1193 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
1194 #define SSB_SPROM4_AGAIN0_SHIFT 0
1195 @@ -485,7 +485,7 @@
1196 #define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
1197 #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
1198 #define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
1199 -#define SSB_SPROM8_TEMPDELTA 0x00BA
1200 +#define SSB_SPROM8_TEMPDELTA 0x00BC
1201 #define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
1202 #define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
1203 #define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
1204 --- /dev/null
1205 +++ b/include/linux/bcm47xx_wdt.h
1206 @@ -0,0 +1,19 @@
1207 +#ifndef LINUX_BCM47XX_WDT_H_
1208 +#define LINUX_BCM47XX_WDT_H_
1209 +
1210 +#include <linux/types.h>
1211 +
1212 +
1213 +struct bcm47xx_wdt {
1214 + u32 (*timer_set)(struct bcm47xx_wdt *, u32);
1215 + u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
1216 + u32 max_timer_ms;
1217 +
1218 + void *driver_data;
1219 +};
1220 +
1221 +static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
1222 +{
1223 + return wdt->driver_data;
1224 +}
1225 +#endif /* LINUX_BCM47XX_WDT_H_ */
1226 --- a/drivers/net/wireless/b43/phy_n.c
1227 +++ b/drivers/net/wireless/b43/phy_n.c
1228 @@ -4583,7 +4583,8 @@ static void b43_nphy_pmu_spur_avoid(stru
1229 #endif
1230 #ifdef CONFIG_B43_SSB
1231 case B43_BUS_SSB:
1232 - /* FIXME */
1233 + ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
1234 + avoid);
1235 break;
1236 #endif
1237 }
1238 --- a/drivers/ssb/pci.c
1239 +++ b/drivers/ssb/pci.c
1240 @@ -339,6 +339,21 @@ static s8 r123_extract_antgain(u8 sprom_
1241 return (s8)gain;
1242 }
1243
1244 +static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
1245 +{
1246 + SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1247 + SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
1248 + SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
1249 + SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
1250 + SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
1251 + SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
1252 + SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
1253 + SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
1254 + SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
1255 + SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
1256 + SSB_SPROM2_MAXP_A_LO_SHIFT);
1257 +}
1258 +
1259 static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
1260 {
1261 int i;
1262 @@ -398,8 +413,7 @@ static void sprom_extract_r123(struct ss
1263 SSB_SPROM1_ITSSI_A_SHIFT);
1264 SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
1265 SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
1266 - if (out->revision >= 2)
1267 - SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1268 +
1269 SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
1270 SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
1271
1272 @@ -410,6 +424,8 @@ static void sprom_extract_r123(struct ss
1273 out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
1274 SSB_SPROM1_AGAIN_A,
1275 SSB_SPROM1_AGAIN_A_SHIFT);
1276 + if (out->revision >= 2)
1277 + sprom_extract_r23(out, in);
1278 }
1279
1280 /* Revs 4 5 and 8 have partially shared layout */
Staging tree of Jo-Philipp Wich