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kernel: bcma: update to version from wireless-testing tag master-2012-07-11
[openwrt/openwrt.git] / target / linux / generic / patches-3.3 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -29,7 +29,7 @@ config BCMA_HOST_PCI
4
5 config BCMA_DRIVER_PCI_HOSTMODE
6 bool "Driver for PCI core working in hostmode"
7 - depends on BCMA && MIPS
8 + depends on BCMA && MIPS && BCMA_HOST_PCI
9 help
10 PCI core hostmode operation (external PCI bus).
11
12 --- a/drivers/bcma/bcma_private.h
13 +++ b/drivers/bcma/bcma_private.h
14 @@ -10,10 +10,19 @@
15
16 #define BCMA_CORE_SIZE 0x1000
17
18 +#define bcma_err(bus, fmt, ...) \
19 + pr_err("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
20 +#define bcma_warn(bus, fmt, ...) \
21 + pr_warn("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
22 +#define bcma_info(bus, fmt, ...) \
23 + pr_info("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
24 +#define bcma_debug(bus, fmt, ...) \
25 + pr_debug("bus%d: " fmt, (bus)->num, ##__VA_ARGS__)
26 +
27 struct bcma_bus;
28
29 /* main.c */
30 -int bcma_bus_register(struct bcma_bus *bus);
31 +int __devinit bcma_bus_register(struct bcma_bus *bus);
32 void bcma_bus_unregister(struct bcma_bus *bus);
33 int __init bcma_bus_early_register(struct bcma_bus *bus,
34 struct bcma_device *core_cc,
35 @@ -48,8 +57,12 @@ extern int __init bcma_host_pci_init(voi
36 extern void __exit bcma_host_pci_exit(void);
37 #endif /* CONFIG_BCMA_HOST_PCI */
38
39 +/* driver_pci.c */
40 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
41 +
42 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
43 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
44 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
45 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
46 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
47
48 #endif
49 --- a/drivers/bcma/core.c
50 +++ b/drivers/bcma/core.c
51 @@ -30,6 +30,7 @@ void bcma_core_disable(struct bcma_devic
52 udelay(10);
53
54 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
55 + bcma_aread32(core, BCMA_RESET_CTL);
56 udelay(1);
57 }
58 EXPORT_SYMBOL_GPL(bcma_core_disable);
59 @@ -74,10 +75,10 @@ void bcma_core_set_clockmode(struct bcma
60 udelay(10);
61 }
62 if (i)
63 - pr_err("HT force timeout\n");
64 + bcma_err(core->bus, "HT force timeout\n");
65 break;
66 case BCMA_CLKMODE_DYNAMIC:
67 - pr_warn("Dynamic clockmode not supported yet!\n");
68 + bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT);
69 break;
70 }
71 }
72 @@ -101,9 +102,9 @@ void bcma_core_pll_ctl(struct bcma_devic
73 udelay(10);
74 }
75 if (i)
76 - pr_err("PLL enable timeout\n");
77 + bcma_err(core->bus, "PLL enable timeout\n");
78 } else {
79 - pr_warn("Disabling PLL not supported yet!\n");
80 + bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
81 }
82 }
83 EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
84 @@ -119,8 +120,8 @@ u32 bcma_core_dma_translation(struct bcm
85 else
86 return BCMA_DMA_TRANSLATION_DMA32_CMT;
87 default:
88 - pr_err("DMA translation unknown for host %d\n",
89 - core->bus->hosttype);
90 + bcma_err(core->bus, "DMA translation unknown for host %d\n",
91 + core->bus->hosttype);
92 }
93 return BCMA_DMA_TRANSLATION_NONE;
94 }
95 --- a/drivers/bcma/driver_chipcommon.c
96 +++ b/drivers/bcma/driver_chipcommon.c
97 @@ -44,7 +44,7 @@ void bcma_core_chipcommon_init(struct bc
98 if (cc->capabilities & BCMA_CC_CAP_PMU)
99 bcma_pmu_init(cc);
100 if (cc->capabilities & BCMA_CC_CAP_PCTL)
101 - pr_err("Power control not implemented!\n");
102 + bcma_err(cc->core->bus, "Power control not implemented!\n");
103
104 if (cc->core->id.rev >= 16) {
105 if (cc->core->bus->sprom.leddc_on_time &&
106 @@ -137,8 +137,7 @@ void bcma_chipco_serial_init(struct bcma
107 | BCMA_CC_CORECTL_UARTCLKEN);
108 }
109 } else {
110 - pr_err("serial not supported on this device ccrev: 0x%x\n",
111 - ccrev);
112 + bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev);
113 return;
114 }
115
116 --- a/drivers/bcma/driver_chipcommon_pmu.c
117 +++ b/drivers/bcma/driver_chipcommon_pmu.c
118 @@ -3,7 +3,8 @@
119 * ChipCommon Power Management Unit driver
120 *
121 * Copyright 2009, Michael Buesch <m@bues.ch>
122 - * Copyright 2007, Broadcom Corporation
123 + * Copyright 2007, 2011, Broadcom Corporation
124 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
125 *
126 * Licensed under the GNU/GPL. See COPYING for details.
127 */
128 @@ -54,38 +55,19 @@ void bcma_chipco_regctl_maskset(struct b
129 }
130 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
131
132 -static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
133 -{
134 - struct bcma_bus *bus = cc->core->bus;
135 -
136 - switch (bus->chipinfo.id) {
137 - case 0x4313:
138 - case 0x4331:
139 - case 43224:
140 - case 43225:
141 - break;
142 - default:
143 - pr_err("PLL init unknown for device 0x%04X\n",
144 - bus->chipinfo.id);
145 - }
146 -}
147 -
148 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
149 {
150 struct bcma_bus *bus = cc->core->bus;
151 u32 min_msk = 0, max_msk = 0;
152
153 switch (bus->chipinfo.id) {
154 - case 0x4313:
155 + case BCMA_CHIP_ID_BCM4313:
156 min_msk = 0x200D;
157 max_msk = 0xFFFF;
158 break;
159 - case 43224:
160 - case 43225:
161 - break;
162 default:
163 - pr_err("PMU resource config unknown for device 0x%04X\n",
164 - bus->chipinfo.id);
165 + bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
166 + bus->chipinfo.id);
167 }
168
169 /* Set the resource masks. */
170 @@ -93,22 +75,9 @@ static void bcma_pmu_resources_init(stru
171 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
172 if (max_msk)
173 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
174 -}
175 -
176 -void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
177 -{
178 - struct bcma_bus *bus = cc->core->bus;
179
180 - switch (bus->chipinfo.id) {
181 - case 0x4313:
182 - case 0x4331:
183 - case 43224:
184 - case 43225:
185 - break;
186 - default:
187 - pr_err("PMU switch/regulators init unknown for device "
188 - "0x%04X\n", bus->chipinfo.id);
189 - }
190 + /* Add some delay; allow resources to come up and settle. */
191 + mdelay(2);
192 }
193
194 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
195 @@ -122,8 +91,11 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
196 val |= BCMA_CHIPCTL_4331_EXTPA_EN;
197 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
198 val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
199 + else if (bus->chipinfo.rev > 0)
200 + val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
201 } else {
202 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
203 + val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
204 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
205 }
206 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
207 @@ -134,26 +106,38 @@ void bcma_pmu_workarounds(struct bcma_dr
208 struct bcma_bus *bus = cc->core->bus;
209
210 switch (bus->chipinfo.id) {
211 - case 0x4313:
212 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
213 + case BCMA_CHIP_ID_BCM4313:
214 + /* enable 12 mA drive strenth for 4313 and set chipControl
215 + register bit 1 */
216 + bcma_chipco_chipctl_maskset(cc, 0,
217 + BCMA_CCTRL_4313_12MA_LED_DRIVE,
218 + BCMA_CCTRL_4313_12MA_LED_DRIVE);
219 break;
220 - case 0x4331:
221 - /* BCM4331 workaround is SPROM-related, we put it in sprom.c */
222 + case BCMA_CHIP_ID_BCM4331:
223 + case BCMA_CHIP_ID_BCM43431:
224 + /* Ext PA lines must be enabled for tx on BCM4331 */
225 + bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
226 break;
227 - case 43224:
228 + case BCMA_CHIP_ID_BCM43224:
229 + case BCMA_CHIP_ID_BCM43421:
230 + /* enable 12 mA drive strenth for 43224 and set chipControl
231 + register bit 15 */
232 if (bus->chipinfo.rev == 0) {
233 - pr_err("Workarounds for 43224 rev 0 not fully "
234 - "implemented\n");
235 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
236 + bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
237 + BCMA_CCTRL_43224_GPIO_TOGGLE,
238 + BCMA_CCTRL_43224_GPIO_TOGGLE);
239 + bcma_chipco_chipctl_maskset(cc, 0,
240 + BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
241 + BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
242 } else {
243 - bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
244 + bcma_chipco_chipctl_maskset(cc, 0,
245 + BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
246 + BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
247 }
248 break;
249 - case 43225:
250 - break;
251 default:
252 - pr_err("Workarounds unknown for device 0x%04X\n",
253 - bus->chipinfo.id);
254 + bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
255 + bus->chipinfo.id);
256 }
257 }
258
259 @@ -164,8 +148,8 @@ void bcma_pmu_init(struct bcma_drv_cc *c
260 pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
261 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
262
263 - pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
264 - pmucap);
265 + bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
266 + cc->pmu.rev, pmucap);
267
268 if (cc->pmu.rev == 1)
269 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
270 @@ -174,12 +158,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
271 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
272 BCMA_CC_PMU_CTL_NOILPONW);
273
274 - if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
275 - pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
276 -
277 - bcma_pmu_pll_init(cc);
278 bcma_pmu_resources_init(cc);
279 - bcma_pmu_swreg_init(cc);
280 bcma_pmu_workarounds(cc);
281 }
282
283 @@ -188,23 +167,22 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_c
284 struct bcma_bus *bus = cc->core->bus;
285
286 switch (bus->chipinfo.id) {
287 - case 0x4716:
288 - case 0x4748:
289 - case 47162:
290 - case 0x4313:
291 - case 0x5357:
292 - case 0x4749:
293 - case 53572:
294 + case BCMA_CHIP_ID_BCM4716:
295 + case BCMA_CHIP_ID_BCM4748:
296 + case BCMA_CHIP_ID_BCM47162:
297 + case BCMA_CHIP_ID_BCM4313:
298 + case BCMA_CHIP_ID_BCM5357:
299 + case BCMA_CHIP_ID_BCM4749:
300 + case BCMA_CHIP_ID_BCM53572:
301 /* always 20Mhz */
302 return 20000 * 1000;
303 - case 0x5356:
304 - case 0x5300:
305 + case BCMA_CHIP_ID_BCM5356:
306 + case BCMA_CHIP_ID_BCM4706:
307 /* always 25Mhz */
308 return 25000 * 1000;
309 default:
310 - pr_warn("No ALP clock specified for %04X device, "
311 - "pmu rev. %d, using default %d Hz\n",
312 - bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
313 + bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
314 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
315 }
316 return BCMA_CC_PMU_ALP_CLOCK;
317 }
318 @@ -221,7 +199,8 @@ static u32 bcma_pmu_clock(struct bcma_dr
319
320 BUG_ON(!m || m > 4);
321
322 - if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
323 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
324 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
325 /* Detect failure in clock setting */
326 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
327 if (tmp & 0x40000)
328 @@ -247,33 +226,62 @@ static u32 bcma_pmu_clock(struct bcma_dr
329 return (fc / div) * 1000000;
330 }
331
332 +static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
333 +{
334 + u32 tmp, ndiv, p1div, p2div;
335 + u32 clock;
336 +
337 + BUG_ON(!m || m > 4);
338 +
339 + /* Get N, P1 and P2 dividers to determine CPU clock */
340 + tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
341 + ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
342 + >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
343 + p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
344 + >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
345 + p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
346 + >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
347 +
348 + tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
349 + if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
350 + /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
351 + clock = (25000000 / 4) * ndiv * p2div / p1div;
352 + else
353 + /* Fixed reference clock 25MHz and m = 2 */
354 + clock = (25000000 / 2) * ndiv * p2div / p1div;
355 +
356 + if (m == BCMA_CC_PMU5_MAINPLL_SSB)
357 + clock = clock / 4;
358 +
359 + return clock;
360 +}
361 +
362 /* query bus clock frequency for PMU-enabled chipcommon */
363 u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
364 {
365 struct bcma_bus *bus = cc->core->bus;
366
367 switch (bus->chipinfo.id) {
368 - case 0x4716:
369 - case 0x4748:
370 - case 47162:
371 + case BCMA_CHIP_ID_BCM4716:
372 + case BCMA_CHIP_ID_BCM4748:
373 + case BCMA_CHIP_ID_BCM47162:
374 return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
375 BCMA_CC_PMU5_MAINPLL_SSB);
376 - case 0x5356:
377 + case BCMA_CHIP_ID_BCM5356:
378 return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
379 BCMA_CC_PMU5_MAINPLL_SSB);
380 - case 0x5357:
381 - case 0x4749:
382 + case BCMA_CHIP_ID_BCM5357:
383 + case BCMA_CHIP_ID_BCM4749:
384 return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
385 BCMA_CC_PMU5_MAINPLL_SSB);
386 - case 0x5300:
387 - return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
388 - BCMA_CC_PMU5_MAINPLL_SSB);
389 - case 53572:
390 + case BCMA_CHIP_ID_BCM4706:
391 + return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
392 + BCMA_CC_PMU5_MAINPLL_SSB);
393 + case BCMA_CHIP_ID_BCM53572:
394 return 75000000;
395 default:
396 - pr_warn("No backplane clock specified for %04X device, "
397 - "pmu rev. %d, using default %d Hz\n",
398 - bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
399 + bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
400 + bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
401 }
402 return BCMA_CC_PMU_HT_CLOCK;
403 }
404 @@ -283,17 +291,21 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
405 {
406 struct bcma_bus *bus = cc->core->bus;
407
408 - if (bus->chipinfo.id == 53572)
409 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
410 return 300000000;
411
412 if (cc->pmu.rev >= 5) {
413 u32 pll;
414 switch (bus->chipinfo.id) {
415 - case 0x5356:
416 + case BCMA_CHIP_ID_BCM4706:
417 + return bcma_pmu_clock_bcm4706(cc,
418 + BCMA_CC_PMU4706_MAINPLL_PLL0,
419 + BCMA_CC_PMU5_MAINPLL_CPU);
420 + case BCMA_CHIP_ID_BCM5356:
421 pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
422 break;
423 - case 0x5357:
424 - case 0x4749:
425 + case BCMA_CHIP_ID_BCM5357:
426 + case BCMA_CHIP_ID_BCM4749:
427 pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
428 break;
429 default:
430 @@ -301,10 +313,188 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
431 break;
432 }
433
434 - /* TODO: if (bus->chipinfo.id == 0x5300)
435 - return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
436 return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
437 }
438
439 return bcma_pmu_get_clockcontrol(cc);
440 }
441 +
442 +static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
443 + u32 value)
444 +{
445 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
446 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
447 +}
448 +
449 +void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
450 +{
451 + u32 tmp = 0;
452 + u8 phypll_offset = 0;
453 + u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
454 + u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
455 + struct bcma_bus *bus = cc->core->bus;
456 +
457 + switch (bus->chipinfo.id) {
458 + case BCMA_CHIP_ID_BCM5357:
459 + case BCMA_CHIP_ID_BCM4749:
460 + case BCMA_CHIP_ID_BCM53572:
461 + /* 5357[ab]0, 43236[ab]0, and 6362b0 */
462 +
463 + /* BCM5357 needs to touch PLL1_PLLCTL[02],
464 + so offset PLL0_PLLCTL[02] by 6 */
465 + phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
466 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
467 + bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
468 +
469 + /* RMW only the P1 divider */
470 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
471 + BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
472 + tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
473 + tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
474 + tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
475 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
476 +
477 + /* RMW only the int feedback divider */
478 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
479 + BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
480 + tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
481 + tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
482 + tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
483 + bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
484 +
485 + tmp = 1 << 10;
486 + break;
487 +
488 + case BCMA_CHIP_ID_BCM4331:
489 + case BCMA_CHIP_ID_BCM43431:
490 + if (spuravoid == 2) {
491 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
492 + 0x11500014);
493 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
494 + 0x0FC00a08);
495 + } else if (spuravoid == 1) {
496 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
497 + 0x11500014);
498 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
499 + 0x0F600a08);
500 + } else {
501 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
502 + 0x11100014);
503 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
504 + 0x03000a08);
505 + }
506 + tmp = 1 << 10;
507 + break;
508 +
509 + case BCMA_CHIP_ID_BCM43224:
510 + case BCMA_CHIP_ID_BCM43225:
511 + case BCMA_CHIP_ID_BCM43421:
512 + if (spuravoid == 1) {
513 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
514 + 0x11500010);
515 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
516 + 0x000C0C06);
517 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
518 + 0x0F600a08);
519 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
520 + 0x00000000);
521 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
522 + 0x2001E920);
523 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
524 + 0x88888815);
525 + } else {
526 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
527 + 0x11100010);
528 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
529 + 0x000c0c06);
530 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
531 + 0x03000a08);
532 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
533 + 0x00000000);
534 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
535 + 0x200005c0);
536 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
537 + 0x88888815);
538 + }
539 + tmp = 1 << 10;
540 + break;
541 +
542 + case BCMA_CHIP_ID_BCM4716:
543 + case BCMA_CHIP_ID_BCM4748:
544 + case BCMA_CHIP_ID_BCM47162:
545 + if (spuravoid == 1) {
546 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
547 + 0x11500060);
548 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
549 + 0x080C0C06);
550 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
551 + 0x0F600000);
552 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
553 + 0x00000000);
554 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
555 + 0x2001E924);
556 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
557 + 0x88888815);
558 + } else {
559 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
560 + 0x11100060);
561 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
562 + 0x080c0c06);
563 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
564 + 0x03000000);
565 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
566 + 0x00000000);
567 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
568 + 0x200005c0);
569 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
570 + 0x88888815);
571 + }
572 +
573 + tmp = 3 << 9;
574 + break;
575 +
576 + case BCMA_CHIP_ID_BCM43227:
577 + case BCMA_CHIP_ID_BCM43228:
578 + case BCMA_CHIP_ID_BCM43428:
579 + /* LCNXN */
580 + /* PLL Settings for spur avoidance on/off mode,
581 + no on2 support for 43228A0 */
582 + if (spuravoid == 1) {
583 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
584 + 0x01100014);
585 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
586 + 0x040C0C06);
587 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
588 + 0x03140A08);
589 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
590 + 0x00333333);
591 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
592 + 0x202C2820);
593 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
594 + 0x88888815);
595 + } else {
596 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
597 + 0x11100014);
598 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
599 + 0x040c0c06);
600 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
601 + 0x03000a08);
602 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
603 + 0x00000000);
604 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
605 + 0x200005c0);
606 + bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
607 + 0x88888815);
608 + }
609 + tmp = 1 << 10;
610 + break;
611 + default:
612 + bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
613 + bus->chipinfo.id);
614 + break;
615 + }
616 +
617 + tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
618 + bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
619 +}
620 +EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
621 --- a/drivers/bcma/driver_mips.c
622 +++ b/drivers/bcma/driver_mips.c
623 @@ -22,15 +22,15 @@
624 /* The 47162a0 hangs when reading MIPS DMP registers registers */
625 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
626 {
627 - return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
628 - dev->id.id == BCMA_CORE_MIPS_74K;
629 + return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
630 + dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
631 }
632
633 /* The 5357b0 hangs when reading USB20H DMP registers */
634 static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
635 {
636 - return (dev->bus->chipinfo.id == 0x5357 ||
637 - dev->bus->chipinfo.id == 0x4749) &&
638 + return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
639 + dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
640 dev->bus->chipinfo.pkg == 11 &&
641 dev->id.id == BCMA_CORE_USB20_HOST;
642 }
643 @@ -143,8 +143,8 @@ static void bcma_core_mips_set_irq(struc
644 1 << irqflag);
645 }
646
647 - pr_info("set_irq: core 0x%04x, irq %d => %d\n",
648 - dev->id.id, oldirq + 2, irq + 2);
649 + bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
650 + dev->id.id, oldirq + 2, irq + 2);
651 }
652
653 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
654 @@ -173,7 +173,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
655 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
656 return bcma_pmu_get_clockcpu(&bus->drv_cc);
657
658 - pr_err("No PMU available, need this to get the cpu clock\n");
659 + bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
660 return 0;
661 }
662 EXPORT_SYMBOL(bcma_cpu_clock);
663 @@ -185,10 +185,10 @@ static void bcma_core_mips_flash_detect(
664 switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
665 case BCMA_CC_FLASHT_STSER:
666 case BCMA_CC_FLASHT_ATSER:
667 - pr_err("Serial flash not supported.\n");
668 + bcma_err(bus, "Serial flash not supported.\n");
669 break;
670 case BCMA_CC_FLASHT_PARA:
671 - pr_info("found parallel flash.\n");
672 + bcma_info(bus, "found parallel flash.\n");
673 bus->drv_cc.pflash.window = 0x1c000000;
674 bus->drv_cc.pflash.window_size = 0x02000000;
675
676 @@ -199,7 +199,7 @@ static void bcma_core_mips_flash_detect(
677 bus->drv_cc.pflash.buswidth = 2;
678 break;
679 default:
680 - pr_err("flash not supported.\n");
681 + bcma_err(bus, "flash not supported.\n");
682 }
683 }
684
685 @@ -209,7 +209,7 @@ void bcma_core_mips_init(struct bcma_drv
686 struct bcma_device *core;
687 bus = mcore->core->bus;
688
689 - pr_info("Initializing MIPS core...\n");
690 + bcma_info(bus, "Initializing MIPS core...\n");
691
692 if (!mcore->setup_done)
693 mcore->assigned_irqs = 1;
694 @@ -244,7 +244,7 @@ void bcma_core_mips_init(struct bcma_drv
695 break;
696 }
697 }
698 - pr_info("IRQ reconfiguration done\n");
699 + bcma_info(bus, "IRQ reconfiguration done\n");
700 bcma_core_mips_dump_irq(bus);
701
702 if (mcore->setup_done)
703 --- a/drivers/bcma/driver_pci.c
704 +++ b/drivers/bcma/driver_pci.c
705 @@ -2,8 +2,9 @@
706 * Broadcom specific AMBA
707 * PCI Core
708 *
709 - * Copyright 2005, Broadcom Corporation
710 + * Copyright 2005, 2011, Broadcom Corporation
711 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
712 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
713 *
714 * Licensed under the GNU/GPL. See COPYING for details.
715 */
716 @@ -16,40 +17,39 @@
717 * R/W ops.
718 **************************************************/
719
720 -static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
721 +u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address)
722 {
723 - pcicore_write32(pc, 0x130, address);
724 - pcicore_read32(pc, 0x130);
725 - return pcicore_read32(pc, 0x134);
726 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
727 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
728 + return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA);
729 }
730
731 -#if 0
732 static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data)
733 {
734 - pcicore_write32(pc, 0x130, address);
735 - pcicore_read32(pc, 0x130);
736 - pcicore_write32(pc, 0x134, data);
737 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address);
738 + pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR);
739 + pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
740 }
741 -#endif
742
743 static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
744 {
745 - const u16 mdio_control = 0x128;
746 - const u16 mdio_data = 0x12C;
747 u32 v;
748 int i;
749
750 - v = (1 << 30); /* Start of Transaction */
751 - v |= (1 << 28); /* Write Transaction */
752 - v |= (1 << 17); /* Turnaround */
753 - v |= (0x1F << 18);
754 + v = BCMA_CORE_PCI_MDIODATA_START;
755 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
756 + v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
757 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
758 + v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR <<
759 + BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
760 + v |= BCMA_CORE_PCI_MDIODATA_TA;
761 v |= (phy << 4);
762 - pcicore_write32(pc, mdio_data, v);
763 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
764
765 udelay(10);
766 for (i = 0; i < 200; i++) {
767 - v = pcicore_read32(pc, mdio_control);
768 - if (v & 0x100 /* Trans complete */)
769 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
770 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
771 break;
772 msleep(1);
773 }
774 @@ -57,79 +57,84 @@ static void bcma_pcie_mdio_set_phy(struc
775
776 static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
777 {
778 - const u16 mdio_control = 0x128;
779 - const u16 mdio_data = 0x12C;
780 int max_retries = 10;
781 u16 ret = 0;
782 u32 v;
783 int i;
784
785 - v = 0x80; /* Enable Preamble Sequence */
786 - v |= 0x2; /* MDIO Clock Divisor */
787 - pcicore_write32(pc, mdio_control, v);
788 + /* enable mdio access to SERDES */
789 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
790 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
791 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
792
793 if (pc->core->id.rev >= 10) {
794 max_retries = 200;
795 bcma_pcie_mdio_set_phy(pc, device);
796 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
797 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
798 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
799 + } else {
800 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
801 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
802 }
803
804 - v = (1 << 30); /* Start of Transaction */
805 - v |= (1 << 29); /* Read Transaction */
806 - v |= (1 << 17); /* Turnaround */
807 - if (pc->core->id.rev < 10)
808 - v |= (u32)device << 22;
809 - v |= (u32)address << 18;
810 - pcicore_write32(pc, mdio_data, v);
811 + v = BCMA_CORE_PCI_MDIODATA_START;
812 + v |= BCMA_CORE_PCI_MDIODATA_READ;
813 + v |= BCMA_CORE_PCI_MDIODATA_TA;
814 +
815 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
816 /* Wait for the device to complete the transaction */
817 udelay(10);
818 for (i = 0; i < max_retries; i++) {
819 - v = pcicore_read32(pc, mdio_control);
820 - if (v & 0x100 /* Trans complete */) {
821 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
822 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) {
823 udelay(10);
824 - ret = pcicore_read32(pc, mdio_data);
825 + ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
826 break;
827 }
828 msleep(1);
829 }
830 - pcicore_write32(pc, mdio_control, 0);
831 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
832 return ret;
833 }
834
835 static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
836 u8 address, u16 data)
837 {
838 - const u16 mdio_control = 0x128;
839 - const u16 mdio_data = 0x12C;
840 int max_retries = 10;
841 u32 v;
842 int i;
843
844 - v = 0x80; /* Enable Preamble Sequence */
845 - v |= 0x2; /* MDIO Clock Divisor */
846 - pcicore_write32(pc, mdio_control, v);
847 + /* enable mdio access to SERDES */
848 + v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN;
849 + v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL;
850 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v);
851
852 if (pc->core->id.rev >= 10) {
853 max_retries = 200;
854 bcma_pcie_mdio_set_phy(pc, device);
855 + v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR <<
856 + BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF);
857 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF);
858 + } else {
859 + v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD);
860 + v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD);
861 }
862
863 - v = (1 << 30); /* Start of Transaction */
864 - v |= (1 << 28); /* Write Transaction */
865 - v |= (1 << 17); /* Turnaround */
866 - if (pc->core->id.rev < 10)
867 - v |= (u32)device << 22;
868 - v |= (u32)address << 18;
869 + v = BCMA_CORE_PCI_MDIODATA_START;
870 + v |= BCMA_CORE_PCI_MDIODATA_WRITE;
871 + v |= BCMA_CORE_PCI_MDIODATA_TA;
872 v |= data;
873 - pcicore_write32(pc, mdio_data, v);
874 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v);
875 /* Wait for the device to complete the transaction */
876 udelay(10);
877 for (i = 0; i < max_retries; i++) {
878 - v = pcicore_read32(pc, mdio_control);
879 - if (v & 0x100 /* Trans complete */)
880 + v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
881 + if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
882 break;
883 msleep(1);
884 }
885 - pcicore_write32(pc, mdio_control, 0);
886 + pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
887 }
888
889 /**************************************************
890 @@ -138,88 +143,108 @@ static void bcma_pcie_mdio_write(struct
891
892 static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
893 {
894 - return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
895 + u32 tmp;
896 +
897 + tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG);
898 + if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT)
899 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE |
900 + BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY;
901 + else
902 + return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE;
903 }
904
905 static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc)
906 {
907 - const u8 serdes_pll_device = 0x1D;
908 - const u8 serdes_rx_device = 0x1F;
909 u16 tmp;
910
911 - bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
912 - bcma_pcicore_polarity_workaround(pc));
913 - tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
914 - if (tmp & 0x4000)
915 - bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
916 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX,
917 + BCMA_CORE_PCI_SERDES_RX_CTRL,
918 + bcma_pcicore_polarity_workaround(pc));
919 + tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
920 + BCMA_CORE_PCI_SERDES_PLL_CTRL);
921 + if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN)
922 + bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL,
923 + BCMA_CORE_PCI_SERDES_PLL_CTRL,
924 + tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN);
925 +}
926 +
927 +static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc)
928 +{
929 + struct bcma_device *core = pc->core;
930 + u16 val16, core_index;
931 + uint regoff;
932 +
933 + regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET);
934 + core_index = (u16)core->core_index;
935 +
936 + val16 = pcicore_read16(pc, regoff);
937 + if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT)
938 + != core_index) {
939 + val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) |
940 + (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK);
941 + pcicore_write16(pc, regoff, val16);
942 + }
943 +}
944 +
945 +/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
946 +/* Needs to happen when coming out of 'standby'/'hibernate' */
947 +static void bcma_core_pci_config_fixup(struct bcma_drv_pci *pc)
948 +{
949 + u16 val16;
950 + uint regoff;
951 +
952 + regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_MISC_CONFIG);
953 +
954 + val16 = pcicore_read16(pc, regoff);
955 +
956 + if (!(val16 & BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST)) {
957 + val16 |= BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST;
958 + pcicore_write16(pc, regoff, val16);
959 + }
960 }
961
962 /**************************************************
963 * Init.
964 **************************************************/
965
966 -static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
967 +static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc)
968 {
969 + bcma_core_pci_fixcfg(pc);
970 bcma_pcicore_serdes_workaround(pc);
971 + bcma_core_pci_config_fixup(pc);
972 }
973
974 -static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
975 -{
976 - struct bcma_bus *bus = pc->core->bus;
977 - u16 chipid_top;
978 -
979 - chipid_top = (bus->chipinfo.id & 0xFF00);
980 - if (chipid_top != 0x4700 &&
981 - chipid_top != 0x5300)
982 - return false;
983 -
984 -#ifdef CONFIG_SSB_DRIVER_PCICORE
985 - if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
986 - return false;
987 -#endif /* CONFIG_SSB_DRIVER_PCICORE */
988 -
989 -#if 0
990 - /* TODO: on BCMA we use address from EROM instead of magic formula */
991 - u32 tmp;
992 - return !mips_busprobe32(tmp, (bus->mmio +
993 - (pc->core->core_index * BCMA_CORE_SIZE)));
994 -#endif
995 -
996 - return true;
997 -}
998 -
999 -void bcma_core_pci_init(struct bcma_drv_pci *pc)
1000 +void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
1001 {
1002 if (pc->setup_done)
1003 return;
1004
1005 - if (bcma_core_pci_is_in_hostmode(pc)) {
1006 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
1007 + pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
1008 + if (pc->hostmode)
1009 bcma_core_pci_hostmode_init(pc);
1010 -#else
1011 - pr_err("Driver compiled without support for hostmode PCI\n");
1012 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
1013 - } else {
1014 - bcma_core_pci_clientmode_init(pc);
1015 - }
1016
1017 - pc->setup_done = true;
1018 + if (!pc->hostmode)
1019 + bcma_core_pci_clientmode_init(pc);
1020 }
1021
1022 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
1023 bool enable)
1024 {
1025 - struct pci_dev *pdev = pc->core->bus->host_pci;
1026 + struct pci_dev *pdev;
1027 u32 coremask, tmp;
1028 int err = 0;
1029
1030 - if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
1031 + if (!pc || core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
1032 /* This bcma device is not on a PCI host-bus. So the IRQs are
1033 * not routed through the PCI core.
1034 * So we must not enable routing through the PCI core. */
1035 goto out;
1036 }
1037
1038 + pdev = pc->core->bus->host_pci;
1039 +
1040 err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
1041 if (err)
1042 goto out;
1043 @@ -236,3 +261,17 @@ out:
1044 return err;
1045 }
1046 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
1047 +
1048 +void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
1049 +{
1050 + u32 w;
1051 +
1052 + w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
1053 + if (extend)
1054 + w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND;
1055 + else
1056 + w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND;
1057 + bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
1058 + bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
1059 +}
1060 +EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
1061 --- a/drivers/bcma/driver_pci_host.c
1062 +++ b/drivers/bcma/driver_pci_host.c
1063 @@ -2,13 +2,592 @@
1064 * Broadcom specific AMBA
1065 * PCI Core in hostmode
1066 *
1067 + * Copyright 2005 - 2011, Broadcom Corporation
1068 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1069 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
1070 + *
1071 * Licensed under the GNU/GPL. See COPYING for details.
1072 */
1073
1074 #include "bcma_private.h"
1075 +#include <linux/pci.h>
1076 +#include <linux/export.h>
1077 #include <linux/bcma/bcma.h>
1078 +#include <asm/paccess.h>
1079 +
1080 +/* Probe a 32bit value on the bus and catch bus exceptions.
1081 + * Returns nonzero on a bus exception.
1082 + * This is MIPS specific */
1083 +#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
1084 +
1085 +/* Assume one-hot slot wiring */
1086 +#define BCMA_PCI_SLOT_MAX 16
1087 +#define PCI_CONFIG_SPACE_SIZE 256
1088 +
1089 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
1090 +{
1091 + struct bcma_bus *bus = pc->core->bus;
1092 + u16 chipid_top;
1093 + u32 tmp;
1094 +
1095 + chipid_top = (bus->chipinfo.id & 0xFF00);
1096 + if (chipid_top != 0x4700 &&
1097 + chipid_top != 0x5300)
1098 + return false;
1099 +
1100 + if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
1101 + bcma_info(bus, "This PCI core is disabled and not working\n");
1102 + return false;
1103 + }
1104 +
1105 + bcma_core_enable(pc->core, 0);
1106 +
1107 + return !mips_busprobe32(tmp, pc->core->io_addr);
1108 +}
1109 +
1110 +static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
1111 +{
1112 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
1113 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
1114 + return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
1115 +}
1116 +
1117 +static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
1118 + u32 data)
1119 +{
1120 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
1121 + pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
1122 + pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
1123 +}
1124 +
1125 +static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
1126 + unsigned int func, unsigned int off)
1127 +{
1128 + u32 addr = 0;
1129 +
1130 + /* Issue config commands only when the data link is up (atleast
1131 + * one external pcie device is present).
1132 + */
1133 + if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
1134 + & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
1135 + goto out;
1136 +
1137 + /* Type 0 transaction */
1138 + /* Slide the PCI window to the appropriate slot */
1139 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
1140 + /* Calculate the address */
1141 + addr = pc->host_controller->host_cfg_addr;
1142 + addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
1143 + addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
1144 + addr |= (off & ~3);
1145 +
1146 +out:
1147 + return addr;
1148 +}
1149
1150 -void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
1151 +static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
1152 + unsigned int func, unsigned int off,
1153 + void *buf, int len)
1154 {
1155 - pr_err("No support for PCI core in hostmode yet\n");
1156 + int err = -EINVAL;
1157 + u32 addr, val;
1158 + void __iomem *mmio = 0;
1159 +
1160 + WARN_ON(!pc->hostmode);
1161 + if (unlikely(len != 1 && len != 2 && len != 4))
1162 + goto out;
1163 + if (dev == 0) {
1164 + /* we support only two functions on device 0 */
1165 + if (func > 1)
1166 + return -EINVAL;
1167 +
1168 + /* accesses to config registers with offsets >= 256
1169 + * requires indirect access.
1170 + */
1171 + if (off >= PCI_CONFIG_SPACE_SIZE) {
1172 + addr = (func << 12);
1173 + addr |= (off & 0x0FFF);
1174 + val = bcma_pcie_read_config(pc, addr);
1175 + } else {
1176 + addr = BCMA_CORE_PCI_PCICFG0;
1177 + addr |= (func << 8);
1178 + addr |= (off & 0xfc);
1179 + val = pcicore_read32(pc, addr);
1180 + }
1181 + } else {
1182 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
1183 + if (unlikely(!addr))
1184 + goto out;
1185 + err = -ENOMEM;
1186 + mmio = ioremap_nocache(addr, sizeof(val));
1187 + if (!mmio)
1188 + goto out;
1189 +
1190 + if (mips_busprobe32(val, mmio)) {
1191 + val = 0xffffffff;
1192 + goto unmap;
1193 + }
1194 +
1195 + val = readl(mmio);
1196 + }
1197 + val >>= (8 * (off & 3));
1198 +
1199 + switch (len) {
1200 + case 1:
1201 + *((u8 *)buf) = (u8)val;
1202 + break;
1203 + case 2:
1204 + *((u16 *)buf) = (u16)val;
1205 + break;
1206 + case 4:
1207 + *((u32 *)buf) = (u32)val;
1208 + break;
1209 + }
1210 + err = 0;
1211 +unmap:
1212 + if (mmio)
1213 + iounmap(mmio);
1214 +out:
1215 + return err;
1216 +}
1217 +
1218 +static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
1219 + unsigned int func, unsigned int off,
1220 + const void *buf, int len)
1221 +{
1222 + int err = -EINVAL;
1223 + u32 addr = 0, val = 0;
1224 + void __iomem *mmio = 0;
1225 + u16 chipid = pc->core->bus->chipinfo.id;
1226 +
1227 + WARN_ON(!pc->hostmode);
1228 + if (unlikely(len != 1 && len != 2 && len != 4))
1229 + goto out;
1230 + if (dev == 0) {
1231 + /* accesses to config registers with offsets >= 256
1232 + * requires indirect access.
1233 + */
1234 + if (off < PCI_CONFIG_SPACE_SIZE) {
1235 + addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
1236 + addr |= (func << 8);
1237 + addr |= (off & 0xfc);
1238 + mmio = ioremap_nocache(addr, sizeof(val));
1239 + if (!mmio)
1240 + goto out;
1241 + }
1242 + } else {
1243 + addr = bcma_get_cfgspace_addr(pc, dev, func, off);
1244 + if (unlikely(!addr))
1245 + goto out;
1246 + err = -ENOMEM;
1247 + mmio = ioremap_nocache(addr, sizeof(val));
1248 + if (!mmio)
1249 + goto out;
1250 +
1251 + if (mips_busprobe32(val, mmio)) {
1252 + val = 0xffffffff;
1253 + goto unmap;
1254 + }
1255 + }
1256 +
1257 + switch (len) {
1258 + case 1:
1259 + val = readl(mmio);
1260 + val &= ~(0xFF << (8 * (off & 3)));
1261 + val |= *((const u8 *)buf) << (8 * (off & 3));
1262 + break;
1263 + case 2:
1264 + val = readl(mmio);
1265 + val &= ~(0xFFFF << (8 * (off & 3)));
1266 + val |= *((const u16 *)buf) << (8 * (off & 3));
1267 + break;
1268 + case 4:
1269 + val = *((const u32 *)buf);
1270 + break;
1271 + }
1272 + if (dev == 0 && !addr) {
1273 + /* accesses to config registers with offsets >= 256
1274 + * requires indirect access.
1275 + */
1276 + addr = (func << 12);
1277 + addr |= (off & 0x0FFF);
1278 + bcma_pcie_write_config(pc, addr, val);
1279 + } else {
1280 + writel(val, mmio);
1281 +
1282 + if (chipid == BCMA_CHIP_ID_BCM4716 ||
1283 + chipid == BCMA_CHIP_ID_BCM4748)
1284 + readl(mmio);
1285 + }
1286 +
1287 + err = 0;
1288 +unmap:
1289 + if (mmio)
1290 + iounmap(mmio);
1291 +out:
1292 + return err;
1293 +}
1294 +
1295 +static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
1296 + unsigned int devfn,
1297 + int reg, int size, u32 *val)
1298 +{
1299 + unsigned long flags;
1300 + int err;
1301 + struct bcma_drv_pci *pc;
1302 + struct bcma_drv_pci_host *pc_host;
1303 +
1304 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
1305 + pc = pc_host->pdev;
1306 +
1307 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
1308 + err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
1309 + PCI_FUNC(devfn), reg, val, size);
1310 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
1311 +
1312 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
1313 +}
1314 +
1315 +static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
1316 + unsigned int devfn,
1317 + int reg, int size, u32 val)
1318 +{
1319 + unsigned long flags;
1320 + int err;
1321 + struct bcma_drv_pci *pc;
1322 + struct bcma_drv_pci_host *pc_host;
1323 +
1324 + pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
1325 + pc = pc_host->pdev;
1326 +
1327 + spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
1328 + err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
1329 + PCI_FUNC(devfn), reg, &val, size);
1330 + spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
1331 +
1332 + return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
1333 +}
1334 +
1335 +/* return cap_offset if requested capability exists in the PCI config space */
1336 +static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
1337 + unsigned int dev,
1338 + unsigned int func, u8 req_cap_id,
1339 + unsigned char *buf, u32 *buflen)
1340 +{
1341 + u8 cap_id;
1342 + u8 cap_ptr = 0;
1343 + u32 bufsize;
1344 + u8 byte_val;
1345 +
1346 + /* check for Header type 0 */
1347 + bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
1348 + sizeof(u8));
1349 + if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
1350 + return cap_ptr;
1351 +
1352 + /* check if the capability pointer field exists */
1353 + bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
1354 + sizeof(u8));
1355 + if (!(byte_val & PCI_STATUS_CAP_LIST))
1356 + return cap_ptr;
1357 +
1358 + /* check if the capability pointer is 0x00 */
1359 + bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
1360 + sizeof(u8));
1361 + if (cap_ptr == 0x00)
1362 + return cap_ptr;
1363 +
1364 + /* loop thr'u the capability list and see if the requested capabilty
1365 + * exists */
1366 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
1367 + while (cap_id != req_cap_id) {
1368 + bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
1369 + sizeof(u8));
1370 + if (cap_ptr == 0x00)
1371 + return cap_ptr;
1372 + bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
1373 + sizeof(u8));
1374 + }
1375 +
1376 + /* found the caller requested capability */
1377 + if ((buf != NULL) && (buflen != NULL)) {
1378 + u8 cap_data;
1379 +
1380 + bufsize = *buflen;
1381 + if (!bufsize)
1382 + return cap_ptr;
1383 +
1384 + *buflen = 0;
1385 +
1386 + /* copy the cpability data excluding cap ID and next ptr */
1387 + cap_data = cap_ptr + 2;
1388 + if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
1389 + bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
1390 + *buflen = bufsize;
1391 + while (bufsize--) {
1392 + bcma_extpci_read_config(pc, dev, func, cap_data, buf,
1393 + sizeof(u8));
1394 + cap_data++;
1395 + buf++;
1396 + }
1397 + }
1398 +
1399 + return cap_ptr;
1400 +}
1401 +
1402 +/* If the root port is capable of returning Config Request
1403 + * Retry Status (CRS) Completion Status to software then
1404 + * enable the feature.
1405 + */
1406 +static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
1407 +{
1408 + struct bcma_bus *bus = pc->core->bus;
1409 + u8 cap_ptr, root_ctrl, root_cap, dev;
1410 + u16 val16;
1411 + int i;
1412 +
1413 + cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
1414 + NULL);
1415 + root_cap = cap_ptr + PCI_EXP_RTCAP;
1416 + bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
1417 + if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
1418 + /* Enable CRS software visibility */
1419 + root_ctrl = cap_ptr + PCI_EXP_RTCTL;
1420 + val16 = PCI_EXP_RTCTL_CRSSVE;
1421 + bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
1422 + sizeof(u16));
1423 +
1424 + /* Initiate a configuration request to read the vendor id
1425 + * field of the device function's config space header after
1426 + * 100 ms wait time from the end of Reset. If the device is
1427 + * not done with its internal initialization, it must at
1428 + * least return a completion TLP, with a completion status
1429 + * of "Configuration Request Retry Status (CRS)". The root
1430 + * complex must complete the request to the host by returning
1431 + * a read-data value of 0001h for the Vendor ID field and
1432 + * all 1s for any additional bytes included in the request.
1433 + * Poll using the config reads for max wait time of 1 sec or
1434 + * until we receive the successful completion status. Repeat
1435 + * the procedure for all the devices.
1436 + */
1437 + for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
1438 + for (i = 0; i < 100000; i++) {
1439 + bcma_extpci_read_config(pc, dev, 0,
1440 + PCI_VENDOR_ID, &val16,
1441 + sizeof(val16));
1442 + if (val16 != 0x1)
1443 + break;
1444 + udelay(10);
1445 + }
1446 + if (val16 == 0x1)
1447 + bcma_err(bus, "PCI: Broken device in slot %d\n",
1448 + dev);
1449 + }
1450 + }
1451 +}
1452 +
1453 +void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
1454 +{
1455 + struct bcma_bus *bus = pc->core->bus;
1456 + struct bcma_drv_pci_host *pc_host;
1457 + u32 tmp;
1458 + u32 pci_membase_1G;
1459 + unsigned long io_map_base;
1460 +
1461 + bcma_info(bus, "PCIEcore in host mode found\n");
1462 +
1463 + pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
1464 + if (!pc_host) {
1465 + bcma_err(bus, "can not allocate memory");
1466 + return;
1467 + }
1468 +
1469 + pc->host_controller = pc_host;
1470 + pc_host->pci_controller.io_resource = &pc_host->io_resource;
1471 + pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
1472 + pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
1473 + pc_host->pdev = pc;
1474 +
1475 + pci_membase_1G = BCMA_SOC_PCI_DMA;
1476 + pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
1477 +
1478 + pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
1479 + pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
1480 +
1481 + pc_host->mem_resource.name = "BCMA PCIcore external memory",
1482 + pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
1483 + pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
1484 + pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
1485 +
1486 + pc_host->io_resource.name = "BCMA PCIcore external I/O",
1487 + pc_host->io_resource.start = 0x100;
1488 + pc_host->io_resource.end = 0x7FF;
1489 + pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
1490 +
1491 + /* Reset RC */
1492 + udelay(3000);
1493 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
1494 + udelay(1000);
1495 + pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
1496 + BCMA_CORE_PCI_CTL_RST_OE);
1497 +
1498 + /* 64 MB I/O access window. On 4716, use
1499 + * sbtopcie0 to access the device registers. We
1500 + * can't use address match 2 (1 GB window) region
1501 + * as mips can't generate 64-bit address on the
1502 + * backplane.
1503 + */
1504 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 ||
1505 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
1506 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1507 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1508 + BCMA_SOC_PCI_MEM_SZ - 1;
1509 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1510 + BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
1511 + } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
1512 + tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
1513 + tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
1514 + tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
1515 + if (pc->core->core_unit == 0) {
1516 + pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
1517 + pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
1518 + BCMA_SOC_PCI_MEM_SZ - 1;
1519 + pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
1520 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1521 + tmp | BCMA_SOC_PCI_MEM);
1522 + } else if (pc->core->core_unit == 1) {
1523 + pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
1524 + pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
1525 + BCMA_SOC_PCI_MEM_SZ - 1;
1526 + pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
1527 + pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
1528 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1529 + tmp | BCMA_SOC_PCI1_MEM);
1530 + }
1531 + } else
1532 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
1533 + BCMA_CORE_PCI_SBTOPCI_IO);
1534 +
1535 + /* 64 MB configuration access window */
1536 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
1537 +
1538 + /* 1 GB memory access window */
1539 + pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
1540 + BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
1541 +
1542 +
1543 + /* As per PCI Express Base Spec 1.1 we need to wait for
1544 + * at least 100 ms from the end of a reset (cold/warm/hot)
1545 + * before issuing configuration requests to PCI Express
1546 + * devices.
1547 + */
1548 + udelay(100000);
1549 +
1550 + bcma_core_pci_enable_crs(pc);
1551 +
1552 + /* Enable PCI bridge BAR0 memory & master access */
1553 + tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
1554 + bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
1555 +
1556 + /* Enable PCI interrupts */
1557 + pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
1558 +
1559 + /* Ok, ready to run, register it to the system.
1560 + * The following needs change, if we want to port hostmode
1561 + * to non-MIPS platform. */
1562 + io_map_base = (unsigned long)ioremap_nocache(pc_host->mem_resource.start,
1563 + resource_size(&pc_host->mem_resource));
1564 + pc_host->pci_controller.io_map_base = io_map_base;
1565 + set_io_port_base(pc_host->pci_controller.io_map_base);
1566 + /* Give some time to the PCI controller to configure itself with the new
1567 + * values. Not waiting at this point causes crashes of the machine. */
1568 + mdelay(10);
1569 + register_pci_controller(&pc_host->pci_controller);
1570 + return;
1571 +}
1572 +
1573 +/* Early PCI fixup for a device on the PCI-core bridge. */
1574 +static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
1575 +{
1576 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1577 + /* This is not a device on the PCI-core bridge. */
1578 + return;
1579 + }
1580 + if (PCI_SLOT(dev->devfn) != 0)
1581 + return;
1582 +
1583 + pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
1584 +
1585 + /* Enable PCI bridge bus mastering and memory space */
1586 + pci_set_master(dev);
1587 + if (pcibios_enable_device(dev, ~0) < 0) {
1588 + pr_err("PCI: BCMA bridge enable failed\n");
1589 + return;
1590 + }
1591 +
1592 + /* Enable PCI bridge BAR1 prefetch and burst */
1593 + pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
1594 +}
1595 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
1596 +
1597 +/* Early PCI fixup for all PCI-cores to set the correct memory address. */
1598 +static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
1599 +{
1600 + struct resource *res;
1601 + int pos;
1602 +
1603 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1604 + /* This is not a device on the PCI-core bridge. */
1605 + return;
1606 + }
1607 + if (PCI_SLOT(dev->devfn) == 0)
1608 + return;
1609 +
1610 + pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
1611 +
1612 + for (pos = 0; pos < 6; pos++) {
1613 + res = &dev->resource[pos];
1614 + if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
1615 + pci_assign_resource(dev, pos);
1616 + }
1617 +}
1618 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
1619 +
1620 +/* This function is called when doing a pci_enable_device().
1621 + * We must first check if the device is a device on the PCI-core bridge. */
1622 +int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
1623 +{
1624 + struct bcma_drv_pci_host *pc_host;
1625 +
1626 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1627 + /* This is not a device on the PCI-core bridge. */
1628 + return -ENODEV;
1629 + }
1630 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
1631 + pci_ops);
1632 +
1633 + pr_info("PCI: Fixing up device %s\n", pci_name(dev));
1634 +
1635 + /* Fix up interrupt lines */
1636 + dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
1637 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1638 +
1639 + return 0;
1640 +}
1641 +EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
1642 +
1643 +/* PCI device IRQ mapping. */
1644 +int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
1645 +{
1646 + struct bcma_drv_pci_host *pc_host;
1647 +
1648 + if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
1649 + /* This is not a device on the PCI-core bridge. */
1650 + return -ENODEV;
1651 + }
1652 +
1653 + pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
1654 + pci_ops);
1655 + return bcma_core_mips_irq(pc_host->pdev->core) + 2;
1656 }
1657 +EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
1658 --- a/drivers/bcma/host_pci.c
1659 +++ b/drivers/bcma/host_pci.c
1660 @@ -18,7 +18,7 @@ static void bcma_host_pci_switch_core(st
1661 pci_write_config_dword(core->bus->host_pci, BCMA_PCI_BAR0_WIN2,
1662 core->wrap);
1663 core->bus->mapped_core = core;
1664 - pr_debug("Switched to core: 0x%X\n", core->id.id);
1665 + bcma_debug(core->bus, "Switched to core: 0x%X\n", core->id.id);
1666 }
1667
1668 /* Provides access to the requested core. Returns base offset that has to be
1669 @@ -154,8 +154,8 @@ const struct bcma_host_ops bcma_host_pci
1670 .awrite32 = bcma_host_pci_awrite32,
1671 };
1672
1673 -static int bcma_host_pci_probe(struct pci_dev *dev,
1674 - const struct pci_device_id *id)
1675 +static int __devinit bcma_host_pci_probe(struct pci_dev *dev,
1676 + const struct pci_device_id *id)
1677 {
1678 struct bcma_bus *bus;
1679 int err = -ENOMEM;
1680 @@ -188,7 +188,7 @@ static int bcma_host_pci_probe(struct pc
1681
1682 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
1683 if (!pci_is_pcie(dev))
1684 - pr_err("PCI card detected, report problems.\n");
1685 + bcma_err(bus, "PCI card detected, report problems.\n");
1686
1687 /* Map MMIO */
1688 err = -ENOMEM;
1689 @@ -201,6 +201,9 @@ static int bcma_host_pci_probe(struct pc
1690 bus->hosttype = BCMA_HOSTTYPE_PCI;
1691 bus->ops = &bcma_host_pci_ops;
1692
1693 + bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
1694 + bus->boardinfo.type = bus->host_pci->subsystem_device;
1695 +
1696 /* Register */
1697 err = bcma_bus_register(bus);
1698 if (err)
1699 @@ -222,7 +225,7 @@ err_kfree_bus:
1700 return err;
1701 }
1702
1703 -static void bcma_host_pci_remove(struct pci_dev *dev)
1704 +static void __devexit bcma_host_pci_remove(struct pci_dev *dev)
1705 {
1706 struct bcma_bus *bus = pci_get_drvdata(dev);
1707
1708 @@ -265,6 +268,7 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
1709
1710 static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
1711 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
1712 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
1713 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
1714 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
1715 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
1716 @@ -277,7 +281,7 @@ static struct pci_driver bcma_pci_bridge
1717 .name = "bcma-pci-bridge",
1718 .id_table = bcma_pci_bridge_tbl,
1719 .probe = bcma_host_pci_probe,
1720 - .remove = bcma_host_pci_remove,
1721 + .remove = __devexit_p(bcma_host_pci_remove),
1722 .driver.pm = BCMA_PM_OPS,
1723 };
1724
1725 --- a/drivers/bcma/main.c
1726 +++ b/drivers/bcma/main.c
1727 @@ -13,6 +13,12 @@
1728 MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
1729 MODULE_LICENSE("GPL");
1730
1731 +/* contains the number the next bus should get. */
1732 +static unsigned int bcma_bus_next_num = 0;
1733 +
1734 +/* bcma_buses_mutex locks the bcma_bus_next_num */
1735 +static DEFINE_MUTEX(bcma_buses_mutex);
1736 +
1737 static int bcma_bus_match(struct device *dev, struct device_driver *drv);
1738 static int bcma_device_probe(struct device *dev);
1739 static int bcma_device_remove(struct device *dev);
1740 @@ -55,7 +61,7 @@ static struct bus_type bcma_bus_type = {
1741 .dev_attrs = bcma_device_attrs,
1742 };
1743
1744 -static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
1745 +struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
1746 {
1747 struct bcma_device *core;
1748
1749 @@ -65,6 +71,7 @@ static struct bcma_device *bcma_find_cor
1750 }
1751 return NULL;
1752 }
1753 +EXPORT_SYMBOL_GPL(bcma_find_core);
1754
1755 static void bcma_release_core_dev(struct device *dev)
1756 {
1757 @@ -93,7 +100,7 @@ static int bcma_register_cores(struct bc
1758
1759 core->dev.release = bcma_release_core_dev;
1760 core->dev.bus = &bcma_bus_type;
1761 - dev_set_name(&core->dev, "bcma%d:%d", 0/*bus->num*/, dev_id);
1762 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
1763
1764 switch (bus->hosttype) {
1765 case BCMA_HOSTTYPE_PCI:
1766 @@ -111,8 +118,9 @@ static int bcma_register_cores(struct bc
1767
1768 err = device_register(&core->dev);
1769 if (err) {
1770 - pr_err("Could not register dev for core 0x%03X\n",
1771 - core->id.id);
1772 + bcma_err(bus,
1773 + "Could not register dev for core 0x%03X\n",
1774 + core->id.id);
1775 continue;
1776 }
1777 core->dev_registered = true;
1778 @@ -132,15 +140,19 @@ static void bcma_unregister_cores(struct
1779 }
1780 }
1781
1782 -int bcma_bus_register(struct bcma_bus *bus)
1783 +int __devinit bcma_bus_register(struct bcma_bus *bus)
1784 {
1785 int err;
1786 struct bcma_device *core;
1787
1788 + mutex_lock(&bcma_buses_mutex);
1789 + bus->num = bcma_bus_next_num++;
1790 + mutex_unlock(&bcma_buses_mutex);
1791 +
1792 /* Scan for devices (cores) */
1793 err = bcma_bus_scan(bus);
1794 if (err) {
1795 - pr_err("Failed to scan: %d\n", err);
1796 + bcma_err(bus, "Failed to scan: %d\n", err);
1797 return -1;
1798 }
1799
1800 @@ -168,14 +180,14 @@ int bcma_bus_register(struct bcma_bus *b
1801 /* Try to get SPROM */
1802 err = bcma_sprom_get(bus);
1803 if (err == -ENOENT) {
1804 - pr_err("No SPROM available\n");
1805 + bcma_err(bus, "No SPROM available\n");
1806 } else if (err)
1807 - pr_err("Failed to get SPROM: %d\n", err);
1808 + bcma_err(bus, "Failed to get SPROM: %d\n", err);
1809
1810 /* Register found cores */
1811 bcma_register_cores(bus);
1812
1813 - pr_info("Bus registered\n");
1814 + bcma_info(bus, "Bus registered\n");
1815
1816 return 0;
1817 }
1818 @@ -203,7 +215,7 @@ int __init bcma_bus_early_register(struc
1819 /* Scan for chip common core */
1820 err = bcma_bus_scan_early(bus, &match, core_cc);
1821 if (err) {
1822 - pr_err("Failed to scan for common core: %d\n", err);
1823 + bcma_err(bus, "Failed to scan for common core: %d\n", err);
1824 return -1;
1825 }
1826
1827 @@ -215,7 +227,7 @@ int __init bcma_bus_early_register(struc
1828 /* Scan for mips core */
1829 err = bcma_bus_scan_early(bus, &match, core_mips);
1830 if (err) {
1831 - pr_err("Failed to scan for mips core: %d\n", err);
1832 + bcma_err(bus, "Failed to scan for mips core: %d\n", err);
1833 return -1;
1834 }
1835
1836 @@ -233,7 +245,7 @@ int __init bcma_bus_early_register(struc
1837 bcma_core_mips_init(&bus->drv_mips);
1838 }
1839
1840 - pr_info("Early bus registered\n");
1841 + bcma_info(bus, "Early bus registered\n");
1842
1843 return 0;
1844 }
1845 --- a/drivers/bcma/scan.c
1846 +++ b/drivers/bcma/scan.c
1847 @@ -19,15 +19,27 @@ struct bcma_device_id_name {
1848 u16 id;
1849 const char *name;
1850 };
1851 -struct bcma_device_id_name bcma_device_names[] = {
1852 +
1853 +static const struct bcma_device_id_name bcma_arm_device_names[] = {
1854 + { BCMA_CORE_ARM_1176, "ARM 1176" },
1855 + { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
1856 + { BCMA_CORE_ARM_CM3, "ARM CM3" },
1857 +};
1858 +
1859 +static const struct bcma_device_id_name bcma_bcm_device_names[] = {
1860 { BCMA_CORE_OOB_ROUTER, "OOB Router" },
1861 + { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
1862 + { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
1863 + { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
1864 + { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
1865 + { BCMA_CORE_ALTA, "ALTA (I2S)" },
1866 + { BCMA_CORE_4706_MAC_GBIT_COMMON, "BCM4706 GBit MAC Common" },
1867 { BCMA_CORE_INVALID, "Invalid" },
1868 { BCMA_CORE_CHIPCOMMON, "ChipCommon" },
1869 { BCMA_CORE_ILINE20, "ILine 20" },
1870 { BCMA_CORE_SRAM, "SRAM" },
1871 { BCMA_CORE_SDRAM, "SDRAM" },
1872 { BCMA_CORE_PCI, "PCI" },
1873 - { BCMA_CORE_MIPS, "MIPS" },
1874 { BCMA_CORE_ETHERNET, "Fast Ethernet" },
1875 { BCMA_CORE_V90, "V90" },
1876 { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
1877 @@ -44,7 +56,6 @@ struct bcma_device_id_name bcma_device_n
1878 { BCMA_CORE_PHY_A, "PHY A" },
1879 { BCMA_CORE_PHY_B, "PHY B" },
1880 { BCMA_CORE_PHY_G, "PHY G" },
1881 - { BCMA_CORE_MIPS_3302, "MIPS 3302" },
1882 { BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
1883 { BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
1884 { BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
1885 @@ -58,15 +69,11 @@ struct bcma_device_id_name bcma_device_n
1886 { BCMA_CORE_PHY_N, "PHY N" },
1887 { BCMA_CORE_SRAM_CTL, "SRAM Controller" },
1888 { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
1889 - { BCMA_CORE_ARM_1176, "ARM 1176" },
1890 - { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
1891 { BCMA_CORE_PHY_LP, "PHY LP" },
1892 { BCMA_CORE_PMU, "PMU" },
1893 { BCMA_CORE_PHY_SSN, "PHY SSN" },
1894 { BCMA_CORE_SDIO_DEV, "SDIO Device" },
1895 - { BCMA_CORE_ARM_CM3, "ARM CM3" },
1896 { BCMA_CORE_PHY_HT, "PHY HT" },
1897 - { BCMA_CORE_MIPS_74K, "MIPS 74K" },
1898 { BCMA_CORE_MAC_GBIT, "GBit MAC" },
1899 { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
1900 { BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
1901 @@ -79,16 +86,41 @@ struct bcma_device_id_name bcma_device_n
1902 { BCMA_CORE_SHIM, "SHIM" },
1903 { BCMA_CORE_DEFAULT, "Default" },
1904 };
1905 -const char *bcma_device_name(struct bcma_device_id *id)
1906 +
1907 +static const struct bcma_device_id_name bcma_mips_device_names[] = {
1908 + { BCMA_CORE_MIPS, "MIPS" },
1909 + { BCMA_CORE_MIPS_3302, "MIPS 3302" },
1910 + { BCMA_CORE_MIPS_74K, "MIPS 74K" },
1911 +};
1912 +
1913 +static const char *bcma_device_name(const struct bcma_device_id *id)
1914 {
1915 - int i;
1916 + const struct bcma_device_id_name *names;
1917 + int size, i;
1918
1919 - if (id->manuf == BCMA_MANUF_BCM) {
1920 - for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
1921 - if (bcma_device_names[i].id == id->id)
1922 - return bcma_device_names[i].name;
1923 - }
1924 + /* search manufacturer specific names */
1925 + switch (id->manuf) {
1926 + case BCMA_MANUF_ARM:
1927 + names = bcma_arm_device_names;
1928 + size = ARRAY_SIZE(bcma_arm_device_names);
1929 + break;
1930 + case BCMA_MANUF_BCM:
1931 + names = bcma_bcm_device_names;
1932 + size = ARRAY_SIZE(bcma_bcm_device_names);
1933 + break;
1934 + case BCMA_MANUF_MIPS:
1935 + names = bcma_mips_device_names;
1936 + size = ARRAY_SIZE(bcma_mips_device_names);
1937 + break;
1938 + default:
1939 + return "UNKNOWN";
1940 + }
1941 +
1942 + for (i = 0; i < size; i++) {
1943 + if (names[i].id == id->id)
1944 + return names[i].name;
1945 }
1946 +
1947 return "UNKNOWN";
1948 }
1949
1950 @@ -212,6 +244,17 @@ static struct bcma_device *bcma_find_cor
1951 return NULL;
1952 }
1953
1954 +static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid)
1955 +{
1956 + struct bcma_device *core;
1957 +
1958 + list_for_each_entry_reverse(core, &bus->cores, list) {
1959 + if (core->id.id == coreid)
1960 + return core;
1961 + }
1962 + return NULL;
1963 +}
1964 +
1965 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
1966 struct bcma_device_id *match, int core_num,
1967 struct bcma_device *core)
1968 @@ -286,6 +329,23 @@ static int bcma_get_next_core(struct bcm
1969 return -EILSEQ;
1970 }
1971
1972 + /* First Slave Address Descriptor should be port 0:
1973 + * the main register space for the core
1974 + */
1975 + tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
1976 + if (tmp <= 0) {
1977 + /* Try again to see if it is a bridge */
1978 + tmp = bcma_erom_get_addr_desc(bus, eromptr,
1979 + SCAN_ADDR_TYPE_BRIDGE, 0);
1980 + if (tmp <= 0) {
1981 + return -EILSEQ;
1982 + } else {
1983 + bcma_info(bus, "Bridge found\n");
1984 + return -ENXIO;
1985 + }
1986 + }
1987 + core->addr = tmp;
1988 +
1989 /* get & parse slave ports */
1990 for (i = 0; i < ports[1]; i++) {
1991 for (j = 0; ; j++) {
1992 @@ -298,7 +358,7 @@ static int bcma_get_next_core(struct bcm
1993 break;
1994 } else {
1995 if (i == 0 && j == 0)
1996 - core->addr = tmp;
1997 + core->addr1 = tmp;
1998 }
1999 }
2000 }
2001 @@ -353,6 +413,7 @@ static int bcma_get_next_core(struct bcm
2002 void bcma_init_bus(struct bcma_bus *bus)
2003 {
2004 s32 tmp;
2005 + struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
2006
2007 if (bus->init_done)
2008 return;
2009 @@ -363,9 +424,12 @@ void bcma_init_bus(struct bcma_bus *bus)
2010 bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
2011
2012 tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
2013 - bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
2014 - bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
2015 - bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
2016 + chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
2017 + chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
2018 + chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
2019 + bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
2020 + chipinfo->id, chipinfo->rev, chipinfo->pkg);
2021 +
2022 bus->init_done = true;
2023 }
2024
2025 @@ -392,6 +456,7 @@ int bcma_bus_scan(struct bcma_bus *bus)
2026 bcma_scan_switch_core(bus, erombase);
2027
2028 while (eromptr < eromend) {
2029 + struct bcma_device *other_core;
2030 struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
2031 if (!core)
2032 return -ENOMEM;
2033 @@ -414,12 +479,13 @@ int bcma_bus_scan(struct bcma_bus *bus)
2034
2035 core->core_index = core_num++;
2036 bus->nr_cores++;
2037 + other_core = bcma_find_core_reverse(bus, core->id.id);
2038 + core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1;
2039
2040 - pr_info("Core %d found: %s "
2041 - "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2042 - core->core_index, bcma_device_name(&core->id),
2043 - core->id.manuf, core->id.id, core->id.rev,
2044 - core->id.class);
2045 + bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2046 + core->core_index, bcma_device_name(&core->id),
2047 + core->id.manuf, core->id.id, core->id.rev,
2048 + core->id.class);
2049
2050 list_add(&core->list, &bus->cores);
2051 }
2052 @@ -471,11 +537,10 @@ int __init bcma_bus_scan_early(struct bc
2053
2054 core->core_index = core_num++;
2055 bus->nr_cores++;
2056 - pr_info("Core %d found: %s "
2057 - "(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2058 - core->core_index, bcma_device_name(&core->id),
2059 - core->id.manuf, core->id.id, core->id.rev,
2060 - core->id.class);
2061 + bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
2062 + core->core_index, bcma_device_name(&core->id),
2063 + core->id.manuf, core->id.id, core->id.rev,
2064 + core->id.class);
2065
2066 list_add(&core->list, &bus->cores);
2067 err = 0;
2068 --- a/drivers/bcma/sprom.c
2069 +++ b/drivers/bcma/sprom.c
2070 @@ -2,6 +2,8 @@
2071 * Broadcom specific AMBA
2072 * SPROM reading
2073 *
2074 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
2075 + *
2076 * Licensed under the GNU/GPL. See COPYING for details.
2077 */
2078
2079 @@ -14,7 +16,57 @@
2080 #include <linux/dma-mapping.h>
2081 #include <linux/slab.h>
2082
2083 -#define SPOFF(offset) ((offset) / sizeof(u16))
2084 +static int(*get_fallback_sprom)(struct bcma_bus *dev, struct ssb_sprom *out);
2085 +
2086 +/**
2087 + * bcma_arch_register_fallback_sprom - Registers a method providing a
2088 + * fallback SPROM if no SPROM is found.
2089 + *
2090 + * @sprom_callback: The callback function.
2091 + *
2092 + * With this function the architecture implementation may register a
2093 + * callback handler which fills the SPROM data structure. The fallback is
2094 + * used for PCI based BCMA devices, where no valid SPROM can be found
2095 + * in the shadow registers and to provide the SPROM for SoCs where BCMA is
2096 + * to controll the system bus.
2097 + *
2098 + * This function is useful for weird architectures that have a half-assed
2099 + * BCMA device hardwired to their PCI bus.
2100 + *
2101 + * This function is available for architecture code, only. So it is not
2102 + * exported.
2103 + */
2104 +int bcma_arch_register_fallback_sprom(int (*sprom_callback)(struct bcma_bus *bus,
2105 + struct ssb_sprom *out))
2106 +{
2107 + if (get_fallback_sprom)
2108 + return -EEXIST;
2109 + get_fallback_sprom = sprom_callback;
2110 +
2111 + return 0;
2112 +}
2113 +
2114 +static int bcma_fill_sprom_with_fallback(struct bcma_bus *bus,
2115 + struct ssb_sprom *out)
2116 +{
2117 + int err;
2118 +
2119 + if (!get_fallback_sprom) {
2120 + err = -ENOENT;
2121 + goto fail;
2122 + }
2123 +
2124 + err = get_fallback_sprom(bus, out);
2125 + if (err)
2126 + goto fail;
2127 +
2128 + bcma_debug(bus, "Using SPROM revision %d provided by platform.\n",
2129 + bus->sprom.revision);
2130 + return 0;
2131 +fail:
2132 + bcma_warn(bus, "Using fallback SPROM failed (err %d)\n", err);
2133 + return err;
2134 +}
2135
2136 /**************************************************
2137 * R/W ops.
2138 @@ -124,10 +176,37 @@ static int bcma_sprom_valid(const u16 *s
2139 * SPROM extraction.
2140 **************************************************/
2141
2142 +#define SPOFF(offset) ((offset) / sizeof(u16))
2143 +
2144 +#define SPEX(_field, _offset, _mask, _shift) \
2145 + bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
2146 +
2147 +#define SPEX32(_field, _offset, _mask, _shift) \
2148 + bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 | \
2149 + sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
2150 +
2151 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
2152 + do { \
2153 + SPEX(_field[0], _offset + 0, _mask, _shift); \
2154 + SPEX(_field[1], _offset + 2, _mask, _shift); \
2155 + SPEX(_field[2], _offset + 4, _mask, _shift); \
2156 + SPEX(_field[3], _offset + 6, _mask, _shift); \
2157 + SPEX(_field[4], _offset + 8, _mask, _shift); \
2158 + SPEX(_field[5], _offset + 10, _mask, _shift); \
2159 + SPEX(_field[6], _offset + 12, _mask, _shift); \
2160 + SPEX(_field[7], _offset + 14, _mask, _shift); \
2161 + } while (0)
2162 +
2163 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
2164 {
2165 - u16 v;
2166 + u16 v, o;
2167 int i;
2168 + u16 pwr_info_offset[] = {
2169 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
2170 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
2171 + };
2172 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
2173 + ARRAY_SIZE(bus->sprom.core_pwr_info));
2174
2175 bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
2176 SSB_SPROM_REVISION_REV;
2177 @@ -137,102 +216,378 @@ static void bcma_sprom_extract_r8(struct
2178 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
2179 }
2180
2181 - bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)];
2182 + SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
2183
2184 - bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
2185 - SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT;
2186 - bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
2187 - SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT;
2188 - bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
2189 - SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT;
2190 - bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
2191 - SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT;
2192 -
2193 - bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
2194 - SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT;
2195 - bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
2196 - SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT;
2197 - bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
2198 - SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT;
2199 - bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
2200 - SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT;
2201 -
2202 - bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
2203 - SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT;
2204 - bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
2205 - SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT;
2206 - bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
2207 - SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT;
2208 - bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
2209 - SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT;
2210 -
2211 - bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
2212 - SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT;
2213 - bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
2214 - SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT;
2215 - bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
2216 - SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT;
2217 - bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
2218 - SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT;
2219 -
2220 - bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
2221 - bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
2222 - bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
2223 - bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
2224 -
2225 - bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
2226 -
2227 - bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
2228 - SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
2229 - bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
2230 - SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
2231 - bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
2232 - SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
2233 - bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
2234 - SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
2235 - bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
2236 - SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
2237 -
2238 - bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
2239 - SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
2240 - bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
2241 - SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
2242 - bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
2243 - SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
2244 - bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
2245 - SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
2246 - bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
2247 - SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
2248 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
2249 + SSB_SPROM4_TXPID2G0_SHIFT);
2250 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G1,
2251 + SSB_SPROM4_TXPID2G1_SHIFT);
2252 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G2,
2253 + SSB_SPROM4_TXPID2G2_SHIFT);
2254 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23, SSB_SPROM4_TXPID2G3,
2255 + SSB_SPROM4_TXPID2G3_SHIFT);
2256 +
2257 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL0,
2258 + SSB_SPROM4_TXPID5GL0_SHIFT);
2259 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01, SSB_SPROM4_TXPID5GL1,
2260 + SSB_SPROM4_TXPID5GL1_SHIFT);
2261 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL2,
2262 + SSB_SPROM4_TXPID5GL2_SHIFT);
2263 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23, SSB_SPROM4_TXPID5GL3,
2264 + SSB_SPROM4_TXPID5GL3_SHIFT);
2265 +
2266 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G0,
2267 + SSB_SPROM4_TXPID5G0_SHIFT);
2268 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01, SSB_SPROM4_TXPID5G1,
2269 + SSB_SPROM4_TXPID5G1_SHIFT);
2270 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G2,
2271 + SSB_SPROM4_TXPID5G2_SHIFT);
2272 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23, SSB_SPROM4_TXPID5G3,
2273 + SSB_SPROM4_TXPID5G3_SHIFT);
2274 +
2275 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH0,
2276 + SSB_SPROM4_TXPID5GH0_SHIFT);
2277 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01, SSB_SPROM4_TXPID5GH1,
2278 + SSB_SPROM4_TXPID5GH1_SHIFT);
2279 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH2,
2280 + SSB_SPROM4_TXPID5GH2_SHIFT);
2281 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23, SSB_SPROM4_TXPID5GH3,
2282 + SSB_SPROM4_TXPID5GH3_SHIFT);
2283 +
2284 + SPEX(boardflags_lo, SSB_SPROM8_BFLLO, ~0, 0);
2285 + SPEX(boardflags_hi, SSB_SPROM8_BFLHI, ~0, 0);
2286 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, ~0, 0);
2287 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, ~0, 0);
2288 +
2289 + SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
2290 + SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
2291 +
2292 + /* Extract cores power info info */
2293 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
2294 + o = pwr_info_offset[i];
2295 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
2296 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
2297 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
2298 + SSB_SPROM8_2G_MAXP, 0);
2299 +
2300 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
2301 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
2302 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
2303 +
2304 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
2305 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
2306 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
2307 + SSB_SPROM8_5G_MAXP, 0);
2308 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
2309 + SSB_SPROM8_5GH_MAXP, 0);
2310 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
2311 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
2312 +
2313 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
2314 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
2315 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
2316 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
2317 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
2318 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
2319 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
2320 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
2321 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
2322 + }
2323 +
2324 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS,
2325 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
2326 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN,
2327 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
2328 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_PDET_RANGE,
2329 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
2330 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TR_ISO,
2331 + SSB_SROM8_FEM_TR_ISO_SHIFT);
2332 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_ANTSWLUT,
2333 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
2334 +
2335 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TSSIPOS,
2336 + SSB_SROM8_FEM_TSSIPOS_SHIFT);
2337 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_EXTPA_GAIN,
2338 + SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
2339 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_PDET_RANGE,
2340 + SSB_SROM8_FEM_PDET_RANGE_SHIFT);
2341 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_TR_ISO,
2342 + SSB_SROM8_FEM_TR_ISO_SHIFT);
2343 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G, SSB_SROM8_FEM_ANTSWLUT,
2344 + SSB_SROM8_FEM_ANTSWLUT_SHIFT);
2345 +
2346 + SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
2347 + SSB_SPROM8_ANTAVAIL_A_SHIFT);
2348 + SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
2349 + SSB_SPROM8_ANTAVAIL_BG_SHIFT);
2350 + SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
2351 + SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
2352 + SSB_SPROM8_ITSSI_BG_SHIFT);
2353 + SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
2354 + SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
2355 + SSB_SPROM8_ITSSI_A_SHIFT);
2356 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
2357 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
2358 + SSB_SPROM8_MAXP_AL_SHIFT);
2359 + SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
2360 + SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
2361 + SSB_SPROM8_GPIOA_P1_SHIFT);
2362 + SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
2363 + SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
2364 + SSB_SPROM8_GPIOB_P3_SHIFT);
2365 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
2366 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
2367 + SSB_SPROM8_TRI5G_SHIFT);
2368 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
2369 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
2370 + SSB_SPROM8_TRI5GH_SHIFT);
2371 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G,
2372 + SSB_SPROM8_RXPO2G_SHIFT);
2373 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
2374 + SSB_SPROM8_RXPO5G_SHIFT);
2375 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
2376 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
2377 + SSB_SPROM8_RSSISMC2G_SHIFT);
2378 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
2379 + SSB_SPROM8_RSSISAV2G_SHIFT);
2380 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
2381 + SSB_SPROM8_BXA2G_SHIFT);
2382 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
2383 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
2384 + SSB_SPROM8_RSSISMC5G_SHIFT);
2385 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
2386 + SSB_SPROM8_RSSISAV5G_SHIFT);
2387 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
2388 + SSB_SPROM8_BXA5G_SHIFT);
2389 +
2390 + SPEX(pa0b0, SSB_SPROM8_PA0B0, ~0, 0);
2391 + SPEX(pa0b1, SSB_SPROM8_PA0B1, ~0, 0);
2392 + SPEX(pa0b2, SSB_SPROM8_PA0B2, ~0, 0);
2393 + SPEX(pa1b0, SSB_SPROM8_PA1B0, ~0, 0);
2394 + SPEX(pa1b1, SSB_SPROM8_PA1B1, ~0, 0);
2395 + SPEX(pa1b2, SSB_SPROM8_PA1B2, ~0, 0);
2396 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, ~0, 0);
2397 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, ~0, 0);
2398 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, ~0, 0);
2399 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, ~0, 0);
2400 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, ~0, 0);
2401 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, ~0, 0);
2402 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, ~0, 0);
2403 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, ~0, 0);
2404 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, ~0, 0);
2405 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, ~0, 0);
2406 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
2407 +
2408 + /* Extract the antenna gain values. */
2409 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
2410 + SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
2411 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
2412 + SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
2413 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
2414 + SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
2415 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
2416 + SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
2417 +
2418 + SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
2419 + SSB_SPROM8_LEDDC_ON_SHIFT);
2420 + SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
2421 + SSB_SPROM8_LEDDC_OFF_SHIFT);
2422 +
2423 + SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
2424 + SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
2425 + SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
2426 + SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
2427 + SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
2428 + SSB_SPROM8_TXRXC_SWITCH_SHIFT);
2429 +
2430 + SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
2431 +
2432 + SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
2433 + SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
2434 + SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
2435 + SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
2436 +
2437 + SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
2438 + SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
2439 + SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
2440 + SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
2441 + SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
2442 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
2443 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
2444 + SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
2445 + SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
2446 + SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
2447 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
2448 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
2449 + SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
2450 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
2451 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
2452 + SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
2453 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
2454 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
2455 + SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
2456 + SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
2457 +
2458 + SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
2459 + SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
2460 + SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
2461 + SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
2462 +
2463 + SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
2464 + SSB_SPROM8_THERMAL_TRESH_SHIFT);
2465 + SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
2466 + SSB_SPROM8_THERMAL_OFFSET_SHIFT);
2467 + SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
2468 + SSB_SPROM8_TEMPDELTA_PHYCAL,
2469 + SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
2470 + SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
2471 + SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
2472 + SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
2473 + SSB_SPROM8_TEMPDELTA_HYSTERESIS,
2474 + SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
2475 +}
2476 +
2477 +/*
2478 + * Indicates the presence of external SPROM.
2479 + */
2480 +static bool bcma_sprom_ext_available(struct bcma_bus *bus)
2481 +{
2482 + u32 chip_status;
2483 + u32 srom_control;
2484 + u32 present_mask;
2485 +
2486 + if (bus->drv_cc.core->id.rev >= 31) {
2487 + if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
2488 + return false;
2489 +
2490 + srom_control = bcma_read32(bus->drv_cc.core,
2491 + BCMA_CC_SROM_CONTROL);
2492 + return srom_control & BCMA_CC_SROM_CONTROL_PRESENT;
2493 + }
2494 +
2495 + /* older chipcommon revisions use chip status register */
2496 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
2497 + switch (bus->chipinfo.id) {
2498 + case BCMA_CHIP_ID_BCM4313:
2499 + present_mask = BCMA_CC_CHIPST_4313_SPROM_PRESENT;
2500 + break;
2501 +
2502 + case BCMA_CHIP_ID_BCM4331:
2503 + present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
2504 + break;
2505 +
2506 + default:
2507 + return true;
2508 + }
2509 +
2510 + return chip_status & present_mask;
2511 +}
2512 +
2513 +/*
2514 + * Indicates that on-chip OTP memory is present and enabled.
2515 + */
2516 +static bool bcma_sprom_onchip_available(struct bcma_bus *bus)
2517 +{
2518 + u32 chip_status;
2519 + u32 otpsize = 0;
2520 + bool present;
2521 +
2522 + chip_status = bcma_read32(bus->drv_cc.core, BCMA_CC_CHIPSTAT);
2523 + switch (bus->chipinfo.id) {
2524 + case BCMA_CHIP_ID_BCM4313:
2525 + present = chip_status & BCMA_CC_CHIPST_4313_OTP_PRESENT;
2526 + break;
2527 +
2528 + case BCMA_CHIP_ID_BCM4331:
2529 + present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
2530 + break;
2531 +
2532 + case BCMA_CHIP_ID_BCM43224:
2533 + case BCMA_CHIP_ID_BCM43225:
2534 + /* for these chips OTP is always available */
2535 + present = true;
2536 + break;
2537 +
2538 + default:
2539 + present = false;
2540 + break;
2541 + }
2542 +
2543 + if (present) {
2544 + otpsize = bus->drv_cc.capabilities & BCMA_CC_CAP_OTPS;
2545 + otpsize >>= BCMA_CC_CAP_OTPS_SHIFT;
2546 + }
2547 +
2548 + return otpsize != 0;
2549 +}
2550 +
2551 +/*
2552 + * Verify OTP is filled and determine the byte
2553 + * offset where SPROM data is located.
2554 + *
2555 + * On error, returns 0; byte offset otherwise.
2556 + */
2557 +static int bcma_sprom_onchip_offset(struct bcma_bus *bus)
2558 +{
2559 + struct bcma_device *cc = bus->drv_cc.core;
2560 + u32 offset;
2561 +
2562 + /* verify OTP status */
2563 + if ((bcma_read32(cc, BCMA_CC_OTPS) & BCMA_CC_OTPS_GU_PROG_HW) == 0)
2564 + return 0;
2565 +
2566 + /* obtain bit offset from otplayout register */
2567 + offset = (bcma_read32(cc, BCMA_CC_OTPL) & BCMA_CC_OTPL_GURGN_OFFSET);
2568 + return BCMA_CC_SPROM + (offset >> 3);
2569 }
2570
2571 int bcma_sprom_get(struct bcma_bus *bus)
2572 {
2573 - u16 offset;
2574 + u16 offset = BCMA_CC_SPROM;
2575 u16 *sprom;
2576 int err = 0;
2577
2578 if (!bus->drv_cc.core)
2579 return -EOPNOTSUPP;
2580
2581 - if (!(bus->drv_cc.capabilities & BCMA_CC_CAP_SPROM))
2582 - return -ENOENT;
2583 + if (!bcma_sprom_ext_available(bus)) {
2584 + bool sprom_onchip;
2585 +
2586 + /*
2587 + * External SPROM takes precedence so check
2588 + * on-chip OTP only when no external SPROM
2589 + * is present.
2590 + */
2591 + sprom_onchip = bcma_sprom_onchip_available(bus);
2592 + if (sprom_onchip) {
2593 + /* determine offset */
2594 + offset = bcma_sprom_onchip_offset(bus);
2595 + }
2596 + if (!offset || !sprom_onchip) {
2597 + /*
2598 + * Maybe there is no SPROM on the device?
2599 + * Now we ask the arch code if there is some sprom
2600 + * available for this device in some other storage.
2601 + */
2602 + err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
2603 + return err;
2604 + }
2605 + }
2606
2607 sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
2608 GFP_KERNEL);
2609 if (!sprom)
2610 return -ENOMEM;
2611
2612 - if (bus->chipinfo.id == 0x4331)
2613 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
2614 + bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
2615 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
2616
2617 - /* Most cards have SPROM moved by additional offset 0x30 (48 dwords).
2618 - * According to brcm80211 this applies to cards with PCIe rev >= 6
2619 - * TODO: understand this condition and use it */
2620 - offset = (bus->chipinfo.id == 0x4331) ? BCMA_CC_SPROM :
2621 - BCMA_CC_SPROM_PCIE6;
2622 + bcma_debug(bus, "SPROM offset 0x%x\n", offset);
2623 bcma_sprom_read(bus, offset, sprom);
2624
2625 - if (bus->chipinfo.id == 0x4331)
2626 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
2627 + bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
2628 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
2629
2630 err = bcma_sprom_valid(sprom);
2631 --- a/include/linux/bcma/bcma.h
2632 +++ b/include/linux/bcma/bcma.h
2633 @@ -26,6 +26,11 @@ struct bcma_chipinfo {
2634 u8 pkg;
2635 };
2636
2637 +struct bcma_boardinfo {
2638 + u16 vendor;
2639 + u16 type;
2640 +};
2641 +
2642 enum bcma_clkmode {
2643 BCMA_CLKMODE_FAST,
2644 BCMA_CLKMODE_DYNAMIC,
2645 @@ -65,6 +70,13 @@ struct bcma_host_ops {
2646
2647 /* Core-ID values. */
2648 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
2649 +#define BCMA_CORE_4706_CHIPCOMMON 0x500
2650 +#define BCMA_CORE_4706_SOC_RAM 0x50E
2651 +#define BCMA_CORE_4706_MAC_GBIT 0x52D
2652 +#define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
2653 +#define BCMA_CORE_ALTA 0x534 /* I2S core */
2654 +#define BCMA_CORE_4706_MAC_GBIT_COMMON 0x5DC
2655 +#define BCMA_CORE_DDR23_PHY 0x5DD
2656 #define BCMA_CORE_INVALID 0x700
2657 #define BCMA_CORE_CHIPCOMMON 0x800
2658 #define BCMA_CORE_ILINE20 0x801
2659 @@ -125,6 +137,36 @@ struct bcma_host_ops {
2660
2661 #define BCMA_MAX_NR_CORES 16
2662
2663 +/* Chip IDs of PCIe devices */
2664 +#define BCMA_CHIP_ID_BCM4313 0x4313
2665 +#define BCMA_CHIP_ID_BCM43224 43224
2666 +#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
2667 +#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
2668 +#define BCMA_CHIP_ID_BCM43225 43225
2669 +#define BCMA_CHIP_ID_BCM43227 43227
2670 +#define BCMA_CHIP_ID_BCM43228 43228
2671 +#define BCMA_CHIP_ID_BCM43421 43421
2672 +#define BCMA_CHIP_ID_BCM43428 43428
2673 +#define BCMA_CHIP_ID_BCM43431 43431
2674 +#define BCMA_CHIP_ID_BCM43460 43460
2675 +#define BCMA_CHIP_ID_BCM4331 0x4331
2676 +#define BCMA_CHIP_ID_BCM6362 0x6362
2677 +#define BCMA_CHIP_ID_BCM4360 0x4360
2678 +#define BCMA_CHIP_ID_BCM4352 0x4352
2679 +
2680 +/* Chip IDs of SoCs */
2681 +#define BCMA_CHIP_ID_BCM4706 0x5300
2682 +#define BCMA_CHIP_ID_BCM4716 0x4716
2683 +#define BCMA_PKG_ID_BCM4716 8
2684 +#define BCMA_PKG_ID_BCM4717 9
2685 +#define BCMA_PKG_ID_BCM4718 10
2686 +#define BCMA_CHIP_ID_BCM47162 47162
2687 +#define BCMA_CHIP_ID_BCM4748 0x4748
2688 +#define BCMA_CHIP_ID_BCM4749 0x4749
2689 +#define BCMA_CHIP_ID_BCM5356 0x5356
2690 +#define BCMA_CHIP_ID_BCM5357 0x5357
2691 +#define BCMA_CHIP_ID_BCM53572 53572
2692 +
2693 struct bcma_device {
2694 struct bcma_bus *bus;
2695 struct bcma_device_id id;
2696 @@ -136,8 +178,10 @@ struct bcma_device {
2697 bool dev_registered;
2698
2699 u8 core_index;
2700 + u8 core_unit;
2701
2702 u32 addr;
2703 + u32 addr1;
2704 u32 wrap;
2705
2706 void __iomem *io_addr;
2707 @@ -175,6 +219,12 @@ int __bcma_driver_register(struct bcma_d
2708
2709 extern void bcma_driver_unregister(struct bcma_driver *drv);
2710
2711 +/* Set a fallback SPROM.
2712 + * See kdoc at the function definition for complete documentation. */
2713 +extern int bcma_arch_register_fallback_sprom(
2714 + int (*sprom_callback)(struct bcma_bus *bus,
2715 + struct ssb_sprom *out));
2716 +
2717 struct bcma_bus {
2718 /* The MMIO area. */
2719 void __iomem *mmio;
2720 @@ -191,10 +241,13 @@ struct bcma_bus {
2721
2722 struct bcma_chipinfo chipinfo;
2723
2724 + struct bcma_boardinfo boardinfo;
2725 +
2726 struct bcma_device *mapped_core;
2727 struct list_head cores;
2728 u8 nr_cores;
2729 u8 init_done:1;
2730 + u8 num;
2731
2732 struct bcma_drv_cc drv_cc;
2733 struct bcma_drv_pci drv_pci;
2734 @@ -282,6 +335,7 @@ static inline void bcma_maskset16(struct
2735 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
2736 }
2737
2738 +extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
2739 extern bool bcma_core_is_enabled(struct bcma_device *core);
2740 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
2741 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
2742 --- a/include/linux/bcma/bcma_driver_chipcommon.h
2743 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
2744 @@ -56,6 +56,9 @@
2745 #define BCMA_CC_OTPS_HW_PROTECT 0x00000001
2746 #define BCMA_CC_OTPS_SW_PROTECT 0x00000002
2747 #define BCMA_CC_OTPS_CID_PROTECT 0x00000004
2748 +#define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */
2749 +#define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8
2750 +#define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */
2751 #define BCMA_CC_OTPC 0x0014 /* OTP control */
2752 #define BCMA_CC_OTPC_RECWAIT 0xFF000000
2753 #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00
2754 @@ -72,6 +75,8 @@
2755 #define BCMA_CC_OTPP_READ 0x40000000
2756 #define BCMA_CC_OTPP_START 0x80000000
2757 #define BCMA_CC_OTPP_BUSY 0x80000000
2758 +#define BCMA_CC_OTPL 0x001C /* OTP layout */
2759 +#define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */
2760 #define BCMA_CC_IRQSTAT 0x0020
2761 #define BCMA_CC_IRQMASK 0x0024
2762 #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */
2763 @@ -79,6 +84,15 @@
2764 #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
2765 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */
2766 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */
2767 +#define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1
2768 +#define BCMA_CC_CHIPST_4313_OTP_PRESENT 2
2769 +#define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2
2770 +#define BCMA_CC_CHIPST_4331_OTP_PRESENT 4
2771 +#define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
2772 +#define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
2773 +#define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
2774 +#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
2775 +#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
2776 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
2777 #define BCMA_CC_JCMD_START 0x80000000
2778 #define BCMA_CC_JCMD_BUSY 0x80000000
2779 @@ -181,6 +195,22 @@
2780 #define BCMA_CC_FLASH_CFG 0x0128
2781 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
2782 #define BCMA_CC_FLASH_WAITCNT 0x012C
2783 +#define BCMA_CC_SROM_CONTROL 0x0190
2784 +#define BCMA_CC_SROM_CONTROL_START 0x80000000
2785 +#define BCMA_CC_SROM_CONTROL_BUSY 0x80000000
2786 +#define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000
2787 +#define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000
2788 +#define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000
2789 +#define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000
2790 +#define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000
2791 +#define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010
2792 +#define BCMA_CC_SROM_CONTROL_LOCK 0x00000008
2793 +#define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006
2794 +#define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000
2795 +#define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002
2796 +#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
2797 +#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
2798 +#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
2799 /* 0x1E0 is defined as shared BCMA_CLKCTLST */
2800 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
2801 #define BCMA_CC_UART0_DATA 0x0300
2802 @@ -240,7 +270,6 @@
2803 #define BCMA_CC_PLLCTL_ADDR 0x0660
2804 #define BCMA_CC_PLLCTL_DATA 0x0664
2805 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
2806 -#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */
2807
2808 /* Divider allocation in 4716/47162/5356 */
2809 #define BCMA_CC_PMU5_MAINPLL_CPU 1
2810 @@ -256,6 +285,15 @@
2811
2812 /* 4706 PMU */
2813 #define BCMA_CC_PMU4706_MAINPLL_PLL0 0
2814 +#define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */
2815 +#define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000
2816 +#define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16
2817 +#define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000
2818 +#define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12
2819 +#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8
2820 +#define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3
2821 +#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
2822 +#define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
2823
2824 /* ALP clock on pre-PMU chips */
2825 #define BCMA_CC_PMU_ALP_CLOCK 20000000
2826 @@ -284,6 +322,19 @@
2827 #define BCMA_CC_PPL_PCHI_OFF 5
2828 #define BCMA_CC_PPL_PCHI_MASK 0x0000003f
2829
2830 +#define BCMA_CC_PMU_PLL_CTL0 0
2831 +#define BCMA_CC_PMU_PLL_CTL1 1
2832 +#define BCMA_CC_PMU_PLL_CTL2 2
2833 +#define BCMA_CC_PMU_PLL_CTL3 3
2834 +#define BCMA_CC_PMU_PLL_CTL4 4
2835 +#define BCMA_CC_PMU_PLL_CTL5 5
2836 +
2837 +#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
2838 +#define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20
2839 +
2840 +#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
2841 +#define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
2842 +
2843 /* BCM4331 ChipControl numbers. */
2844 #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
2845 #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
2846 @@ -297,9 +348,18 @@
2847 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
2848 #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
2849 #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
2850 +#define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */
2851 #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
2852 #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
2853
2854 +/* 43224 chip-specific ChipControl register bits */
2855 +#define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
2856 +#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
2857 +#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
2858 +
2859 +/* 4313 Chip specific ChipControl register bits */
2860 +#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
2861 +
2862 /* Data for the PMU, if available.
2863 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
2864 */
2865 @@ -387,5 +447,6 @@ extern void bcma_chipco_chipctl_maskset(
2866 u32 offset, u32 mask, u32 set);
2867 extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
2868 u32 offset, u32 mask, u32 set);
2869 +extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
2870
2871 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
2872 --- a/include/linux/bcma/bcma_driver_pci.h
2873 +++ b/include/linux/bcma/bcma_driver_pci.h
2874 @@ -53,11 +53,47 @@ struct pci_dev;
2875 #define BCMA_CORE_PCI_SBTOPCI1_MASK 0xFC000000
2876 #define BCMA_CORE_PCI_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
2877 #define BCMA_CORE_PCI_SBTOPCI2_MASK 0xC0000000
2878 +#define BCMA_CORE_PCI_CONFIG_ADDR 0x0120 /* pcie config space access */
2879 +#define BCMA_CORE_PCI_CONFIG_DATA 0x0124 /* pcie config space access */
2880 +#define BCMA_CORE_PCI_MDIO_CONTROL 0x0128 /* controls the mdio access */
2881 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
2882 +#define BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL 0x2
2883 +#define BCMA_CORE_PCI_MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
2884 +#define BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
2885 +#define BCMA_CORE_PCI_MDIO_DATA 0x012c /* Data to the mdio access */
2886 +#define BCMA_CORE_PCI_MDIODATA_MASK 0x0000ffff /* data 2 bytes */
2887 +#define BCMA_CORE_PCI_MDIODATA_TA 0x00020000 /* Turnaround */
2888 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
2889 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
2890 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
2891 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
2892 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
2893 +#define BCMA_CORE_PCI_MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
2894 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
2895 +#define BCMA_CORE_PCI_MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
2896 +#define BCMA_CORE_PCI_MDIODATA_WRITE 0x10000000 /* write Transaction */
2897 +#define BCMA_CORE_PCI_MDIODATA_READ 0x20000000 /* Read Transaction */
2898 +#define BCMA_CORE_PCI_MDIODATA_START 0x40000000 /* start of Transaction */
2899 +#define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
2900 +#define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
2901 +#define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
2902 +#define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
2903 +#define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
2904 +#define BCMA_CORE_PCI_PCIEIND_ADDR 0x0130 /* indirect access to the internal register */
2905 +#define BCMA_CORE_PCI_PCIEIND_DATA 0x0134 /* Data to/from the internal regsiter */
2906 +#define BCMA_CORE_PCI_CLKREQENCTRL 0x0138 /* >= rev 6, Clkreq rdma control */
2907 #define BCMA_CORE_PCI_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
2908 #define BCMA_CORE_PCI_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
2909 #define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
2910 #define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
2911 #define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
2912 +#define BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */
2913 +#define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */
2914 +#define BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */
2915 +#define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */
2916 +#define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
2917 +#define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
2918 +#define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */
2919
2920 /* SBtoPCIx */
2921 #define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
2922 @@ -72,20 +108,118 @@ struct pci_dev;
2923 #define BCMA_CORE_PCI_SBTOPCI_RC_READL 0x00000010 /* Memory read line */
2924 #define BCMA_CORE_PCI_SBTOPCI_RC_READM 0x00000020 /* Memory read multiple */
2925
2926 +/* PCIE protocol PHY diagnostic registers */
2927 +#define BCMA_CORE_PCI_PLP_MODEREG 0x200 /* Mode */
2928 +#define BCMA_CORE_PCI_PLP_STATUSREG 0x204 /* Status */
2929 +#define BCMA_CORE_PCI_PLP_POLARITYINV_STAT 0x10 /* Status reg PCIE_PLP_STATUSREG */
2930 +#define BCMA_CORE_PCI_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
2931 +#define BCMA_CORE_PCI_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
2932 +#define BCMA_CORE_PCI_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
2933 +#define BCMA_CORE_PCI_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
2934 +#define BCMA_CORE_PCI_PLP_ATTNREG 0x218 /* Attention */
2935 +#define BCMA_CORE_PCI_PLP_ATTNMASKREG 0x21C /* Attention Mask */
2936 +#define BCMA_CORE_PCI_PLP_RXERRCTR 0x220 /* Rx Error */
2937 +#define BCMA_CORE_PCI_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
2938 +#define BCMA_CORE_PCI_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
2939 +#define BCMA_CORE_PCI_PLP_TESTCTRLREG 0x22C /* Test Control reg */
2940 +#define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
2941 +#define BCMA_CORE_PCI_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
2942 +#define BCMA_CORE_PCI_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
2943 +#define BCMA_CORE_PCI_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
2944 +
2945 +/* PCIE protocol DLLP diagnostic registers */
2946 +#define BCMA_CORE_PCI_DLLP_LCREG 0x100 /* Link Control */
2947 +#define BCMA_CORE_PCI_DLLP_LSREG 0x104 /* Link Status */
2948 +#define BCMA_CORE_PCI_DLLP_LAREG 0x108 /* Link Attention */
2949 +#define BCMA_CORE_PCI_DLLP_LSREG_LINKUP (1 << 16)
2950 +#define BCMA_CORE_PCI_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
2951 +#define BCMA_CORE_PCI_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
2952 +#define BCMA_CORE_PCI_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
2953 +#define BCMA_CORE_PCI_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
2954 +#define BCMA_CORE_PCI_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
2955 +#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */
2956 +#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
2957 +#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
2958 +#define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
2959 +#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
2960 +#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
2961 +#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
2962 +#define BCMA_CORE_PCI_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
2963 +#define BCMA_CORE_PCI_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
2964 +#define BCMA_CORE_PCI_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
2965 +#define BCMA_CORE_PCI_DLLP_ERRCTRREG 0x144 /* Error Counter */
2966 +#define BCMA_CORE_PCI_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
2967 +#define BCMA_CORE_PCI_DLLP_TESTREG 0x14C /* Test */
2968 +#define BCMA_CORE_PCI_DLLP_PKTBIST 0x150 /* Packet BIST */
2969 +#define BCMA_CORE_PCI_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
2970 +
2971 +/* SERDES RX registers */
2972 +#define BCMA_CORE_PCI_SERDES_RX_CTRL 1 /* Rx cntrl */
2973 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
2974 +#define BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
2975 +#define BCMA_CORE_PCI_SERDES_RX_TIMER1 2 /* Rx Timer1 */
2976 +#define BCMA_CORE_PCI_SERDES_RX_CDR 6 /* CDR */
2977 +#define BCMA_CORE_PCI_SERDES_RX_CDRBW 7 /* CDR BW */
2978 +
2979 +/* SERDES PLL registers */
2980 +#define BCMA_CORE_PCI_SERDES_PLL_CTRL 1 /* PLL control reg */
2981 +#define BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
2982 +
2983 /* PCIcore specific boardflags */
2984 #define BCMA_CORE_PCI_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
2985
2986 +/* PCIE Config space accessing MACROS */
2987 +#define BCMA_CORE_PCI_CFG_BUS_SHIFT 24 /* Bus shift */
2988 +#define BCMA_CORE_PCI_CFG_SLOT_SHIFT 19 /* Slot/Device shift */
2989 +#define BCMA_CORE_PCI_CFG_FUN_SHIFT 16 /* Function shift */
2990 +#define BCMA_CORE_PCI_CFG_OFF_SHIFT 0 /* Register shift */
2991 +
2992 +#define BCMA_CORE_PCI_CFG_BUS_MASK 0xff /* Bus mask */
2993 +#define BCMA_CORE_PCI_CFG_SLOT_MASK 0x1f /* Slot/Device mask */
2994 +#define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
2995 +#define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
2996 +
2997 +/* PCIE Root Capability Register bits (Host mode only) */
2998 +#define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
2999 +
3000 +struct bcma_drv_pci;
3001 +
3002 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
3003 +struct bcma_drv_pci_host {
3004 + struct bcma_drv_pci *pdev;
3005 +
3006 + u32 host_cfg_addr;
3007 + spinlock_t cfgspace_lock;
3008 +
3009 + struct pci_controller pci_controller;
3010 + struct pci_ops pci_ops;
3011 + struct resource mem_resource;
3012 + struct resource io_resource;
3013 +};
3014 +#endif
3015 +
3016 struct bcma_drv_pci {
3017 struct bcma_device *core;
3018 u8 setup_done:1;
3019 + u8 hostmode:1;
3020 +
3021 +#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
3022 + struct bcma_drv_pci_host *host_controller;
3023 +#endif
3024 };
3025
3026 /* Register access */
3027 +#define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)
3028 #define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
3029 +#define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)
3030 #define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
3031
3032 -extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
3033 +extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
3034 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
3035 struct bcma_device *core, bool enable);
3036 +extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
3037 +
3038 +extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
3039 +extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
3040
3041 #endif /* LINUX_BCMA_DRIVER_PCI_H_ */
3042 --- a/include/linux/bcma/bcma_regs.h
3043 +++ b/include/linux/bcma/bcma_regs.h
3044 @@ -56,4 +56,31 @@
3045 #define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
3046 #define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
3047
3048 +/* SiliconBackplane Address Map.
3049 + * All regions may not exist on all chips.
3050 + */
3051 +#define BCMA_SOC_SDRAM_BASE 0x00000000U /* Physical SDRAM */
3052 +#define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
3053 +#define BCMA_SOC_PCI_MEM_SZ (64 * 1024 * 1024)
3054 +#define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
3055 +#define BCMA_SOC_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
3056 +#define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
3057 +
3058 +
3059 +#define BCMA_SOC_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
3060 +#define BCMA_SOC_PCI_DMA2 0x80000000U /* Client Mode sb2pcitranslation2 (1 GB) */
3061 +#define BCMA_SOC_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
3062 +#define BCMA_SOC_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2
3063 + * (2 ZettaBytes), low 32 bits
3064 + */
3065 +#define BCMA_SOC_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2
3066 + * (2 ZettaBytes), high 32 bits
3067 + */
3068 +
3069 +#define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
3070 +#define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
3071 +#define BCMA_SOC_PCIE1_DMA_H32 0xc0000000U /* PCIE Client Mode sb2pcitranslation2
3072 + * (2 ZettaBytes), high 32 bits
3073 + */
3074 +
3075 #endif /* LINUX_BCMA_REGS_H_ */
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