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update to 2.6.32.20
[openwrt/staging/pepe2k.git] / target / linux / generic / patches-2.6.32 / 975-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
3 @@ -373,6 +373,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
4 {
5 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
6 }
7 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
8
9 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
10 {
11 --- a/drivers/ssb/driver_chipcommon_pmu.c
12 +++ b/drivers/ssb/driver_chipcommon_pmu.c
13 @@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
14 case 0x5354:
15 ssb_pmu0_pllinit_r0(cc, crystalfreq);
16 break;
17 + case 0x4322:
18 + if (cc->pmu.rev == 2) {
19 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
20 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
21 + }
22 + break;
23 default:
24 ssb_printk(KERN_ERR PFX
25 "ERROR: PLL init unknown for device %04X\n",
26 @@ -417,6 +423,7 @@ static void ssb_pmu_resources_init(struc
27
28 switch (bus->chip_id) {
29 case 0x4312:
30 + case 0x4322:
31 /* We keep the default settings:
32 * min_msk = 0xCBB
33 * max_msk = 0x7FFFF
34 --- a/drivers/ssb/driver_gige.c
35 +++ b/drivers/ssb/driver_gige.c
36 @@ -12,6 +12,7 @@
37 #include <linux/ssb/ssb_driver_gige.h>
38 #include <linux/pci.h>
39 #include <linux/pci_regs.h>
40 +#include <linux/slab.h>
41
42
43 /*
44 --- a/drivers/ssb/driver_mipscore.c
45 +++ b/drivers/ssb/driver_mipscore.c
46 @@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
47 set_irq(dev, irq++);
48 }
49 break;
50 - /* fallthrough */
51 case SSB_DEV_PCI:
52 case SSB_DEV_ETHERNET:
53 case SSB_DEV_ETHERNET_GBIT:
54 @@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
55 set_irq(dev, irq++);
56 break;
57 }
58 + /* fallthrough */
59 + case SSB_DEV_EXTIF:
60 + set_irq(dev, 0);
61 + break;
62 }
63 }
64 ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
65 --- a/drivers/ssb/driver_pcicore.c
66 +++ b/drivers/ssb/driver_pcicore.c
67 @@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore
68 .pci_ops = &ssb_pcicore_pciops,
69 .io_resource = &ssb_pcicore_io_resource,
70 .mem_resource = &ssb_pcicore_mem_resource,
71 - .mem_offset = 0x24000000,
72 };
73
74 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
75 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
76 -
77 /* This function is called when doing a pci_enable_device().
78 * We must first check if the device is a device on the PCI-core bridge. */
79 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
80 {
81 - struct resource *res;
82 - int pos, size;
83 - u32 *base;
84 -
85 if (d->bus->ops != &ssb_pcicore_pciops) {
86 /* This is not a device on the PCI-core bridge. */
87 return -ENODEV;
88 @@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci
89 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
90 pci_name(d));
91
92 - /* Fix up resource bases */
93 - for (pos = 0; pos < 6; pos++) {
94 - res = &d->resource[pos];
95 - if (res->flags & IORESOURCE_IO)
96 - base = &ssb_pcicore_pcibus_iobase;
97 - else
98 - base = &ssb_pcicore_pcibus_membase;
99 - res->flags |= IORESOURCE_PCI_FIXED;
100 - if (res->end) {
101 - size = res->end - res->start + 1;
102 - if (*base & (size - 1))
103 - *base = (*base + size) & ~(size - 1);
104 - res->start = *base;
105 - res->end = res->start + size - 1;
106 - *base += size;
107 - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
108 - }
109 - /* Fix up PCI bridge BAR0 only */
110 - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
111 - break;
112 - }
113 /* Fix up interrupt lines */
114 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
115 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
116 @@ -551,13 +522,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
117 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
118
119 /* Enable interrupts for this device. */
120 - if (bus->host_pci &&
121 - ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
122 + if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
123 u32 coremask;
124
125 /* Calculate the "coremask" for the device. */
126 coremask = (1 << dev->core_index);
127
128 + SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
129 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
130 if (err)
131 goto out;
132 --- a/drivers/ssb/main.c
133 +++ b/drivers/ssb/main.c
134 @@ -18,6 +18,7 @@
135 #include <linux/dma-mapping.h>
136 #include <linux/pci.h>
137 #include <linux/mmc/sdio_func.h>
138 +#include <linux/slab.h>
139
140 #include <pcmcia/cs_types.h>
141 #include <pcmcia/cs.h>
142 @@ -140,6 +141,19 @@ static void ssb_device_put(struct ssb_de
143 put_device(dev->dev);
144 }
145
146 +static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
147 +{
148 + if (drv)
149 + get_driver(&drv->drv);
150 + return drv;
151 +}
152 +
153 +static inline void ssb_driver_put(struct ssb_driver *drv)
154 +{
155 + if (drv)
156 + put_driver(&drv->drv);
157 +}
158 +
159 static int ssb_device_resume(struct device *dev)
160 {
161 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
162 @@ -210,90 +224,81 @@ int ssb_bus_suspend(struct ssb_bus *bus)
163 EXPORT_SYMBOL(ssb_bus_suspend);
164
165 #ifdef CONFIG_SSB_SPROM
166 -int ssb_devices_freeze(struct ssb_bus *bus)
167 +/** ssb_devices_freeze - Freeze all devices on the bus.
168 + *
169 + * After freezing no device driver will be handling a device
170 + * on this bus anymore. ssb_devices_thaw() must be called after
171 + * a successful freeze to reactivate the devices.
172 + *
173 + * @bus: The bus.
174 + * @ctx: Context structure. Pass this to ssb_devices_thaw().
175 + */
176 +int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
177 {
178 - struct ssb_device *dev;
179 - struct ssb_driver *drv;
180 - int err = 0;
181 - int i;
182 - pm_message_t state = PMSG_FREEZE;
183 + struct ssb_device *sdev;
184 + struct ssb_driver *sdrv;
185 + unsigned int i;
186 +
187 + memset(ctx, 0, sizeof(*ctx));
188 + ctx->bus = bus;
189 + SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
190
191 - /* First check that we are capable to freeze all devices. */
192 for (i = 0; i < bus->nr_devices; i++) {
193 - dev = &(bus->devices[i]);
194 - if (!dev->dev ||
195 - !dev->dev->driver ||
196 - !device_is_registered(dev->dev))
197 - continue;
198 - drv = drv_to_ssb_drv(dev->dev->driver);
199 - if (!drv)
200 + sdev = ssb_device_get(&bus->devices[i]);
201 +
202 + if (!sdev->dev || !sdev->dev->driver ||
203 + !device_is_registered(sdev->dev)) {
204 + ssb_device_put(sdev);
205 continue;
206 - if (!drv->suspend) {
207 - /* Nope, can't suspend this one. */
208 - return -EOPNOTSUPP;
209 }
210 - }
211 - /* Now suspend all devices */
212 - for (i = 0; i < bus->nr_devices; i++) {
213 - dev = &(bus->devices[i]);
214 - if (!dev->dev ||
215 - !dev->dev->driver ||
216 - !device_is_registered(dev->dev))
217 + sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
218 + if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
219 + ssb_device_put(sdev);
220 continue;
221 - drv = drv_to_ssb_drv(dev->dev->driver);
222 - if (!drv)
223 - continue;
224 - err = drv->suspend(dev, state);
225 - if (err) {
226 - ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
227 - dev_name(dev->dev));
228 - goto err_unwind;
229 }
230 + sdrv->remove(sdev);
231 + ctx->device_frozen[i] = 1;
232 }
233
234 return 0;
235 -err_unwind:
236 - for (i--; i >= 0; i--) {
237 - dev = &(bus->devices[i]);
238 - if (!dev->dev ||
239 - !dev->dev->driver ||
240 - !device_is_registered(dev->dev))
241 - continue;
242 - drv = drv_to_ssb_drv(dev->dev->driver);
243 - if (!drv)
244 - continue;
245 - if (drv->resume)
246 - drv->resume(dev);
247 - }
248 - return err;
249 }
250
251 -int ssb_devices_thaw(struct ssb_bus *bus)
252 +/** ssb_devices_thaw - Unfreeze all devices on the bus.
253 + *
254 + * This will re-attach the device drivers and re-init the devices.
255 + *
256 + * @ctx: The context structure from ssb_devices_freeze()
257 + */
258 +int ssb_devices_thaw(struct ssb_freeze_context *ctx)
259 {
260 - struct ssb_device *dev;
261 - struct ssb_driver *drv;
262 - int err;
263 - int i;
264 + struct ssb_bus *bus = ctx->bus;
265 + struct ssb_device *sdev;
266 + struct ssb_driver *sdrv;
267 + unsigned int i;
268 + int err, result = 0;
269
270 for (i = 0; i < bus->nr_devices; i++) {
271 - dev = &(bus->devices[i]);
272 - if (!dev->dev ||
273 - !dev->dev->driver ||
274 - !device_is_registered(dev->dev))
275 + if (!ctx->device_frozen[i])
276 continue;
277 - drv = drv_to_ssb_drv(dev->dev->driver);
278 - if (!drv)
279 + sdev = &bus->devices[i];
280 +
281 + if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
282 continue;
283 - if (SSB_WARN_ON(!drv->resume))
284 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
285 + if (SSB_WARN_ON(!sdrv || !sdrv->probe))
286 continue;
287 - err = drv->resume(dev);
288 +
289 + err = sdrv->probe(sdev, &sdev->id);
290 if (err) {
291 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
292 - dev_name(dev->dev));
293 + dev_name(sdev->dev));
294 + result = err;
295 }
296 + ssb_driver_put(sdrv);
297 + ssb_device_put(sdev);
298 }
299
300 - return 0;
301 + return result;
302 }
303 #endif /* CONFIG_SSB_SPROM */
304
305 @@ -490,8 +495,7 @@ static int ssb_devices_register(struct s
306 #endif
307 break;
308 case SSB_BUSTYPE_SDIO:
309 -#ifdef CONFIG_SSB_SDIO
310 - sdev->irq = bus->host_sdio->dev.irq;
311 +#ifdef CONFIG_SSB_SDIOHOST
312 dev->parent = &bus->host_sdio->dev;
313 #endif
314 break;
315 @@ -830,6 +834,9 @@ int ssb_bus_pcibus_register(struct ssb_b
316 if (!err) {
317 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
318 "PCI device %s\n", dev_name(&host_pci->dev));
319 + } else {
320 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
321 + " of SSB with error %d\n", err);
322 }
323
324 return err;
325 --- a/drivers/ssb/pci.c
326 +++ b/drivers/ssb/pci.c
327 @@ -17,6 +17,7 @@
328
329 #include <linux/ssb/ssb.h>
330 #include <linux/ssb/ssb_regs.h>
331 +#include <linux/slab.h>
332 #include <linux/pci.h>
333 #include <linux/delay.h>
334
335 @@ -642,6 +643,14 @@ static int ssb_pci_sprom_get(struct ssb_
336 }
337 ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
338
339 + if (!ssb_is_sprom_available(bus)) {
340 + ssb_printk(KERN_ERR PFX "No SPROM available!\n");
341 + return -ENODEV;
342 + }
343 +
344 + bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
345 + SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
346 +
347 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
348 if (!buf)
349 goto out;
350 --- a/drivers/ssb/pcihost_wrapper.c
351 +++ b/drivers/ssb/pcihost_wrapper.c
352 @@ -12,6 +12,7 @@
353 */
354
355 #include <linux/pci.h>
356 +#include <linux/slab.h>
357 #include <linux/ssb/ssb.h>
358
359
360 --- a/drivers/ssb/pcmcia.c
361 +++ b/drivers/ssb/pcmcia.c
362 @@ -617,136 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co
363 } \
364 } while (0)
365
366 -int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
367 - struct ssb_init_invariants *iv)
368 +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
369 + tuple_t *tuple,
370 + void *priv)
371 {
372 - tuple_t tuple;
373 - int res;
374 - unsigned char buf[32];
375 + struct ssb_sprom *sprom = priv;
376 +
377 + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
378 + return -EINVAL;
379 + if (tuple->TupleDataLen != ETH_ALEN + 2)
380 + return -EINVAL;
381 + if (tuple->TupleData[1] != ETH_ALEN)
382 + return -EINVAL;
383 + memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
384 + return 0;
385 +};
386 +
387 +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
388 + tuple_t *tuple,
389 + void *priv)
390 +{
391 + struct ssb_init_invariants *iv = priv;
392 struct ssb_sprom *sprom = &iv->sprom;
393 struct ssb_boardinfo *bi = &iv->boardinfo;
394 const char *error_description;
395
396 + GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
397 + switch (tuple->TupleData[0]) {
398 + case SSB_PCMCIA_CIS_ID:
399 + GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
400 + (tuple->TupleDataLen != 7),
401 + "id tpl size");
402 + bi->vendor = tuple->TupleData[1] |
403 + ((u16)tuple->TupleData[2] << 8);
404 + break;
405 + case SSB_PCMCIA_CIS_BOARDREV:
406 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
407 + "boardrev tpl size");
408 + sprom->board_rev = tuple->TupleData[1];
409 + break;
410 + case SSB_PCMCIA_CIS_PA:
411 + GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
412 + (tuple->TupleDataLen != 10),
413 + "pa tpl size");
414 + sprom->pa0b0 = tuple->TupleData[1] |
415 + ((u16)tuple->TupleData[2] << 8);
416 + sprom->pa0b1 = tuple->TupleData[3] |
417 + ((u16)tuple->TupleData[4] << 8);
418 + sprom->pa0b2 = tuple->TupleData[5] |
419 + ((u16)tuple->TupleData[6] << 8);
420 + sprom->itssi_a = tuple->TupleData[7];
421 + sprom->itssi_bg = tuple->TupleData[7];
422 + sprom->maxpwr_a = tuple->TupleData[8];
423 + sprom->maxpwr_bg = tuple->TupleData[8];
424 + break;
425 + case SSB_PCMCIA_CIS_OEMNAME:
426 + /* We ignore this. */
427 + break;
428 + case SSB_PCMCIA_CIS_CCODE:
429 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
430 + "ccode tpl size");
431 + sprom->country_code = tuple->TupleData[1];
432 + break;
433 + case SSB_PCMCIA_CIS_ANTENNA:
434 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
435 + "ant tpl size");
436 + sprom->ant_available_a = tuple->TupleData[1];
437 + sprom->ant_available_bg = tuple->TupleData[1];
438 + break;
439 + case SSB_PCMCIA_CIS_ANTGAIN:
440 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
441 + "antg tpl size");
442 + sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
443 + sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
444 + sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
445 + sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
446 + sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
447 + sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
448 + sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
449 + sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
450 + break;
451 + case SSB_PCMCIA_CIS_BFLAGS:
452 + GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
453 + (tuple->TupleDataLen != 5),
454 + "bfl tpl size");
455 + sprom->boardflags_lo = tuple->TupleData[1] |
456 + ((u16)tuple->TupleData[2] << 8);
457 + break;
458 + case SSB_PCMCIA_CIS_LEDS:
459 + GOTO_ERROR_ON(tuple->TupleDataLen != 5,
460 + "leds tpl size");
461 + sprom->gpio0 = tuple->TupleData[1];
462 + sprom->gpio1 = tuple->TupleData[2];
463 + sprom->gpio2 = tuple->TupleData[3];
464 + sprom->gpio3 = tuple->TupleData[4];
465 + break;
466 + }
467 + return -ENOSPC; /* continue with next entry */
468 +
469 +error:
470 + ssb_printk(KERN_ERR PFX
471 + "PCMCIA: Failed to fetch device invariants: %s\n",
472 + error_description);
473 + return -ENODEV;
474 +}
475 +
476 +
477 +int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
478 + struct ssb_init_invariants *iv)
479 +{
480 + struct ssb_sprom *sprom = &iv->sprom;
481 + int res;
482 +
483 memset(sprom, 0xFF, sizeof(*sprom));
484 sprom->revision = 1;
485 sprom->boardflags_lo = 0;
486 sprom->boardflags_hi = 0;
487
488 /* First fetch the MAC address. */
489 - memset(&tuple, 0, sizeof(tuple));
490 - tuple.DesiredTuple = CISTPL_FUNCE;
491 - tuple.TupleData = buf;
492 - tuple.TupleDataMax = sizeof(buf);
493 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
494 - GOTO_ERROR_ON(res != 0, "MAC first tpl");
495 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
496 - GOTO_ERROR_ON(res != 0, "MAC first tpl data");
497 - while (1) {
498 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
499 - if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
500 - break;
501 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
502 - GOTO_ERROR_ON(res != 0, "MAC next tpl");
503 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
504 - GOTO_ERROR_ON(res != 0, "MAC next tpl data");
505 + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
506 + ssb_pcmcia_get_mac, sprom);
507 + if (res != 0) {
508 + ssb_printk(KERN_ERR PFX
509 + "PCMCIA: Failed to fetch MAC address\n");
510 + return -ENODEV;
511 }
512 - GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
513 - memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
514
515 /* Fetch the vendor specific tuples. */
516 - memset(&tuple, 0, sizeof(tuple));
517 - tuple.DesiredTuple = SSB_PCMCIA_CIS;
518 - tuple.TupleData = buf;
519 - tuple.TupleDataMax = sizeof(buf);
520 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
521 - GOTO_ERROR_ON(res != 0, "VEN first tpl");
522 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
523 - GOTO_ERROR_ON(res != 0, "VEN first tpl data");
524 - while (1) {
525 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
526 - switch (tuple.TupleData[0]) {
527 - case SSB_PCMCIA_CIS_ID:
528 - GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
529 - (tuple.TupleDataLen != 7),
530 - "id tpl size");
531 - bi->vendor = tuple.TupleData[1] |
532 - ((u16)tuple.TupleData[2] << 8);
533 - break;
534 - case SSB_PCMCIA_CIS_BOARDREV:
535 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
536 - "boardrev tpl size");
537 - sprom->board_rev = tuple.TupleData[1];
538 - break;
539 - case SSB_PCMCIA_CIS_PA:
540 - GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
541 - (tuple.TupleDataLen != 10),
542 - "pa tpl size");
543 - sprom->pa0b0 = tuple.TupleData[1] |
544 - ((u16)tuple.TupleData[2] << 8);
545 - sprom->pa0b1 = tuple.TupleData[3] |
546 - ((u16)tuple.TupleData[4] << 8);
547 - sprom->pa0b2 = tuple.TupleData[5] |
548 - ((u16)tuple.TupleData[6] << 8);
549 - sprom->itssi_a = tuple.TupleData[7];
550 - sprom->itssi_bg = tuple.TupleData[7];
551 - sprom->maxpwr_a = tuple.TupleData[8];
552 - sprom->maxpwr_bg = tuple.TupleData[8];
553 - break;
554 - case SSB_PCMCIA_CIS_OEMNAME:
555 - /* We ignore this. */
556 - break;
557 - case SSB_PCMCIA_CIS_CCODE:
558 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
559 - "ccode tpl size");
560 - sprom->country_code = tuple.TupleData[1];
561 - break;
562 - case SSB_PCMCIA_CIS_ANTENNA:
563 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
564 - "ant tpl size");
565 - sprom->ant_available_a = tuple.TupleData[1];
566 - sprom->ant_available_bg = tuple.TupleData[1];
567 - break;
568 - case SSB_PCMCIA_CIS_ANTGAIN:
569 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
570 - "antg tpl size");
571 - sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
572 - sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
573 - sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
574 - sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
575 - sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
576 - sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
577 - sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
578 - sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
579 - break;
580 - case SSB_PCMCIA_CIS_BFLAGS:
581 - GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
582 - (tuple.TupleDataLen != 5),
583 - "bfl tpl size");
584 - sprom->boardflags_lo = tuple.TupleData[1] |
585 - ((u16)tuple.TupleData[2] << 8);
586 - break;
587 - case SSB_PCMCIA_CIS_LEDS:
588 - GOTO_ERROR_ON(tuple.TupleDataLen != 5,
589 - "leds tpl size");
590 - sprom->gpio0 = tuple.TupleData[1];
591 - sprom->gpio1 = tuple.TupleData[2];
592 - sprom->gpio2 = tuple.TupleData[3];
593 - sprom->gpio3 = tuple.TupleData[4];
594 - break;
595 - }
596 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
597 - if (res == -ENOSPC)
598 - break;
599 - GOTO_ERROR_ON(res != 0, "VEN next tpl");
600 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
601 - GOTO_ERROR_ON(res != 0, "VEN next tpl data");
602 - }
603 + res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
604 + ssb_pcmcia_do_get_invariants, sprom);
605 + if ((res == 0) || (res == -ENOSPC))
606 + return 0;
607
608 - return 0;
609 -error:
610 ssb_printk(KERN_ERR PFX
611 - "PCMCIA: Failed to fetch device invariants: %s\n",
612 - error_description);
613 + "PCMCIA: Failed to fetch device invariants\n");
614 return -ENODEV;
615 }
616
617 --- a/drivers/ssb/scan.c
618 +++ b/drivers/ssb/scan.c
619 @@ -354,7 +354,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
620 dev->bus = bus;
621 dev->ops = bus->ops;
622
623 - ssb_dprintk(KERN_INFO PFX
624 + printk(KERN_DEBUG PFX
625 "Core %d found: %s "
626 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
627 i, ssb_core_name(dev->id.coreid),
628 --- a/drivers/ssb/sprom.c
629 +++ b/drivers/ssb/sprom.c
630 @@ -14,6 +14,7 @@
631 #include "ssb_private.h"
632
633 #include <linux/ctype.h>
634 +#include <linux/slab.h>
635
636
637 static const struct ssb_sprom *fallback_sprom;
638 @@ -102,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
639 u16 *sprom;
640 int res = 0, err = -ENOMEM;
641 size_t sprom_size_words = bus->sprom_size;
642 + struct ssb_freeze_context freeze;
643
644 sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
645 if (!sprom)
646 @@ -123,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
647 err = -ERESTARTSYS;
648 if (mutex_lock_interruptible(&bus->sprom_mutex))
649 goto out_kfree;
650 - err = ssb_devices_freeze(bus);
651 - if (err == -EOPNOTSUPP) {
652 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
653 - "No suspend support. Is CONFIG_PM enabled?\n");
654 - goto out_unlock;
655 - }
656 + err = ssb_devices_freeze(bus, &freeze);
657 if (err) {
658 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
659 goto out_unlock;
660 }
661 res = sprom_write(bus, sprom);
662 - err = ssb_devices_thaw(bus);
663 + err = ssb_devices_thaw(&freeze);
664 if (err)
665 ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
666 out_unlock:
667 @@ -192,5 +189,19 @@ bool ssb_is_sprom_available(struct ssb_b
668 bus->chipco.dev->id.revision >= 31)
669 return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
670
671 + return true;
672 +}
673 +
674 +/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
675 +bool ssb_is_sprom_available(struct ssb_bus *bus)
676 +{
677 + /* status register only exists on chipcomon rev >= 11 and we need check
678 + for >= 31 only */
679 + /* this routine differs from specs as we do not access SPROM directly
680 + on PCMCIA */
681 + if (bus->bustype == SSB_BUSTYPE_PCI &&
682 + bus->chipco.dev->id.revision >= 31)
683 + return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
684 +
685 return true;
686 }
687 --- a/drivers/ssb/ssb_private.h
688 +++ b/drivers/ssb/ssb_private.h
689 @@ -176,19 +176,27 @@ extern const struct ssb_sprom *ssb_get_f
690
691 /* core.c */
692 extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
693 -extern int ssb_devices_freeze(struct ssb_bus *bus);
694 -extern int ssb_devices_thaw(struct ssb_bus *bus);
695 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
696 int ssb_for_each_bus_call(unsigned long data,
697 int (*func)(struct ssb_bus *bus, unsigned long data));
698 extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
699
700 +struct ssb_freeze_context {
701 + /* Pointer to the bus */
702 + struct ssb_bus *bus;
703 + /* Boolean list to indicate whether a device is frozen on this bus. */
704 + bool device_frozen[SSB_MAX_NR_CORES];
705 +};
706 +extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
707 +extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
708 +
709 +
710
711 /* b43_pci_bridge.c */
712 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
713 extern int __init b43_pci_ssb_bridge_init(void);
714 extern void __exit b43_pci_ssb_bridge_exit(void);
715 -#else /* CONFIG_SSB_B43_PCI_BRIDGR */
716 +#else /* CONFIG_SSB_B43_PCI_BRIDGE */
717 static inline int b43_pci_ssb_bridge_init(void)
718 {
719 return 0;
720 @@ -196,6 +204,6 @@ static inline int b43_pci_ssb_bridge_ini
721 static inline void b43_pci_ssb_bridge_exit(void)
722 {
723 }
724 -#endif /* CONFIG_SSB_PCIHOST */
725 +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
726
727 #endif /* LINUX_SSB_PRIVATE_H_ */
728 --- a/include/linux/ssb/ssb.h
729 +++ b/include/linux/ssb/ssb.h
730 @@ -269,7 +269,8 @@ struct ssb_bus {
731
732 const struct ssb_bus_ops *ops;
733
734 - /* The core in the basic address register window. (PCI bus only) */
735 + /* The core currently mapped into the MMIO window.
736 + * Not valid on all host-buses. So don't use outside of SSB. */
737 struct ssb_device *mapped_device;
738 union {
739 /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
740 @@ -281,14 +282,17 @@ struct ssb_bus {
741 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
742 spinlock_t bar_lock;
743
744 - /* The bus this backplane is running on. */
745 + /* The host-bus this backplane is running on. */
746 enum ssb_bustype bustype;
747 - /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
748 - struct pci_dev *host_pci;
749 - /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
750 - struct pcmcia_device *host_pcmcia;
751 - /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
752 - struct sdio_func *host_sdio;
753 + /* Pointers to the host-bus. Check bustype before using any of these pointers. */
754 + union {
755 + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
756 + struct pci_dev *host_pci;
757 + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
758 + struct pcmcia_device *host_pcmcia;
759 + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
760 + struct sdio_func *host_sdio;
761 + };
762
763 /* See enum ssb_quirks */
764 unsigned int quirks;
765 @@ -393,6 +397,9 @@ extern void ssb_bus_unregister(struct ss
766
767 /* Does the device have an SPROM? */
768 extern bool ssb_is_sprom_available(struct ssb_bus *bus);
769 +
770 +/* Does the device have an SPROM? */
771 +extern bool ssb_is_sprom_available(struct ssb_bus *bus);
772
773 /* Set a fallback SPROM.
774 * See kdoc at the function definition for complete documentation. */
775 --- a/include/linux/ssb/ssb_regs.h
776 +++ b/include/linux/ssb/ssb_regs.h
777 @@ -198,63 +198,63 @@
778 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
779 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
780 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
781 -#define SSB_SPROM1_PA0B0 0x105E
782 -#define SSB_SPROM1_PA0B1 0x1060
783 -#define SSB_SPROM1_PA0B2 0x1062
784 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
785 +#define SSB_SPROM1_PA0B0 0x005E
786 +#define SSB_SPROM1_PA0B1 0x0060
787 +#define SSB_SPROM1_PA0B2 0x0062
788 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
789 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
790 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
791 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
792 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
793 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
794 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
795 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
796 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
797 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
798 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
799 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
800 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
801 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
802 -#define SSB_SPROM1_PA1B0 0x106A
803 -#define SSB_SPROM1_PA1B1 0x106C
804 -#define SSB_SPROM1_PA1B2 0x106E
805 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
806 +#define SSB_SPROM1_PA1B0 0x006A
807 +#define SSB_SPROM1_PA1B1 0x006C
808 +#define SSB_SPROM1_PA1B2 0x006E
809 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
810 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
811 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
812 #define SSB_SPROM1_ITSSI_A_SHIFT 8
813 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
814 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
815 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
816 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
817 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
818 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
819 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
820 #define SSB_SPROM1_AGAIN_A_SHIFT 8
821
822 /* SPROM Revision 2 (inherits from rev 1) */
823 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
824 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
825 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
826 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
827 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
828 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
829 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
830 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
831 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
832 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
833 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
834 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
835 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
836 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
837 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
838 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
839 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
840 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
841 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
842 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
843 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
844 #define SSB_SPROM2_OPO_VALUE 0x00FF
845 #define SSB_SPROM2_OPO_UNUSED 0xFF00
846 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
847 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
848
849 /* SPROM Revision 3 (inherits most data from rev 2) */
850 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
851 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
852 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
853 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
854 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
855 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
856 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
857 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
858 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
859 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
860 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
861 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
862 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
863 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
864 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
865 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
866 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
867 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
868 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
869 @@ -265,100 +265,100 @@
870 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
871
872 /* SPROM Revision 4 */
873 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
874 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
875 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
876 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
877 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
878 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
879 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
880 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
881 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
882 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
883 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
884 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
885 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
886 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
887 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
888 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
889 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
890 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
891 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
892 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
893 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
894 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
895 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
896 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
897 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
898 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
899 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
900 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
901 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
902 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
903 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
904 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
905 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
906 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
907 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
908 #define SSB_SPROM4_AGAIN0_SHIFT 0
909 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
910 #define SSB_SPROM4_AGAIN1_SHIFT 8
911 -#define SSB_SPROM4_AGAIN23 0x1060
912 +#define SSB_SPROM4_AGAIN23 0x0060
913 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
914 #define SSB_SPROM4_AGAIN2_SHIFT 0
915 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
916 #define SSB_SPROM4_AGAIN3_SHIFT 8
917 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
918 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
919 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
920 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
921 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
922 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
923 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
924 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
925 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
926 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
927 #define SSB_SPROM4_ITSSI_A_SHIFT 8
928 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
929 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
930 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
931 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
932 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
933 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
934 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
935 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
936 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
937 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
938 -#define SSB_SPROM4_PA0B2 0x1086
939 -#define SSB_SPROM4_PA1B0 0x108E
940 -#define SSB_SPROM4_PA1B1 0x1090
941 -#define SSB_SPROM4_PA1B2 0x1092
942 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
943 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
944 +#define SSB_SPROM4_PA0B2 0x0086
945 +#define SSB_SPROM4_PA1B0 0x008E
946 +#define SSB_SPROM4_PA1B1 0x0090
947 +#define SSB_SPROM4_PA1B2 0x0092
948
949 /* SPROM Revision 5 (inherits most data from rev 4) */
950 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
951 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
952 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
953 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
954 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
955 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
956 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
957 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
958 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
959 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
960 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
961 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
962 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
963 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
964 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
965 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
966 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
967 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
968
969 /* SPROM Revision 8 */
970 -#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
971 -#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
972 -#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
973 -#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
974 -#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
975 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
976 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
977 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
978 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
979 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
980 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
981 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
982 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
983 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
984 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
985 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
986 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
987 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
988 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
989 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
990 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
991 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
992 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
993 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
994 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
995 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
996 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
997 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
998 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
999 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1000 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1001 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1002 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1003 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
1004 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
1005 #define SSB_SPROM8_AGAIN0_SHIFT 0
1006 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
1007 #define SSB_SPROM8_AGAIN1_SHIFT 8
1008 -#define SSB_SPROM8_AGAIN23 0x10A0
1009 +#define SSB_SPROM8_AGAIN23 0x00A0
1010 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
1011 #define SSB_SPROM8_AGAIN2_SHIFT 0
1012 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
1013 #define SSB_SPROM8_AGAIN3_SHIFT 8
1014 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
1015 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1016 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1017 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1018 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
1019 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1020 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1021 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
1022 -#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
1023 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
1024 #define SSB_SPROM8_RSSISMF2G 0x000F
1025 #define SSB_SPROM8_RSSISMC2G 0x00F0
1026 #define SSB_SPROM8_RSSISMC2G_SHIFT 4
1027 @@ -366,7 +366,7 @@
1028 #define SSB_SPROM8_RSSISAV2G_SHIFT 8
1029 #define SSB_SPROM8_BXA2G 0x1800
1030 #define SSB_SPROM8_BXA2G_SHIFT 11
1031 -#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
1032 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
1033 #define SSB_SPROM8_RSSISMF5G 0x000F
1034 #define SSB_SPROM8_RSSISMC5G 0x00F0
1035 #define SSB_SPROM8_RSSISMC5G_SHIFT 4
1036 @@ -374,47 +374,47 @@
1037 #define SSB_SPROM8_RSSISAV5G_SHIFT 8
1038 #define SSB_SPROM8_BXA5G 0x1800
1039 #define SSB_SPROM8_BXA5G_SHIFT 11
1040 -#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
1041 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
1042 #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
1043 #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
1044 #define SSB_SPROM8_TRI5G_SHIFT 8
1045 -#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
1046 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
1047 #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
1048 #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
1049 #define SSB_SPROM8_TRI5GH_SHIFT 8
1050 -#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
1051 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
1052 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
1053 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
1054 #define SSB_SPROM8_RXPO5G_SHIFT 8
1055 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
1056 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1057 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1058 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1059 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
1060 -#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
1061 -#define SSB_SPROM8_PA0B1 0x10C4
1062 -#define SSB_SPROM8_PA0B2 0x10C6
1063 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
1064 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
1065 +#define SSB_SPROM8_PA0B1 0x00C4
1066 +#define SSB_SPROM8_PA0B2 0x00C6
1067 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
1068 #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
1069 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
1070 #define SSB_SPROM8_ITSSI_A_SHIFT 8
1071 -#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
1072 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
1073 #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
1074 #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
1075 #define SSB_SPROM8_MAXP_AL_SHIFT 8
1076 -#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
1077 -#define SSB_SPROM8_PA1B1 0x10CE
1078 -#define SSB_SPROM8_PA1B2 0x10D0
1079 -#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
1080 -#define SSB_SPROM8_PA1LOB1 0x10D4
1081 -#define SSB_SPROM8_PA1LOB2 0x10D6
1082 -#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
1083 -#define SSB_SPROM8_PA1HIB1 0x10DA
1084 -#define SSB_SPROM8_PA1HIB2 0x10DC
1085 -#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
1086 -#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
1087 -#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
1088 -#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
1089 -#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
1090 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
1091 +#define SSB_SPROM8_PA1B1 0x00CE
1092 +#define SSB_SPROM8_PA1B2 0x00D0
1093 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
1094 +#define SSB_SPROM8_PA1LOB1 0x00D4
1095 +#define SSB_SPROM8_PA1LOB2 0x00D6
1096 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1097 +#define SSB_SPROM8_PA1HIB1 0x00DA
1098 +#define SSB_SPROM8_PA1HIB2 0x00DC
1099 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1100 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1101 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1102 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1103 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1104
1105 /* Values for SSB_SPROM1_BINF_CCODE */
1106 enum {
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