target/linux/generic/hack-6.6/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch

   1 From 5f62951fba63a9f9cfff564209426bdea5fcc371 Mon Sep 17 00:00:00 2001
   2 From: Alex Marginean <alexandru.marginean@nxp.com>
   3 Date: Tue, 27 Aug 2019 15:16:56 +0300
   4 Subject: [PATCH] drivers: net: phy: aquantia: enable AQR112 and AQR412
   5
   6 Adds support for AQR112 and AQR412 which is mostly based on existing code
   7 with the addition of code configuring the protocol on system side.
   8 This allows changing the system side protocol without having to deploy a
   9 different firmware on the PHY.
  10
  11 Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  12 ---
  13  drivers/net/phy/aquantia/aquantia_main.c | 88 +++++++++++++++++++++++++++++++++++++++++
  14  1 file changed, 88 insertions(+)
  15
  16 --- a/drivers/net/phy/aquantia/aquantia_main.c
  17 +++ b/drivers/net/phy/aquantia/aquantia_main.c
  18 @@ -101,6 +101,29 @@
  19  #define AQR107_OP_IN_PROG_SLEEP                1000
  20  #define AQR107_OP_IN_PROG_TIMEOUT      100000
  21
  22 +/* registers in MDIO_MMD_VEND1 region */
  23 +#define AQUANTIA_VND1_GLOBAL_SC                        0x000
  24 +#define  AQUANTIA_VND1_GLOBAL_SC_LP            BIT(0xb)
  25 +
  26 +/* global start rate, the protocol associated with this speed is used by default
  27 + * on SI.
  28 + */
  29 +#define AQUANTIA_VND1_GSTART_RATE              0x31a
  30 +#define  AQUANTIA_VND1_GSTART_RATE_OFF         0
  31 +#define  AQUANTIA_VND1_GSTART_RATE_100M                1
  32 +#define  AQUANTIA_VND1_GSTART_RATE_1G          2
  33 +#define  AQUANTIA_VND1_GSTART_RATE_10G         3
  34 +#define  AQUANTIA_VND1_GSTART_RATE_2_5G                4
  35 +#define  AQUANTIA_VND1_GSTART_RATE_5G          5
  36 +
  37 +/* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
  38 +#define AQUANTIA_VND1_GSYSCFG_BASE             0x31b
  39 +#define AQUANTIA_VND1_GSYSCFG_100M             0
  40 +#define AQUANTIA_VND1_GSYSCFG_1G               1
  41 +#define AQUANTIA_VND1_GSYSCFG_2_5G             2
  42 +#define AQUANTIA_VND1_GSYSCFG_5G               3
  43 +#define AQUANTIA_VND1_GSYSCFG_10G              4
  44 +
  45  struct aqr107_hw_stat {
  46         const char *name;
  47         int reg;
  48 @@ -232,6 +255,51 @@ static int aqr_config_aneg(struct phy_de
  49         return genphy_c45_check_and_restart_aneg(phydev, changed);
  50  }
  51
  52 +static struct {
  53 +       u16 syscfg;
  54 +       int cnt;
  55 +       u16 start_rate;
  56 +} aquantia_syscfg[PHY_INTERFACE_MODE_MAX] = {
  57 +       [PHY_INTERFACE_MODE_SGMII] =      {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
  58 +                                          AQUANTIA_VND1_GSTART_RATE_1G},
  59 +       [PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
  60 +                                          AQUANTIA_VND1_GSTART_RATE_2_5G},
  61 +       [PHY_INTERFACE_MODE_XGMII] =      {0x100, AQUANTIA_VND1_GSYSCFG_10G,
  62 +                                          AQUANTIA_VND1_GSTART_RATE_10G},
  63 +       [PHY_INTERFACE_MODE_USXGMII] =    {0x080, AQUANTIA_VND1_GSYSCFG_10G,
  64 +                                          AQUANTIA_VND1_GSTART_RATE_10G},
  65 +};
  66 +
  67 +/* Sets up protocol on system side before calling aqr_config_aneg */
  68 +static int aqr_config_aneg_set_prot(struct phy_device *phydev)
  69 +{
  70 +       int if_type = phydev->interface;
  71 +       int i;
  72 +
  73 +       if (!aquantia_syscfg[if_type].cnt)
  74 +               return 0;
  75 +
  76 +       /* set PHY in low power mode so we can configure protocols */
  77 +       phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,
  78 +                     AQUANTIA_VND1_GLOBAL_SC_LP);
  79 +       mdelay(10);
  80 +
  81 +       /* set the default rate to enable the SI link */
  82 +       phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
  83 +                     aquantia_syscfg[if_type].start_rate);
  84 +
  85 +       for (i = 0; i <= aquantia_syscfg[if_type].cnt; i++)
  86 +               phy_write_mmd(phydev, MDIO_MMD_VEND1,
  87 +                             AQUANTIA_VND1_GSYSCFG_BASE + i,
  88 +                             aquantia_syscfg[if_type].syscfg);
  89 +
  90 +       /* wake PHY back up */
  91 +       phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
  92 +       mdelay(10);
  93 +
  94 +       return aqr_config_aneg(phydev);
  95 +}
  96 +
  97  static int aqr_config_intr(struct phy_device *phydev)
  98  {
  99         bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
 100 @@ -809,7 +877,7 @@ static struct phy_driver aqr_driver[] =
 101         PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
 102         .name           = "Aquantia AQR112",
 103         .probe          = aqr107_probe,
 104 -       .config_aneg    = aqr_config_aneg,
 105 +       .config_aneg    = aqr_config_aneg_set_prot,
 106         .config_intr    = aqr_config_intr,
 107         .handle_interrupt = aqr_handle_interrupt,
 108         .get_tunable    = aqr107_get_tunable,
 109 @@ -827,7 +895,7 @@ static struct phy_driver aqr_driver[] =
 110         PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
 111         .name           = "Aquantia AQR412",
 112         .probe          = aqr107_probe,
 113 -       .config_aneg    = aqr_config_aneg,
 114 +       .config_aneg    = aqr_config_aneg_set_prot,
 115         .config_intr    = aqr_config_intr,
 116         .handle_interrupt = aqr_handle_interrupt,
 117         .get_tunable    = aqr107_get_tunable,