target/linux/generic/hack-6.1/765-mxl-gpy-control-LED-reg-from-DT.patch

   1 From 94b90966095f3fa625897e8f53d215882f6e19b3 Mon Sep 17 00:00:00 2001
   2 From: David Bauer <mail@david-bauer.net>
   3 Date: Sat, 11 Mar 2023 17:00:01 +0100
   4 Subject: [PATCH] mxl-gpy: control LED reg from DT
   5
   6 Add dynamic configuration for the LED control registers on MXL PHYs.
   7
   8 This patch has been tested with MaxLinear GPY211C. It is unlikely to be
   9 accepted upstream, as upstream plans on integrating their own framework
  10 for handling these LEDs.
  11
  12 For the time being, use this hack to configure PHY driven device-LEDs to
  13 show the correct state.
  14
  15 A possible alternative might be to expose the LEDs using the kernel LED
  16 framework and bind it to the netdevice. This might also be upstreamable,
  17 although it is a considerable extra amount of work.
  18
  19 Signed-off-by: David Bauer <mail@david-bauer.net>
  20 ---
  21  drivers/net/phy/mxl-gpy.c | 37 ++++++++++++++++++++++++++++++++++++-
  22  1 file changed, 36 insertions(+), 1 deletion(-)
  23
  24 --- a/drivers/net/phy/mxl-gpy.c
  25 +++ b/drivers/net/phy/mxl-gpy.c
  26 @@ -10,6 +10,7 @@
  27  #include <linux/bitfield.h>
  28  #include <linux/hwmon.h>
  29  #include <linux/mutex.h>
  30 +#include <linux/of.h>
  31  #include <linux/phy.h>
  32  #include <linux/polynomial.h>
  33  #include <linux/netdevice.h>
  34 @@ -33,6 +34,7 @@
  35  #define PHY_MIISTAT            0x18    /* MII state */
  36  #define PHY_IMASK              0x19    /* interrupt mask */
  37  #define PHY_ISTAT              0x1A    /* interrupt status */
  38 +#define PHY_LED                        0x1B    /* LED control */
  39  #define PHY_FWV                        0x1E    /* firmware version */
  40
  41  #define PHY_MIISTAT_SPD_MASK   GENMASK(2, 0)
  42 @@ -56,10 +58,15 @@
  43                                  PHY_IMASK_ADSC | \
  44                                  PHY_IMASK_ANC)
  45
  46 +#define PHY_LED_NUM_LEDS       4
  47 +
  48  #define PHY_FWV_REL_MASK       BIT(15)
  49  #define PHY_FWV_MAJOR_MASK     GENMASK(11, 8)
  50  #define PHY_FWV_MINOR_MASK     GENMASK(7, 0)
  51
  52 +/* LED */
  53 +#define VSPEC1_LED(x)          (0x1 + x)
  54 +
  55  /* SGMII */
  56  #define VSPEC1_SGMII_CTRL      0x08
  57  #define VSPEC1_SGMII_CTRL_ANEN BIT(12)         /* Aneg enable */
  58 @@ -241,6 +248,31 @@ out:
  59         return ret;
  60  }
  61
  62 +static int gpy_led_write(struct phy_device *phydev)
  63 +{
  64 +       struct device_node *node = phydev->mdio.dev.of_node;
  65 +       u32 led_regs[PHY_LED_NUM_LEDS];
  66 +       int i, ret;
  67 +
  68 +       if (!IS_ENABLED(CONFIG_OF_MDIO))
  69 +               return 0;
  70 +
  71 +       if (of_property_read_u32_array(node, "mxl,led-config", led_regs, PHY_LED_NUM_LEDS))
  72 +               return 0;
  73 +
  74 +       /* Enable LED function handling on all ports*/
  75 +       phy_write(phydev, PHY_LED, 0xFF00);
  76 +
  77 +       /* Write LED register values */
  78 +       for (i = 0; i < PHY_LED_NUM_LEDS; i++) {
  79 +               ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_LED(i), (u16)led_regs[i]);
  80 +               if (ret < 0)
  81 +                       return ret;
  82 +       }
  83 +
  84 +       return 0;
  85 +}
  86 +
  87  static int gpy_config_init(struct phy_device *phydev)
  88  {
  89         int ret;
  90 @@ -252,7 +284,10 @@ static int gpy_config_init(struct phy_de
  91
  92         /* Clear all pending interrupts */
  93         ret = phy_read(phydev, PHY_ISTAT);
  94 -       return ret < 0 ? ret : 0;
  95 +       if (ret < 0)
  96 +               return ret;
  97 +
  98 +       return gpy_led_write(phydev);
  99  }
 100
 101  static bool gpy_has_broken_mdint(struct phy_device *phydev)