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[openwrt/staging/pepe2k.git] / target / linux / generic / files / drivers / ssb / fallback-sprom.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * SSB Fallback SPROM Driver
4 *
5 * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
6 * Copyright (C) 2014 Jonas Gorski <jonas.gorski@gmail.com>
7 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
8 * Copyright (C) 2008 Florian Fainelli <f.fainelli@gmail.com>
9 */
10
11 #include <linux/etherdevice.h>
12 #include <linux/firmware.h>
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/of_net.h>
17 #include <linux/of_platform.h>
18 #include <linux/ssb/ssb.h>
19
20 #define SSB_FBS_MAX_SIZE 440
21
22 /* Get the word-offset for a SSB_SPROM_XXX define. */
23 #define SPOFF(offset) ((offset) / sizeof(u16))
24 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
25 #define SPEX16(_outvar, _offset, _mask, _shift) \
26 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
27 #define SPEX32(_outvar, _offset, _mask, _shift) \
28 out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
29 in[SPOFF(_offset)]) & (_mask)) >> (_shift))
30 #define SPEX(_outvar, _offset, _mask, _shift) \
31 SPEX16(_outvar, _offset, _mask, _shift)
32
33 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
34 do { \
35 SPEX(_field[0], _offset + 0, _mask, _shift); \
36 SPEX(_field[1], _offset + 2, _mask, _shift); \
37 SPEX(_field[2], _offset + 4, _mask, _shift); \
38 SPEX(_field[3], _offset + 6, _mask, _shift); \
39 SPEX(_field[4], _offset + 8, _mask, _shift); \
40 SPEX(_field[5], _offset + 10, _mask, _shift); \
41 SPEX(_field[6], _offset + 12, _mask, _shift); \
42 SPEX(_field[7], _offset + 14, _mask, _shift); \
43 } while (0)
44
45 struct ssb_fbs {
46 struct device *dev;
47 struct list_head list;
48 struct ssb_sprom sprom;
49 u32 pci_bus;
50 u32 pci_dev;
51 bool devid_override;
52 };
53
54 static DEFINE_SPINLOCK(ssb_fbs_lock);
55 static struct list_head ssb_fbs_list = LIST_HEAD_INIT(ssb_fbs_list);
56
57 int ssb_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
58 {
59 const u32 pci_bus = bus->host_pci->bus->number;
60 const u32 pci_dev = PCI_SLOT(bus->host_pci->devfn);
61 struct ssb_fbs *pos;
62
63 list_for_each_entry(pos, &ssb_fbs_list, list) {
64 if (pos->pci_bus != pci_bus ||
65 pos->pci_dev != pci_dev)
66 continue;
67
68 if (pos->devid_override)
69 bus->host_pci->device = pos->sprom.dev_id;
70
71 memcpy(out, &pos->sprom, sizeof(struct ssb_sprom));
72 dev_info(pos->dev, "requested by [%x:%x]",
73 pos->pci_bus, pos->pci_dev);
74
75 return 0;
76 }
77
78 pr_err("unable to fill SPROM for [%x:%x]\n", pci_bus, pci_dev);
79
80 return -EINVAL;
81 }
82
83 static s8 sprom_extract_antgain(u8 sprom_revision, const u16 *in, u16 offset,
84 u16 mask, u16 shift)
85 {
86 u16 v;
87 u8 gain;
88
89 v = in[SPOFF(offset)];
90 gain = (v & mask) >> shift;
91 if (gain == 0xFF)
92 gain = 2; /* If unset use 2dBm */
93 if (sprom_revision == 1) {
94 /* Convert to Q5.2 */
95 gain <<= 2;
96 } else {
97 /* Q5.2 Fractional part is stored in 0xC0 */
98 gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
99 }
100
101 return (s8)gain;
102 }
103
104 static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
105 {
106 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
107 SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
108 SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
109 SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
110 SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
111 SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
112 SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
113 SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
114 SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
115 SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
116 SSB_SPROM2_MAXP_A_LO_SHIFT);
117 }
118
119 static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
120 {
121 SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
122 SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
123 SSB_SPROM1_ETHPHY_ET1A_SHIFT);
124 SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
125 SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
126 SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
127 SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
128 if (out->revision == 1)
129 SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
130 SSB_SPROM1_BINF_CCODE_SHIFT);
131 SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
132 SSB_SPROM1_BINF_ANTA_SHIFT);
133 SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
134 SSB_SPROM1_BINF_ANTBG_SHIFT);
135 SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
136 SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
137 SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
138 SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
139 SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
140 SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
141 SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
142 SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
143 SSB_SPROM1_GPIOA_P1_SHIFT);
144 SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
145 SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
146 SSB_SPROM1_GPIOB_P3_SHIFT);
147 SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A,
148 SSB_SPROM1_MAXPWR_A_SHIFT);
149 SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0);
150 SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A,
151 SSB_SPROM1_ITSSI_A_SHIFT);
152 SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
153 SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
154
155 SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
156 SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
157
158 /* Extract the antenna gain values. */
159 out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
160 SSB_SPROM1_AGAIN,
161 SSB_SPROM1_AGAIN_BG,
162 SSB_SPROM1_AGAIN_BG_SHIFT);
163 out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
164 SSB_SPROM1_AGAIN,
165 SSB_SPROM1_AGAIN_A,
166 SSB_SPROM1_AGAIN_A_SHIFT);
167 if (out->revision >= 2)
168 sprom_extract_r23(out, in);
169 }
170
171 /* Revs 4 5 and 8 have partially shared layout */
172 static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
173 {
174 SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
175 SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
176 SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
177 SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
178 SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
179 SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
180 SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
181 SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
182
183 SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
184 SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
185 SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
186 SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
187 SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
188 SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
189 SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
190 SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
191
192 SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
193 SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
194 SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
195 SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
196 SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
197 SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
198 SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
199 SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
200
201 SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
202 SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
203 SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
204 SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
205 SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
206 SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
207 SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
208 SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
209 }
210
211 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
212 {
213 static const u16 pwr_info_offset[] = {
214 SSB_SPROM4_PWR_INFO_CORE0, SSB_SPROM4_PWR_INFO_CORE1,
215 SSB_SPROM4_PWR_INFO_CORE2, SSB_SPROM4_PWR_INFO_CORE3
216 };
217 int i;
218
219 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
220 ARRAY_SIZE(out->core_pwr_info));
221
222 SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
223 SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
224 SSB_SPROM4_ETHPHY_ET1A_SHIFT);
225 SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
226 SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
227 if (out->revision == 4) {
228 SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
229 SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
230 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
231 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
232 SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
233 SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
234 } else {
235 SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
236 SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
237 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
238 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
239 SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
240 SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
241 }
242 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
243 SSB_SPROM4_ANTAVAIL_A_SHIFT);
244 SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG,
245 SSB_SPROM4_ANTAVAIL_BG_SHIFT);
246 SPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0);
247 SPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG,
248 SSB_SPROM4_ITSSI_BG_SHIFT);
249 SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0);
250 SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A,
251 SSB_SPROM4_ITSSI_A_SHIFT);
252 if (out->revision == 4) {
253 SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);
254 SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,
255 SSB_SPROM4_GPIOA_P1_SHIFT);
256 SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);
257 SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,
258 SSB_SPROM4_GPIOB_P3_SHIFT);
259 } else {
260 SPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0);
261 SPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1,
262 SSB_SPROM5_GPIOA_P1_SHIFT);
263 SPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0);
264 SPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3,
265 SSB_SPROM5_GPIOB_P3_SHIFT);
266 }
267
268 /* Extract the antenna gain values. */
269 out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
270 SSB_SPROM4_AGAIN01,
271 SSB_SPROM4_AGAIN0,
272 SSB_SPROM4_AGAIN0_SHIFT);
273 out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
274 SSB_SPROM4_AGAIN01,
275 SSB_SPROM4_AGAIN1,
276 SSB_SPROM4_AGAIN1_SHIFT);
277 out->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,
278 SSB_SPROM4_AGAIN23,
279 SSB_SPROM4_AGAIN2,
280 SSB_SPROM4_AGAIN2_SHIFT);
281 out->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,
282 SSB_SPROM4_AGAIN23,
283 SSB_SPROM4_AGAIN3,
284 SSB_SPROM4_AGAIN3_SHIFT);
285
286 /* Extract cores power info info */
287 for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
288 u16 o = pwr_info_offset[i];
289
290 SPEX(core_pwr_info[i].itssi_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,
291 SSB_SPROM4_2G_ITSSI, SSB_SPROM4_2G_ITSSI_SHIFT);
292 SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,
293 SSB_SPROM4_2G_MAXP, 0);
294
295 SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SPROM4_2G_PA_0, ~0, 0);
296 SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SPROM4_2G_PA_1, ~0, 0);
297 SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SPROM4_2G_PA_2, ~0, 0);
298 SPEX(core_pwr_info[i].pa_2g[3], o + SSB_SPROM4_2G_PA_3, ~0, 0);
299
300 SPEX(core_pwr_info[i].itssi_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,
301 SSB_SPROM4_5G_ITSSI, SSB_SPROM4_5G_ITSSI_SHIFT);
302 SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,
303 SSB_SPROM4_5G_MAXP, 0);
304 SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM4_5GHL_MAXP,
305 SSB_SPROM4_5GH_MAXP, 0);
306 SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM4_5GHL_MAXP,
307 SSB_SPROM4_5GL_MAXP, SSB_SPROM4_5GL_MAXP_SHIFT);
308
309 SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SPROM4_5GL_PA_0, ~0, 0);
310 SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SPROM4_5GL_PA_1, ~0, 0);
311 SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SPROM4_5GL_PA_2, ~0, 0);
312 SPEX(core_pwr_info[i].pa_5gl[3], o + SSB_SPROM4_5GL_PA_3, ~0, 0);
313 SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SPROM4_5G_PA_0, ~0, 0);
314 SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SPROM4_5G_PA_1, ~0, 0);
315 SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SPROM4_5G_PA_2, ~0, 0);
316 SPEX(core_pwr_info[i].pa_5g[3], o + SSB_SPROM4_5G_PA_3, ~0, 0);
317 SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SPROM4_5GH_PA_0, ~0, 0);
318 SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SPROM4_5GH_PA_1, ~0, 0);
319 SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SPROM4_5GH_PA_2, ~0, 0);
320 SPEX(core_pwr_info[i].pa_5gh[3], o + SSB_SPROM4_5GH_PA_3, ~0, 0);
321 }
322
323 sprom_extract_r458(out, in);
324
325 /* TODO - get remaining rev 4 stuff needed */
326 }
327
328 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
329 {
330 int i;
331 u16 o;
332 static const u16 pwr_info_offset[] = {
333 SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
334 SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
335 };
336 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
337 ARRAY_SIZE(out->core_pwr_info));
338
339 SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
340 SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
341 SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
342 SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
343 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
344 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
345 SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
346 SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
347 SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
348 SSB_SPROM8_ANTAVAIL_A_SHIFT);
349 SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
350 SSB_SPROM8_ANTAVAIL_BG_SHIFT);
351 SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
352 SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
353 SSB_SPROM8_ITSSI_BG_SHIFT);
354 SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
355 SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
356 SSB_SPROM8_ITSSI_A_SHIFT);
357 SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
358 SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
359 SSB_SPROM8_MAXP_AL_SHIFT);
360 SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
361 SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
362 SSB_SPROM8_GPIOA_P1_SHIFT);
363 SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
364 SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
365 SSB_SPROM8_GPIOB_P3_SHIFT);
366 SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
367 SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
368 SSB_SPROM8_TRI5G_SHIFT);
369 SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
370 SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
371 SSB_SPROM8_TRI5GH_SHIFT);
372 SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
373 SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
374 SSB_SPROM8_RXPO5G_SHIFT);
375 SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
376 SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
377 SSB_SPROM8_RSSISMC2G_SHIFT);
378 SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
379 SSB_SPROM8_RSSISAV2G_SHIFT);
380 SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
381 SSB_SPROM8_BXA2G_SHIFT);
382 SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
383 SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
384 SSB_SPROM8_RSSISMC5G_SHIFT);
385 SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
386 SSB_SPROM8_RSSISAV5G_SHIFT);
387 SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
388 SSB_SPROM8_BXA5G_SHIFT);
389 SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
390 SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
391 SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
392 SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
393 SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
394 SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
395 SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
396 SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
397 SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
398 SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
399 SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
400 SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
401 SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
402 SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
403 SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
404 SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
405 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
406
407 /* Extract the antenna gain values. */
408 out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
409 SSB_SPROM8_AGAIN01,
410 SSB_SPROM8_AGAIN0,
411 SSB_SPROM8_AGAIN0_SHIFT);
412 out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
413 SSB_SPROM8_AGAIN01,
414 SSB_SPROM8_AGAIN1,
415 SSB_SPROM8_AGAIN1_SHIFT);
416 out->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,
417 SSB_SPROM8_AGAIN23,
418 SSB_SPROM8_AGAIN2,
419 SSB_SPROM8_AGAIN2_SHIFT);
420 out->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,
421 SSB_SPROM8_AGAIN23,
422 SSB_SPROM8_AGAIN3,
423 SSB_SPROM8_AGAIN3_SHIFT);
424
425 /* Extract cores power info info */
426 for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
427 o = pwr_info_offset[i];
428 SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
429 SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
430 SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
431 SSB_SPROM8_2G_MAXP, 0);
432
433 SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
434 SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
435 SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
436
437 SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
438 SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
439 SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
440 SSB_SPROM8_5G_MAXP, 0);
441 SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
442 SSB_SPROM8_5GH_MAXP, 0);
443 SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
444 SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
445
446 SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
447 SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
448 SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
449 SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
450 SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
451 SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
452 SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
453 SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
454 SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
455 }
456
457 /* Extract FEM info */
458 SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
459 SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
460 SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
461 SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
462 SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
463 SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
464 SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
465 SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
466 SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
467 SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
468
469 SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
470 SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
471 SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
472 SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
473 SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
474 SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
475 SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
476 SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
477 SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
478 SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
479
480 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
481 SSB_SPROM8_LEDDC_ON_SHIFT);
482 SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
483 SSB_SPROM8_LEDDC_OFF_SHIFT);
484
485 SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
486 SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
487 SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
488 SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
489 SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
490 SSB_SPROM8_TXRXC_SWITCH_SHIFT);
491
492 SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
493
494 SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
495 SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
496 SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
497 SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
498
499 SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
500 SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
501 SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
502 SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
503 SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
504 SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
505 SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
506 SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
507 SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
508 SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
509 SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
510 SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
511 SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
512 SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
513 SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
514 SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
515 SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
516 SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
517 SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
518 SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
519
520 SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
521 SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
522 SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
523 SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
524
525 SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
526 SSB_SPROM8_THERMAL_TRESH_SHIFT);
527 SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
528 SSB_SPROM8_THERMAL_OFFSET_SHIFT);
529 SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
530 SSB_SPROM8_TEMPDELTA_PHYCAL,
531 SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
532 SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
533 SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
534 SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
535 SSB_SPROM8_TEMPDELTA_HYSTERESIS,
536 SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
537 sprom_extract_r458(out, in);
538
539 /* TODO - get remaining rev 8 stuff needed */
540 }
541
542 static int sprom_extract(struct ssb_fbs *priv, const u16 *in, u16 size)
543 {
544 struct ssb_sprom *out = &priv->sprom;
545
546 memset(out, 0, sizeof(*out));
547
548 out->revision = in[size - 1] & 0x00FF;
549
550 switch (out->revision) {
551 case 1:
552 case 2:
553 case 3:
554 sprom_extract_r123(out, in);
555 break;
556 case 4:
557 case 5:
558 sprom_extract_r45(out, in);
559 break;
560 case 8:
561 sprom_extract_r8(out, in);
562 break;
563 default:
564 dev_warn(priv->dev,
565 "Unsupported SPROM revision %d detected."
566 " Will extract v1\n",
567 out->revision);
568 out->revision = 1;
569 sprom_extract_r123(out, in);
570 }
571
572 if (out->boardflags_lo == 0xFFFF)
573 out->boardflags_lo = 0; /* per specs */
574 if (out->boardflags_hi == 0xFFFF)
575 out->boardflags_hi = 0; /* per specs */
576
577 return 0;
578 }
579
580 static void ssb_fbs_fixup(struct ssb_fbs *priv, u16 *sprom)
581 {
582 struct device_node *node = priv->dev->of_node;
583 u32 fixups, off, val;
584 int i = 0;
585
586 if (!of_get_property(node, "brcm,sprom-fixups", &fixups))
587 return;
588
589 fixups /= sizeof(u32);
590
591 dev_info(priv->dev, "patching SPROM with %u fixups...\n", fixups >> 1);
592
593 while (i < fixups) {
594 if (of_property_read_u32_index(node, "brcm,sprom-fixups",
595 i++, &off)) {
596 dev_err(priv->dev, "error reading fixup[%u] offset\n",
597 i - 1);
598 return;
599 }
600
601 if (of_property_read_u32_index(node, "brcm,sprom-fixups",
602 i++, &val)) {
603 dev_err(priv->dev, "error reading fixup[%u] value\n",
604 i - 1);
605 return;
606 }
607
608 dev_dbg(priv->dev, "fixup[%d]=0x%04x\n", off, val);
609
610 sprom[off] = val;
611 }
612 }
613
614 static bool sprom_override_devid(struct ssb_fbs *priv, struct ssb_sprom *out,
615 const u16 *in)
616 {
617 SPEX(dev_id, SSB_SPROM1_PID, 0xFFFF, 0);
618 return !!out->dev_id;
619 }
620
621 static int ssb_fbs_set(struct ssb_fbs *priv, struct device_node *node)
622 {
623 struct ssb_sprom *sprom = &priv->sprom;
624 const struct firmware *fw;
625 const char *sprom_name;
626 int err;
627
628 if (of_property_read_string(node, "brcm,sprom", &sprom_name))
629 sprom_name = NULL;
630
631 if (sprom_name) {
632 err = request_firmware_direct(&fw, sprom_name, priv->dev);
633 if (err)
634 dev_err(priv->dev, "%s load error\n", sprom_name);
635 } else {
636 err = -ENOENT;
637 }
638
639 if (err) {
640 sprom->revision = 0x02;
641 sprom->board_rev = 0x0017;
642 sprom->country_code = 0x00;
643 sprom->ant_available_bg = 0x03;
644 sprom->pa0b0 = 0x15ae;
645 sprom->pa0b1 = 0xfa85;
646 sprom->pa0b2 = 0xfe8d;
647 sprom->pa1b0 = 0xffff;
648 sprom->pa1b1 = 0xffff;
649 sprom->pa1b2 = 0xffff;
650 sprom->gpio0 = 0xff;
651 sprom->gpio1 = 0xff;
652 sprom->gpio2 = 0xff;
653 sprom->gpio3 = 0xff;
654 sprom->maxpwr_bg = 0x4c;
655 sprom->itssi_bg = 0x00;
656 sprom->boardflags_lo = 0x2848;
657 sprom->boardflags_hi = 0x0000;
658 priv->devid_override = false;
659
660 dev_warn(priv->dev, "using basic SPROM\n");
661 } else {
662 size_t size = min(fw->size, (size_t) SSB_FBS_MAX_SIZE);
663 u16 tmp_sprom[SSB_FBS_MAX_SIZE >> 1];
664 u32 i, j;
665
666 for (i = 0, j = 0; i < size; i += 2, j++)
667 tmp_sprom[j] = (fw->data[i] << 8) | fw->data[i + 1];
668
669 release_firmware(fw);
670 ssb_fbs_fixup(priv, tmp_sprom);
671 sprom_extract(priv, tmp_sprom, size >> 1);
672
673 priv->devid_override = sprom_override_devid(priv, sprom,
674 tmp_sprom);
675 }
676
677 return 0;
678 }
679
680 static int ssb_fbs_probe(struct platform_device *pdev)
681 {
682 struct device *dev = &pdev->dev;
683 struct device_node *node = dev->of_node;
684 struct ssb_fbs *priv;
685 unsigned long flags;
686 u8 mac[ETH_ALEN];
687
688 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
689 if (!priv)
690 return -ENOMEM;
691
692 priv->dev = dev;
693
694 ssb_fbs_set(priv, node);
695
696 of_property_read_u32(node, "pci-bus", &priv->pci_bus);
697 of_property_read_u32(node, "pci-dev", &priv->pci_dev);
698
699 of_get_mac_address(node, mac);
700 if (is_valid_ether_addr(mac)) {
701 dev_info(dev, "mtd mac %pM\n", mac);
702 } else {
703 random_ether_addr(mac);
704 dev_info(dev, "random mac %pM\n", mac);
705 }
706
707 memcpy(priv->sprom.il0mac, mac, ETH_ALEN);
708 memcpy(priv->sprom.et0mac, mac, ETH_ALEN);
709 memcpy(priv->sprom.et1mac, mac, ETH_ALEN);
710 memcpy(priv->sprom.et2mac, mac, ETH_ALEN);
711
712 spin_lock_irqsave(&ssb_fbs_lock, flags);
713 list_add(&priv->list, &ssb_fbs_list);
714 spin_unlock_irqrestore(&ssb_fbs_lock, flags);
715
716 dev_info(dev, "registered SPROM for [%x:%x]\n",
717 priv->pci_bus, priv->pci_dev);
718
719 return 0;
720 }
721
722 static const struct of_device_id ssb_fbs_of_match[] = {
723 { .compatible = "brcm,ssb-sprom", },
724 { /* sentinel */ }
725 };
726 MODULE_DEVICE_TABLE(of, ssb_fbs_of_match);
727
728 static struct platform_driver ssb_fbs_driver = {
729 .probe = ssb_fbs_probe,
730 .driver = {
731 .name = "ssb-sprom",
732 .of_match_table = ssb_fbs_of_match,
733 },
734 };
735
736 int __init ssb_fbs_register(void)
737 {
738 return platform_driver_register(&ssb_fbs_driver);
739 }
Staging tree of Piotr Dymacz